Power-Up Circuit for Field Programmable Gate Arrays

The present invention relates to application specific integrated circuits, and more particularly to field programmable gate arrays, and even more particularly to a circuit for preventing current spikes during power up of a field programmable gate array.

A field programmable gate array (FPGA) is a versatile integrated circuit chip, the internal circuitry of which may be configured before packaging by a manufacturer or after packaging by an individual user to realize a user-specific circuit. To configure an FPGA, the user typically configures an on-chip interconnect structure of the FPGA so that selected circuit components in logic modules of the FPGA are electrically connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. In an FPGA employing, for example, amorphous silicon antifuses, selected amorphous silicon antifuses electrically disposed between selected routing conductors in the interconnect structure are "programmed" to connect the selected routing conductors together electrically. Which antifuses are programmed and which antifuses are left unprogrammed determines how the circuit components of the numerous logic modules are interconnected and therefore determines the resulting circuit. FPGAs can employ other types of antifuse structures including, for example, antifuses employing nitrides and oxides. For further details on FPGAs and antifuses, see U.S. Pat. Nos. 5,557,136, 5,544,070, and 5,220,213 all of which are incorporated herein in their entirety.

FIG. 1 (Prior Art) is a simplified illustration of a first logic module 101, an output of which is connected to an input of a second logic module 102 by programmed antifuses 104 and routing conductors 106 of the interconnect structure. Logic module 102 includes a NAND gate 116 shown in detail in FIG. 2 (Prior Art). The seven inputs of NAND gate 116 are labeled 1-7. Transistors 110 and 114 are high voltage protection transistors provided to prevent high voltages present on the interconnect structure during antifuse programming from damaging the logic transistors of the circuit 108 (in this case an inverter) of the logic module output. Protection transistors 110 and 114 are nonconductive during antifuse programming and are conductive during normal circuit operation.

During power up of the FPGA during normal circuit operation (after the FPGA has been programmed and when it is being used by the user), outputs of logic modules which are to supply digital logic HIGHs during the power up period may actually only supply an intermediate voltage. FIG. 3 is a waveform diagram showing the supply voltage V.sub.CC 115 increasing during the power up period. Supply voltage V.sub.CC is supplied to the gate of protection transistor 115 so that protection transistor 115 will be conductive during normal operation so that the output of inverter 108 will be coupled to input 118 of NAND gate 116.

A threshold voltage drop however exists across transistor 114. If inverter 108 outputs a voltage V.sub.CC, node 117 would only be driven to V.sub.CC minus the threshold voltage V.sub.THPT of protection transistor 114 (for example, 1.2 volts) due to this threshold voltage drop were it not for the effect of protection transistor 110. The gate of protection transistor 110 is supplied with a greater charge pump voltage V.sub.CP (for example, 7.8 volts) such that a threshold voltage drop (for example, 1.2 volts) does not occur across transistor 110 during normal circuit operation. Protection transistor 110 therefore conducts the necessary current from the output of inverter 108 to drive input 118 the rest of the way up to V.sub.CC.

Until the voltages V.sub.CC and V.sub.CP reach their appropriate levels (for example, 5.0 volts and 7.8 volts, respectively), however, intermediate voltages are present on those logic module inputs that are to be driven during this power up period with digital logic HIGHs. If, for example, input 7 (see FIG. 2) is at a digital logic LOW and inputs 4-6 are at an intermediate voltage insufficient to turn pmos transistors 214, 218 and 222 completely off, then a current I.sub.CC 225 will flow from supply voltage V.sub.CC, through transistor 228, 214, 218, 222 and 226. Because there are many thousands of these current paths due to the many logic modules in an FPGA, the cumulative total current I.sub.CC may be undesirably large and could be beyond a supply current maximum specified for the device.

FIG. 3 (Prior Art) shows the current spike I.sub.CC that occurs during power up. In the event the FPGA is being powered from a battery, the battery may not be able to supply the large spike of power up current causing the supply voltage V.sub.CC to drop undesirably low during power up.

A method and circuit are desired to prevent such current spikes during power up.

A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during the power up. This voltage turns off transistor(s) in the logic module and prevents the current spike. When power up is completed, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

In some embodiments, a node NA of the protection circuit has a voltage which is initially low and which increases as the voltage V.sub.CP output by a charge pump increases. When the voltage on node NA is below a switching threshold voltage, the protection circuit supplies a first digital logic level (for example, tracks the supply voltage V.sub.CC as V.sub.CC rises) onto the internal disable input. The first digital logic level turns off transistor(s) in the logic module and prevents the current spike. When the voltage on node NA reaches the switching threshold voltage (corresponding with the supply voltage V.sub.CC and the charge pump voltage V.sub.CP having voltages of sufficient magnitudes such that the current spike will not occur if the first digital logic level is removed), the protection circuit supplies a second digital logic level (for example, ground potential) onto the internal disable input.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent from the following description, there is shown and described a preferred embodiment of this invention simply by way of illustration of the mode best suited to carry out the invention. As it will be realized, the invention is capable of other different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the scope of the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.

The accompanying drawings incorporated in and forming a part of the specification, illustrate the present invention, and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 (Prior Art) shows a portion of a field programmable gate array having logic modules connected by antifuses and routing conductors.

FIG. 2 (Prior Art) is a transistor level diagram of a NAND gate that is part of the logic modules shown in FIG. 1.

FIG. 3 (Prior Art) is a waveform diagram of the V.sub.CC and the V.sub.CP voltages and the I.sub.CC current spike that occurs during power up of the field programmable gate array.

FIG. 4 is a simplified schematic of a protection circuit in accordance with an embodiment of the present invention.

FIG. 5 is a simplified waveform diagram of voltages at selected nodes of the protection circuit shown in FIG. 4.

FIG. 1 is an illustration of a portion of a prior art device 100 showing a first logic module 101 and a second logic module 102 that have been interconnected by programmed antifuses 104 and routing conductors 106. Details of such a prior art device can be found in U.S. patent application Ser. No. 08/667,702, which is incorporated herein in its entirety. Details of antifuses can be found in U.S. Pat. Nos. 5,302,546, 5,294,846, and 5,243,226 all of which are incorporated herein in their entirety. The output of logic module 101 includes inverter 108, protection transistor 110 that has a gate connected to a voltage generated by a charge pump, V.sub.CP 112, and protection transistor 114 that has a gate connected to the supply voltage, V.sub.CC 115.

The logic module 102 includes a NAND gate 116 having seven inputs (three are noninverting and four are inverting). Each of the top six inputs can be selectively connected to logic modules via the interconnect structure. One of the inputs to the NAND gate 116 is an internal disable input INTDIS 120 that is used in the prior art to disable the NAND gate 116 during testing of the device. NAND gate 116 is disabled by supplying a digital logic HIGH to the internal disable input INTDIS 120. During power up, the internal disable input INTDIS 120 is supplied with a digital logic LOW in the prior art device.

FIG. 2 is a transistor level diagram of NAND gate 116 showing the seven inputs which have been numbered from 1 to 7 and the NAND gate output 200. As discussed in conjunction with FIG. 1, each of the six inputs 1 through 6 can be connected to other logic modules (such as logic module 101) via the interconnect structure. The seventh input 7 (also labeled 120) is the internal disable input INTDIS. The input 1 is connected to the gate of the nmos transistor 202 and to the gate of the pmos transistor 204. The input 2 is connected to the gate of the nmos transistor 206 and to the gate of the pmos transistor 208. The input 3 is connected to the gate of the nmos transistor 210 and to the gate of the pmos transistor 212. The input 4 is connected to the gate of the pmos transistor 214 and to the gate of the nmos transistor 216. The input 5 is connected to the gate of the pmos transistor 218 and to the gate of the nmos transistor 220. The input 6 is connected to the gate of the pmos transistor 222 and to the gate of the nmos transistor 224. The input 7 which is the INTDIS 120 is connected to the gate of the nmos transistor 226 and to the gate of the pmos transistor 228. The drain of pmos transistor 222 and the drains of nmos transistors 224, 220, 216 and 226 form an output node 230. Node 230 is connected to the gates of pmos transistor 232 and nmos transistor 234.

As can be appreciated, the transistors 228, 214, 218, and 222 provide a path for a current I.sub.CC, indicated at 225, from the supply voltage V.sub.CC to common ground 236 if all of the transistors 228, 214, 218 and 222 are ON or partially ON when at least one of nmos transistors 224, 220, 216 and 226 is ON or partially ON. Similarly, the transistors 234, 202, 206, and 210 provide a path from the supply voltage V.sub.CC for a current I.sub.CC, indicated at 235, to common ground 236 if all of the transistors 234, 202, 206, and 210 are ON or partially ON when at least one of the pmos transistors 232, 204, 208, and 212 is ON or partially ON.

Referring again to FIG. 1, when the prior art device 100 has power applied to it, the voltage sources V.sub.CP and V.sub.CC begin to increase from zero as shown in FIG. 3. The instantaneous voltage from the supply voltage V.sub.CC is represented by v.sub.CC and the instantaneous voltage from the charge pump is represented by v.sub.CP. The threshold voltage of protection transistors 114 and 110 is represented by V.sub.THPT (for example, 1.2 volts). The threshold voltage of the logic transistors in NAND gate 116 is represented by V.sub.THLT (for example, 0.7 volts).

FIG. 3 shows the relationship between the instantaneous voltage v.sub.CC shown at 300 and the instantaneous voltage v.sub.CP shown at 302. Because the instantaneous voltage v.sub.CP is less than v.sub.CC during the initial power up phase as shown in FIG. 3, the voltage at node 117 is initially approximately (v.sub.CC -V.sub.THPT). Due to the interconnect structure, the voltage at node 117 is also present on the input 118 of NAND gate 116. Because the voltage at node 117 is at an intermediate state (that is, the voltage v.sub.CC -V.sub.THPT at node 117 is not sufficiently high to turn a pmos transistor OFF but is sufficiently high to turn an nmos transistor ON), the nmos transistor of any logic module input connected to a node such as node 117 would be either ON or partially ON.

If, for example, input INTDIS 120 is low, then the nmos transistor 226 is OFF and the pmos transistor 228 is ON. If the voltages on inputs 4-6 were driven with intermediate voltages during this period, then I.sub.CC current 225 would flow from supply voltage V.sub.CC, through transistors 214, 218 and 222 and through transistors 224, 220 and 216 to common ground. Node 230 may also be at an intermediate voltage due to the voltage divider effect of the partially on pmos and nmos transistors between V.sub.CC and common ground. In addition, if inputs 1-3 were driven with intermediate voltages during this period, then I.sub.CC current 235 would flow through transistors 232, 204, 208 and 212 and through transistors 234, 202, 206 and 210 to common ground.

FIG. 3 indicates graphically the current spike that occurs during the power up of a prior art field programmable gate array. Although the currents flowing through individual transistors that are partially ON during power up are small, on the order of tenths of milliamperes, because there are thousands of such transistors, the collective current is significant and as shown in FIG. 3 the magnitude can be on the order of 50-120 mA. When the charge pump voltage v.sub.CP exceeds v.sub.CC adequately, protection transistor 110 conducts current from inverter 108 to pull the voltage on node 117 the rest of the way up to v.sub.CC and the I.sub.CC current spikes 225 and 235 stop.

FIG. 4 is a simplified schematic diagram of a protection circuit 400 in accordance with the present invention that prevents the I.sub.CC current spike of the prior art. Output 402 of circuit 400 is coupled to the input INTDIS 120 (FIG. 2) of NAND gate 116 of all logic modules in the FPGA. Circuit 400 causes a digital HIGH voltage (in one embodiment, a voltage that tracks v.sub.CC) to be supplied onto the input INTDIS 120 during the power up period when the prior art current spike would have occurred.

V.sub.CPINTLO is the lowest possible voltage output by the charge pump when the internal disable signal INDIS goes LOW. The charge pump's output voltage v.sub.CP rising above v.sub.CC is what allows the voltage on node 117 to rise up to v.sub.CC. Accordingly, V.sub.CPINTLO must be at least (v.sub.CC -V.sub.THLT)+V.sub.THPT. After this power up period and once v.sub.CP is adequately high, circuit 400 allows the input INTDIS 120 to be driven with a digital logic LOW for normal circuit operation.

Referring to FIG. 2, the instantaneous voltage v.sub.CC is supplied to the gate of the pmos transistor 228 which makes pmos transistor 228 nonconductive. With the transistor 228 nonconductive, current 225 cannot flow. Because the instantaneous voltage v.sub.CC is also supplied to the gate of the nmos transistor 226, nmos transistor 226 is ON, the drain of transistor 226 pulls node 230 LOW, and nmos transistor 234 is nonconductive. Transistor 234 being nonconductive prevents the flow of current 235.

Referring again to FIG. 4, circuit 400 includes an nmos transistor 404 connected between an output of the charge pump 406 and node NA. Nmos transistor 408 is connected between node NA and nmos transistor 410. The nmos transistor 410 is shortable, indicated by the dashed line 412, and is shorted out of the circuit in the 5 volt mask option which clamps the voltage at node NA to one threshold voltage above V.sub.CC. With the transistor 410 in the circuit for 3 volt operation, the voltage at node NA is clamped to two threshold voltages above V.sub.CC. Node NA is connected to node NB via a transistor 414. Transistor 414 is shortable and is shorted for 3 volts operation. With the transistor 414 in the circuit, the voltage at node NB is clamped at V.sub.CC +V.sub.THLT (also the output of the charge pump minus the two threshold voltages of transistors 404 and 414). Transistor 416 is connected as a diode to couple node NB to V.sub.CC and to clamp node NB to not more than one threshold drop above V.sub.CC.

Transistor 418 is provided to test circuit 400. To test the power up circuit 400, input terminal "Con24" 420 is pulsed HIGH when the charge pump 406 is on after the power up period has elapsed. When transistor 418 pulses ON, node NB pulses LOW, inverter 430 outputs a digital logic HIGH pulse, inverter 436 outputs a digital logic LOW pulse, inverter 438 outputs a digital logic HIGH pulse, and buffer 440 outputs a digital logic HIGH pulse. If output 402 does not pulse HIGH, circuit 400 is determined to have failed.

Transistor 422 is controlled by an input from an input terminal "Con5" 424. A digital logic LOW may be placed on terminal 424 to disable circuit 400 in some test modes. Capacitor 426 is connected between node NB and common ground at 428 and functions to maintain node NB at zero volts initially at power up and further functions to retard the voltage increase of node NB. Capacitor 432 is connected between V.sub.CC and node NC and functions to couple node NC to v.sub.CC initially at very low voltages below V.sub.THLT. Transistor 434, inverter 436, and inverter 438 form a buffer circuit with hysteresis to prevent oscillation on node NE. Buffer 440 is gated with other signals and operates as a buffer during normal circuit operation.

FIG. 5 is a simplified waveform diagram of the voltage V.sub.CC, the voltage at INTDIS, and the voltages at the nodes NA, NB, NC, and ND. The current spike during power up can be prevented if a voltage equal to the instantaneous v.sub.CC is applied to the INTDIS input 120 of the NAND gate 116 (FIGS. 1 and 2) during the power up period when intermediate voltages could be present on logic modules inputs.

Referring to FIGS. 4 and 5, during power up the voltage at node NA begins to increase and is one threshold voltage below the voltage at the output of the charge pump. The voltage on node NB begins to increase and as discussed above is retarded by capacitor 426. In addition, as discussed above, the voltage on node NB is at least one threshold voltage below the voltage on node NA due to transistor 414. The voltage on node NC is initially determined by capacitor 432 and tracks the instantaneous voltage v.sub.CC due to capacitive coupling. Inverters 436 and 438 operate to drive the voltage at INTDIS 402 to v.sub.CC which is rising. When the rising voltage on node NB reaches the threshold switching voltage of inverter 430 (which is designed to be approximately V.sub.CC -V.sub.THLT) , inverter 430 begins to switch the voltage on node NC LOW as indicated at 500 (FIG. 5). At this instant, the charge pump's output voltage ("Con9") is approximately 2V.sub.THPT +V.sub.CC -V.sub.THLT (which is about V.sub.THPT higher than V.sub.CC). This charge pump voltage prevents intermediate voltage levels at the inputs of the logic cells. The voltage at INTDIS 402 remains HIGH (tracking v.sub.CC) until inverter 430 completes the switching node NC to a LOW at which time the voltage on input INTDIS switches LOW, indicated at 502. When the voltage on input INTDIS switches LOW, the power up function of the circuit 400 is complete and circuit 400 operates in the normal mode. In this embodiment, signal INTDIS transitions LOW even before v.sub.CC reaches steady state at V.sub.CC.

The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications or variations are possible in light of the above teachings. The embodiment was chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one to utilize the invention in various embodiments and with various modifications which are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as defined by the claims.