Arrangement for Selective Generation of an Output Signal Related to a Clock Signal and Method Therefor

The present invention relates to dynamic latching arrangements. More particularly, the present invention relates to a circuit arrangement and method for conditionally driving a dynamic latching arrangement to selectively generate a signal related to an input clock signal.

Digital logic circuits may be classified by the type of logic they use. For example, one type, known as combinational or combinatorial logic, generates one or more outputs as a function only of the current input or inputs. By contrast, state logic circuits typically produce the output or outputs as a function of what is known as a present state vector. The present state vector is typically stored in storage elements. For example, the present state vector may be stored in flip-flops or magnetic storage media. Several factors typically influence the present state vector, such as the current input or inputs and the history of inputs.

State logic circuits typically include circuitry that generates what is known as a next state vector, which typically in turn determines the output or outputs generated. Like the present state vector, the next state vector is typically stored in storage elements.

State logic circuits can be further classified by the way in which they store the present and next state vectors. One type of state logic circuit, known as static logic, typically stores state vectors on arrays of memory elements, such as flip-flops. Another type, known as dynamic logic, typically stores information as electrical charges on points in the circuit known as nodes. Such nodes typically assume a high impedance state when they are not being updated. In such a state, the nodes can hold electrical charges.

State logic circuits are often designed for synchronous operation. Circuits of this type typically rely on clock signals to synchronize their operations. In such logic circuits, the output values are updated every time an effective edge or transition of the clock signal occurs. For some systems, the effective edge is defined as the positive edge of the clock signal. In circuits of this type, the output values are updated when the clock signal transitions from the low logic state to the high logic state. For other systems, the effective edge is defined as the negative edge of the clock signal. These systems have outputs whose values are updated when the clock signal transitions from the high logic state to the low logic state. A number of applications benefit from the ability to select between a clock signal and a signal related to the clock signal. For example, some applications benefit from the ability to generate a divided clock signal having a frequency lower than the clock signal. This capability is desirable, for example, for use in prescaling circuits.

Some clock division approaches use an edge-triggered flip-flop configured as a toggle to provide a divided clock signal. Approaches of this type typically also use a multiplexer to select between the original clock signal and the divided clock signal. The multiplexer increases the amount of chip real estate required, thereby increasing both the device size and the cost of manufacture. Furthermore, the additional level of logic imposes gate delays, resulting in slower overall speed. Power consumption is also increased unnecessarily because power is required to run the unused path. For example, if the original clock signal is selected, power is required to generate the divided clock signal even though the divided clock signal is not used. Conversely, if the divided clock signal is selected, power is required to run the original clock signal path. This waste of power is particularly significant in applications in which power must be used efficiently, such as portable computers and other battery-powered devices.

Generally, the present invention provides a circuit arrangement and method for conditionally driving a dynamic latching arrangement. Consistent with one aspect of the present invention, a circuit arrangement includes a dynamic latching arrangement that includes first and second state storing circuits, at least one of which has an internal node. The dynamic latching arrangement processes a clock signal and generates an output signal as a function of an internal signal stored on the internal node. The circuit arrangement further includes conditional driving circuitry that selectively impresses an alternate internal signal on the internal node such that the circuit arrangement generates an alternate output signal as a function of the alternate internal signal.

Consistent with another aspect of the present invention, a system incorporating the circuit arrangement is provided.

Consistent with another aspect of the invention, a circuit arrangement for selectively generating a clock signal or a divided clock signal in response to a control signal is provided. The circuit arrangement includes a first circuit that generates the divided clock signal and a second circuit that selectively impresses a signal related to an input clock signal on an internal node of the first circuit in response to the control signal.

Consistent with another aspect of the present invention, a method for selectively providing a clock signal or a divided clock signal is provided. The method involves presenting an input clock signal to a circuit and generating the divided clock signal. When a control signal is asserted, a signal related to the input clock signal is impressed on an internal node of the circuit.

Consistent with another aspect of the present invention, a method for selectively generating an output signal related to a clock signal is provided. The clock signal is provided to at least one dynamic latching arrangement. A signal is selectively impressed on an internal node of the latching arrangement.

The above summary of the present invention is not intended to describe each illustrated embodiment, or every implementation, of the present invention. This is the purpose of the figures and of the detailed description that follow.

Various aspects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 illustrates in block diagram form a system consistent with an embodiment of the present invention;

FIG. 2 illustrates in block diagram form a circuit arrangement consistent with an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating in greater detail a circuit arrangement consistent with an embodiment of the present invention; and

FIGS. 4A and 4B are timing diagrams illustrating various waveforms generated in a circuit arrangement consistent with an embodiment of the present invention.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

The present invention is believed to be applicable to dynamic logic circuits. Circuit arrangements consistent with the present invention have been found to be particularly advantageous in application environments in which it is desirable to selectively generate either a copy of an input clock signal or a divided clock signal. The illustrated embodiments take advantage of the high impedance present on dynamic logic nodes during portions of their cycles in order to conditionally impress a clock signal on the nodes. Thus, the multiplexer used by some approaches is eliminated, reducing the amount of logic required. As a result, the circuit arrangements are simpler and more compact than previous approaches. The reduction in logic also results in higher speed and lower power consumption.

Referring now to the drawings, FIG. 1 illustrates an exemplary system consistent with an embodiment of the invention. The system may be implemented, for example, as a computer 5. A central processing unit (CPU) 6 performs arithmetic and logic operations and includes, for example, an arithmetic logic unit and control circuitry. A memory 7, stores data used by the CPU 6, such as program instructions to be executed by the CPU 6. The memory 7 may include random access memory, read only memory, or both. The CPU 6 accesses data stored in the memory 7 using an address signal to select a location for storing data in the memory 7. A dynamic latching arrangement 8 (discussed in greater detail below), is utilized in the CPU 6, the memory 7, or both.

FIG. 2 shows in block diagram form a dynamic latching arrangement 8 consistent with the invention. The dynamic latching arrangement has an input stage 10 and an output stage 12. The output stage 12 receives a control signal from an input terminal 16. Both stages 10 and 12 receive a clock signal CP from an input terminal 14. The clock signal CP is typically a square wave with a high logic state and a low logic state, alternating between the two states with a period T.sub.0 and a frequency f.sub.0 =1/T.sub.0.

The input stage 10 employs a feedback loop 18 to receive as input a signal OUT from the output stage 12 when the clock signal CP is at one logic state. A copy of the signal OUT is provided to the output stage 12 when the clock signal CP enters the other logic state. A conditional driver 15 is configured and arranged such that, when the control signal is active, a signal related to the clock signal CP is impressed on an internal node, such as a node N.sub.4, of the latching arrangement 8 due to the high impedance on the internal node. For example, the impressed signal may be a logical complement of the clock signal CP. Assuming such a signal is impressed on the internal node of the latching arrangement 8, a copy of the clock signal CP is generated as the signal OUT. When, on the other hand, the control signal is not active, the conditional driver 15 impresses no signal on the internal node. Instead, the output stage 12 changes its logic state at the positive edge of the clock signal CP. The positive edge occurs, and the state of the output stage 12 changes, once every two transitions of the clock signal CP. As a result, the signal OUT is a square wave with a period T.sub.1 equal to twice T.sub.0 and a frequency f.sub.1 =1/T.sub.1 =f.sub.0 /2.

One particular embodiment of the latching arrangement 8 is illustrated in FIG. 3. Discussion of the operation of this embodiment of the latching arrangement 8 is facilitated by reference to the timing diagrams of FIGS. 4A and 4B, which respectively illustrate waveforms generated in modes of operation in which the control signal is inactive and active. In the illustrated configuration, the input stage 10 is active during the low logic phase of the clock cycle, and the output stage 12 is active during the high logic phase of the clock cycle. Each stage samples a signal during its active phase. When the clock signal CP is low, the input stage 10 samples the signal OUT provided by the output stage 12 through the feedback loop 18. When the clock signal CP transitions to the high logic state, the output stage 12 samples the output from the input stage 10 and changes its state accordingly.

The input stage 10 is configured and arranged to receive an input signal when it is activated by an input stage clock device 104. The input stage clock device 104 may be implemented, for example, as a P-type MOSFET. Assuming the input stage clock device 104 is implemented as a P-type MOSFET, the input stage 10 receives the input signal when the clock signal CP is in the low logic state. In this embodiment, the input stage receives the signal OUT from the output stage 12 through the feedback loop 18. A gate terminal 106 of the input stage clock device 104 is responsive to the clock signal CP. A pair of transistors 108 and 110 is configured to invert the signal OUT provided to their respective gate terminals 112 and 114 through the feedback loop 18. For example, the transistor 108 may be implemented as a P-type MOSFET coupled to a power supply V.sub.DD, and the transistor 110 may be implemented as a grounded N-type MOSFET. When the clock signal CP transitions to the low logic state, the input stage clock device 104 enters the conducting mode. If the signal OUT is also low as illustrated at a time T.sub.a in FIG. 4A, the transistor 108 pulls a voltage V.sub.1 at the nodes N.sub.1 and N.sub.2 up to V.sub.DD, placing the input stage 10 in the high logic state. If, as illustrated at a time T.sub.b in FIG. 4A, the signal OUT is high, the transistor 110 pulls the voltage V.sub.1 down to ground, placing the input stage 10 in the low logic state.

The output stage 12 generates the signal OUT based on the signal received from the input stage 10 and on the state of the control signal. An output stage clock device 116 activates the output stage 12 when the clock signal CP assumes a preselected logic state. For example, in the illustrated embodiment, the output stage clock device 116 activates the output stage 12 on the positive edge of the clock signal CP. Assuming the output stage 12 is positive edge-triggered, the output stage clock device 116 is implemented as an N-type MOSFET. A gate terminal 118 of the output stage clock device 116 is responsive to the clock signal CP. The transistors 120 and 122 are configured and arranged to invert the signal provided to their respective gate terminals 124 and 126 from the nodes N.sub.1 and N.sub.2. For example, the transistor 120 may be implemented as a P-type MOSFET coupled to the power supply V.sub.DD, and the transistor 122 may be implemented as a grounded N-type MOSFET. On the positive edge of the clock signal CP, the output stage clock device 116 enters the conducting mode. If the input stage 10 is in the low logic state, as illustrated at a time T.sub.c in FIG. 4A, the gate terminal 124 of the transistor 120 is grounded through the input stage clock device 104 and the transistor 108. Consequently, the transistor 120, along with the output stage clock device 116, pulls a voltage V.sub.2 at the nodes N.sub.3 and N.sub.4 up to V.sub.DD. If, as illustrated at a time T.sub.d in FIG. 4A, the input stage 10 is in the high logic state, the gate terminal 126 of the transistor 122 is coupled through the input stage clock device 104 and the transistor 106 to V.sub.DD. As a result, the transistor 120 pulls the voltage V.sub.2 down to ground. A pair of transistors 128 and 130 is similarly configured and arranged to provide an additional inversion to generate the signal OUT, which is provided to the gate terminals 112 and 114 of the transistors 106 and 108 of the input stage 10 through the feedback loop 18. Because the positive edge of the clock signal CP occurs once per cycle of the clock signal CP (i.e., once for every two transitions), the signal OUT changes its state once for every two transitions of the clock signal CP. Thus, the circuit generates an output square waveform with half the frequency of the clock signal CP.

Additional circuitry is configured and arranged to allow a signal related to the clock signal CP to be impressed on an internal node of the latching arrangement 8 such that the signal OUT is a copy of the clock signal CP rather than a divided clock signal. For example, in the illustrated embodiment, the conditional driver 15 selectively impresses the node N.sub.4 with a logical complement of the clock signal CP. A control device 131 is responsive to the control signal from the control input terminal 16. The control device may be implemented, for example, as a transistor 132. In the illustrated embodiment, the transistor 132 is implemented as an N-type MOSFET. However, it will be appreciated by those skilled in the art that a different type of component, such as a P-type MOSFET, may be selected to implement the control device. A transistor 134 is responsive to the clock signal CP. When the control signal and the clock signal CP are low, transistors 116, 132, and 136 are in the nonconducting mode. The node N.sub.4 is thus placed in a state of high impedance and retains its previous state. The transistor 134 is decoupled from the node N.sub.4, and the logical complement of the clock signal CP is not impressed on the node N.sub.4. Consequently, the circuit generates a divided clock signal, which is provided at the output terminal 20.

When the control signal is high, the transistor 132 is in the conducting mode and couples the transistor 134 to the node N.sub.4. If the clock signal CP is low, as illustrated at the times T.sub.a and T.sub.b in FIG. 4B, the transistor 134 acts as a pull-up resistor, pulling the voltage V.sub.2 at the node N.sub.4 up to V.sub.DD. The transistor 136, which is in the nonconducting mode when the clock signal CP is low, maintains the node N.sub.4 in a high impedance state. Because transistors 128 and 130 invert the state produced at N.sub.4, the signal OUT is low. If, as illustrated at the times T.sub.c and T.sub.d in FIG. 4B, the clock signal CP is high, the transistor 136 acts as a pull-down resistor, pulling the voltage V.sub.2 at the node N.sub.4 down to ground. The transistor 134 is in the nonconducting mode, such that the node N.sub.4 is not coupled to V.sub.DD. The pair of transistors 128 and 130 produce another level of inversion so that the signal OUT is high. As a result, when the control signal is high, the signal OUT has the same frequency as the clock signal CP.

While the present invention has been described in connection with the exemplary embodiments thereof, it will be understood that many modifications will be readily apparent to those skilled in the art. A relatively small modification is to, for example, implement the transistor 132 as a P-type MOSFET. This variation would yield a circuit that provides a copy of the input clock signal when the control signal is low and the divided clock signal when the control signal is high. Furthermore, the conditional driver 15 may be coupled to the input stage 10 rather than to the output stage 12. These and other modifications to the illustrated embodiments are intended to fall within the scope of the present invention, as set forth in the following claims.