Method and Apparatus for External Viewing of an Internal Bus

The invention generally relates to electrical system design, and more specifically to circuitry for observing an internal integrated circuit (IC) bus on an existing external bus from within the IC.

In the semiconductor arts, it is known that microprocessor units (MPU) have internal buses for the transmitting of data, address information, and control information. Often it is desirable for the states of the internal buses to be reviewed externally to the MPU. Traditionally this is accomplished by providing external pins either directly or multiplexed, for transmitting the internal bus data to an external source. A problem with this technique occurs with many modern MPUs, in that as the number of internal buses and control signals increase, the number of input/output (I/O) pins needed to view the internal states of desired buses must increase. The number of pins required may not be physically realizable on any practical package which can be used to encapsulate the integrated circuit. The number of pins required may also adversely impact the cost of the system of which the integrated circuit is a component. Therefore, it would be desirable to view, external to the integrated circuit, multiple internal buses, without increasing the number of pins needed external to the integrated circuit.

FIG. 1 illustrates, in a block diagram form, a system 100 in accordance with the present invention.

FIG. 2 illustrates, in block diagram form, a system portion 200 of the system 100, including a detailed view of control section 120.

FIG. 3 illustrates a timing diagram in accordance with the present invention.

FIG. 4 illustrates a flow diagram representing a method 400 in accordance with the present invention.

In general, the present invention allows a central processing unit (CPU) to initiate a fast access bus request to a memory control section in order to access on-chip memory. In response to the fast access bus request, a control section uses one or more compare registers to provide one or more compare addresses. The one or more compare addresses are compared to the actual fast access bus (FAB) address. If the requested FAB address resides within the boundaries of the compare register, the control section will not respond with an address acknowledge signal (FAACK) to the CPU (e.g. a control signal will be asserted which will block the assertion of the FAACK). In response to not receiving a valid address acknowledge signal (FAACK), the CPU will attempt to access the desired address location through an alternate bus referred to as the inter-module bus (IMB). The alternate bus can be viewed externally to the microprocessor 100, thereby giving users observability of the access information. This information would normally be provided over the fast access bus (FAB) since the fast access bus (FAB) is not observable directly to a user external to the integrated circuit 100.

First, the interconnectivity of FIGS. 1-2 will be discussed, followed by the functional operation of the devices represented in the FIGURES.

Regarding connectivity, FIG. 1 illustrates a microprocessor or integrated circuit (IC) 100. Microprocessor 100 comprises a CPU 110, a control section 120, a memory block 130, other modules 150, an integration module 160, an external output 170, an inter-module bus (IMB) 114, a fast access bus (FAB) 112, and a memory bus 122. The CPU 110 is connected to the FAB control section 112. Additionally, CPU 110 is connected to the integration module 160, other modules 150, and the control section 120 through the inter-module bus (IMB) bus. The control section is coupled via a memory bus 122 to the memory block 130, and to the external output 170. The memory block 130 includes a plurality of separate bit cell blocks 131-141.

FIG. 2 illustrates the portion 200 of microprocessor 100. The portion 200 includes a detailed view of control section 120, and memory block 230, which corresponds to memory block 130 of FIG. 1, and visibility bus drivers 250 which in turn would be a portion of the external output 170 of FIG. 1. The control section 120 has a fast access bus (FAB) interface 210, an arbitration and clocks section 220, an IMB interface section 225, comparators 215, a visibility bus (VB) interface 226, and a random access memory (RAM) access section 260. A buffered FAB address and data bus is provided by the FAB interface 210 and received by comparators 215 and visibility bus (VB) interface 226. A fast access bus address (FADDR) is provided by FAB interface 210 and connected to arbitration/clocks section 220. A bi-directional bus is connected between FAB interface 210, inter-module bus (IMB) interface 225, comparators 215, and RAM access 260. An operand bus address (CADDR) bus and array bus select (ABSEL) are output from the section 220 to access internal memory 230.

FIG. 3 illustrates a timing diagram relationship between the FAB 112 and the control section 120.

FIG. 4 illustrates a flow diagram of a method 400. The flow diagram comprises rectangular action blocks 410-415, and a diamond shaped decision block 420.

In operation, the CPU 110 of FIG. 1 can initialize and access the control module section 120, integration module 160 or other modules 150, through the inter-module bus (IMB) 114. In addition, the CPU 110 can access the control section 120 through the fast access bus (FAB) 112. By providing a separate FAB 112, the CPU is able to access memory block 130, through a control section 120, at a faster rate. The faster rate is supported by a bus clock which in a preferred embodiment is twice that of the bus clock associated with the IMB 114. Additional throughput is possible in the system of FIGS. 1 and 2 since FAB 112 memory accesses can be performed in parallel to instruction fetches on the IMB 114.

During a normal memory block 130 access cycle the CPU 110 initiates the access via the FAB 112. The control section 120 which receives the FAB 112 determines whether or not the FAB address is a valid address in memory block 130. When an address is identified in the memory block 130 as being a valid address, the control section responds to the CPU 110 by sending an active FAB address acknowledge signal which is part of the FAB 112. This indicates to the CPU that the FAB address is valid. As such, the read or write access to the memory block 130 proceeds in a traditional fashion with the CPU either reading or writing data, with the cycle concluding when a transfer acknowledge signal is sent by the control block 120.

During a viewable memory block access cycle, the control section 120 does not assert an address acknowledge signal. As a result, the CPU 110 will attempt the same access on the IMB 114. Since the IMB is observable outside the microprocessor 100, the access which would normally occur on the FAB 112 is rerouted to the IMB 114, and becomes externally observable outside the packaged integrated circuit 100.

FIG. 2 illustrates in more detail the control section 120. The FAB 112 is received by the FAB interface portion 210 of the control section 120. FAB interface block 210 provides the address received from the FAB to the comparator portion 215. Comparator portion 215 includes a comparator register for storing an address or address block to be viewed on the IMB 114. When the value stored in the comparator register portion of the comparator 215 matches the current address on the FAB 112, the acknowledge enable signal 211 is not asserted. When the FAB interface portion 210 does not respond to the CPU 110 with an asserted address acknowledge signal, the CPU 110 is notified that the FAB did not acknowledge the request.

When an address is identified as invalid by the control section 120 through the FAB 112, the CPU 110 will attempt the exact same access on the IMB 114. The IMB 114 access to the control section 120 occurs through the IMB interface portion 225. The IMB interface portion 225 will process the data request rejected by the FAB 112. In the event that the memory location being accessed truly does not exist in the memory block 130, the IMB interface portion will not send a valid address acknowledge signal. However, in the event where the comparator registers associated with the FAB interface 210 blocked the FAB 112 request, the IMB interface 225 will access the desired location and present it to the IMB 114. By redirecting the access being attempted over the FAB to the inter-modular bus 114, the data access which would normally occur on the FAB is observable external to the microprocessor 100 without the need of additional input/output resources.

In an alternative embodiment of the present invention it may be desirable to have the option to actually pin out the fast address bus directly. A visiblility bus (VB) interface 226, is illustrated in FIG. 2. The VB interface 226 receives the FAB address and data information from the interface block 210. This information is provided directly to visibility bus (VB) drivers 250. VB drivers 250 provide the information to external pins, serially or in parallel, such that the FAB 112 is observed external to microprocessor 100. Generally, this will entail driving a parallel bus. Note that the combination of using the VB interface 226 and the comparator block 215 in order to disable the FAB offers a flexible solution. The first being where it is desirable to view the FAB address bus working at its full clock speed external to the part that may be accomplished through the VB interface 226. However, in a situation where extra pins are not available for external viewing, it is possible to redirect the FAB address bus contents to the IMB 114 by masking out an acknowledge signal (FAACK) when the address of the access on the FAB is within a certain constraint (equal to a specific address or within a defined address range).

FIG. 3 illustrates the common relationship among the signals associated with FAB 112. The clock signal shows a number of cycles of the FAB clock 112. Note that the cycle representation for the clock signal begins at cycle F3 of the previous access cycle. The previous bus cycle was a read cycle as indicated by the data signal. At cycle F3 of the previous memory access the FAB data transfer acknowledge signal is driven active during cycle F3 by the FAB interface 210. This indicates that the data to be read by the CPU either has been or is in the process of being transferred to the FAB 112. During cycle F4 of the previous bus access the CPU 110 drives a new address to the address bus and asserts the FAB cycle start signal (FCYS). Also during cycle F4 of the previous access, the FAB address acknowledge signal is de-asserted by the FAB interface 210. During the rising edge of current cycle F1, the address information is received by the control section 120, and the data from the prior access is read by the CPU 110. During cycle F1, the address received by the control section is decoded. During cycle F2 of the current access, the FCYS signal is de-asserted, and in the event where the comparator portion 215 of the control section 120 identifies a match between the comparator register and the address provided by the CPU, the FAB address acknowledge signal remains deasserted as indicated by the highlighted line of FIG. 3. Note that if the compare had not been valid it would indicate a normal bus cycle and the FAB address acknowledge signal would have been asserted during cycle F2.

For a write cycle, the CPU would present the write data on the address bus during cycle F2. In the timing diagram of FIG. 3, during the cycle F3, no transitions take place, as the FAB data transfer acknowledge signal has been disabled because of the compare registers matched the FAB address. Upon completion of the current cycle, the CPU would recognize that an invalid access attempt has occurred over the FAB, and a similar attempt would be made over the inter-module bus (IMB) 114. During the IMB access 114, a successful access, albeit at a lower bus speed, would occur allowing observability of the FAB.

The FAB data transfer acknowledge signal (FDTACK) and a fast access bus break point (FBKPT) (see FIG. 3) may also be used to inspect internal contents of memory. However, breakpoints tend to be more performance inhibiting than the FAACK denial mechanism taught herein. For the breakpoint function, the comparators contained within block 215 perform a compare function which identifies a break point location which is related to a given address. Since these comparators are already present in order to do breakpoint operations, the additional functionality of disabling the FAB (by denying FAACK) when attempting to observe accesses to a memory portion does not require additional hardware, as the breakpoint comparators double for this function.

FIG. 4 illustrates a method 400 in accordance with the present invention. During a first step 410, a semiconductor device having a first bus and a second bus is provided. The first bus would be analogous to the fast access bus, and the second bus would be analogous to the IMB 114. Next, at step 411, the address to be viewed externally is defined. This would be analogous to storing in the registers of comparator section 215, the address or addresses desired to be viewed external. These stored addresses are compared to the FAB address. Next, at step 412, an address request is placed on the first bus. The addresses on the first bus is part of an overall memory block 130 cycle. Next, during a step 420, it is determined whether or not the view address, which is stored in the registers of comparator block 215, matches the requested address, as provided on the first bus in step 412. In the event no match occurs, normal processing continues at a step 415. However, if a match does occur at step 420, processing continues at block 413. At block 413 the request is not acknowledged. This is analogous to the FAB address acknowledge signal not being asserted during cycle F2. Next, at step 414, the address of step 411 is provided to the second bus to define memory access. This occurs following step 413 when the CPU 110 recognizes that the fast access bus 112 request was not acknowledged. This access of the second bus in one embodiment would occur over the inter-module bus (IMB) 114.

While the present invention has been illustrated and described with reference to specific embodiments, further modifications and improvements will occur to those skilled in the art. For example, multiple enable signals may replace a single enable signal. Bus widths can be varied (e.g., 16 bit bus, 24 bit bus, 32 bit bus, 64 bit bus, etc.). Any type of memory (e.g., DRAM, SRAM, EEPROM, flash, ferroelectric, any combination thereof, etc.) and any configuration of memory (e.g. ten 2K blocks, three 32K blocks, five 16K blocks, etc.) can be used within the memory block 130. CPU 110 can be a pipelined or superscalar CPU or a plurality of individual CPUs. It is to be understood, therefore, that this invention is not limited to the particular forms illustrated and that it is intended in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention.