Level-Shift Circuit for Driving Word Lines of Negative Gate Erasable Type Flash Memory

1. Field of the Invention

This invention relates to a level-shift circuit used in a CMOS circuit, and more particularly to a level-shift circuit suitable for driving word lines in a negative gate erasable type flash memory.

2. Description of the Related Art

Conventionally, a level-shift circuit used in a CMOS circuit is constructed as shown in FIGS. 1 and 2. FIG. 1 shows a circuit for shifting the "H" level and FIG. 2 shows a circuit for shifting the "L" level, and in each of the above circuits, the "H" level of an input signal V.sub.IN is set at Vcc and the "L" level thereof is set at the ground potential (GND) level. This type of level-shift circuit is described in Jpn. Appln. KOKAI Publication No. 6-215591 (U.S. Application No. 08/179,126), for example.

The level-shift circuit shown in FIG. 1 includes P-channel MOS transistors Q1, Q2, N-channel MOS transistors Q3, Q4 and a CMOS inverter 11. A potential V.sub.H is applied to the sources of the MOS transistors Q1, Q2, and the drain-source paths of the MOS transistors Q3, Q4 are respectively connected between the drains of the MOS transistors Q1, Q2 and the ground node GND. The gate of the MOS transistor Q1 is connected to a common connection node between the MOS transistors Q2 and Q4 and the gate of the MOS transistor Q2 is connected to a common connection node between the MOS transistors Q1 and Q3. An input signal V.sub.IN is supplied to the gate of the MOS transistor Q3 and the input signal V.sub.IN is supplied to the gate of the MOS transistor Q4 via the inverter 11. An output signal V.sub.OUT is output from a connection node between the MOS transistors Q2 and Q4 and an inverted signal V.sub.OUT of the output signal V.sub.OUT is output from a connection node between the MOS transistors Q1 and Q3. In this circuit, the "L" level of the output signals V.sub.OUT and V.sub.OUT is kept at the ground level, but the "H" level thereof is shifted to the potential V.sub.H.

The level-shift circuit shown in FIG. 2 includes P-channel MOS transistors Q5, Q6, N-channel MOS transistors Q7, Q8 and a CMOS inverter 12. A power supply node Vcc is connected to the sources of the MOS transistors Q5, Q6, and the drain-source paths of the MOS transistors Q7, Q8 are respectively connected between the drains of the MOS transistors Q5, Q6 and a potential node V.sub.L. The gate of the MOS transistor Q7 is connected to a common connection node between the MOS transistors Q6 and Q8 and the gate of the MOS transistor Q8 is connected to a common connection node between the MOS transistors Q5 and Q7. An input signal V.sub.IN is supplied to the gate of the MOS transistor Q5 and the input signal V.sub.IN is supplied to the gate of the MOS transistor Q6 via the inverter 12. An output signal V.sub.OUT is output from a connection node between the MOS transistors Q6 and Q8 and an inverted signal V.sub.OUT of the output signal V.sub.OUT is output from a connection node between the MOS transistors Q5 and Q7. In the circuit of FIG. 2, the "H" level of the output signals V.sub.OUT and V.sub.OUT is kept at Vcc, but the "L" level thereof is shifted to the potential V.sub.L.

The P-channel MOS transistors Q1, Q2 in the circuit of FIG. 1 are formed in an N-well region biased by the potential V.sub.H, and the N-channel MOS transistors Q7, Q8 in the circuit of FIG. 2 are formed in a P-well region biased by the potential V.sub.L.

Next, the row decoder circuit of a flash memory is considered. At the time of data writing in the cell transistor of the flash memory, the source thereof is grounded, and potentials Vg (Vg=Vpr>Vcc) and Vd (Vd>0) are respectively applied to the control gate and drain thereof. By application of the above potentials, hot electrons are injected into the floating gate to effect the writing operation. On the other hand, at the time of erasing, a high positive potential Vs (Vs>0) is applied to the source and a high negative potential Vg (Vg=Ver<0) is applied to the control gate to set up an intense electric field across the tunnel oxide film and extract electrons in the floating gate by the tunnel current (this is called "negative gate erasing"). In the negative gate erasing, since a negative potential is applied to the control gate, the potential applied to the source can be suppressed to a lower potential in comparison with a method of erasing data by applying the ground potential to the control gate (this is called "source erasing").

Further, at the verifying time of the program, the potential of the floating gate is set to a potential higher than Vcc to check the threshold voltage Vth. Since the control gate corresponds to the word line in the memory cell array, it becomes necessary for the row decoder circuit for driving the control gates, that is, word lines to output a potential higher than Vcc to the word line at the time of writing or verifying and output a negative potential to the word line at the time of erasing.

The potentials V.sub.H, V.sub.L and the word line potential in the writing mode, erasing mode and verifying mode can be summarized as shown in the following table 1.

If the level-shift circuits shown in FIGS. 1 and 2 are applied to the above row decoder, a circuit as shown in FIG. 3 is obtained. FIG. 3 shows a circuit portion corresponding to one word line in the row decoder circuit. An address signal Add is supplied to a decoder 20 and a decoder signal SEL output from the decoder 20 is supplied to a latch circuit 21. The latch circuit 21 latches the decoder signal SEL in response to a latch signal LAT. An output signal of the latch circuit 21 is supplied to the level-shift circuit 22 shown in FIG. 2 in which the "L" level thereof is shifted to the potential V.sub.L and whose output signal is supplied to the level-shift circuit 23 shown in FIG. 1. In the level-shift circuit 23, the "H" level of the output signal of the level-shift circuit 22 is shifted to the potential V.sub.H and then the output signal is supplied to the word line. As a result, the "H" level of the signal supplied to the word line is set to V.sub.H and the "L" level thereof is set to V.sub.L. In the circuit of FIG. 3, as the output signals of the level-shift circuits 22, 23, output signals V.sub.OUT of the level-shift circuits shown in FIGS. 1 and 2 are used.

When the address signal Add is decoded, the decoder signal SEL for the selected word line is set to the "H" level and the decoder signal SEL for the non-selected word line is set to the "L" level. The "H" level of the decoder signal SEL is Vcc and the "L" level thereof is GND. For example, the latch circuit 21 is constructed by a set-reset type flip-flop as shown in FIG. 4, and if the latch signal LAT supplied to the reset input terminal is set at the "H" level, the "H" and "L" levels of the input signal V.sub.IN are supplied as they are as the output signal V.sub.OUT. On the other hand, if the latch signal LAT is set at the "L" level, the output signal V.sub.OUT is held at the "L" level when the input signal V.sub.IN supplied to the set input terminal is set at the "L" level, and after this, once the input signal V.sub.IN is set to the "H" level, the output signal V.sub.OUT inverted and kept at the "H" level.

With the above construction, the latch signal LAT of the latch circuit 21 is set to the "H" level and the potential V.sub.L is set at the GND level at the time of writing. Decoding of the address signal Add is effected with V.sub.H =Vcc, and after determination, the potential V.sub.H is changed from the Vcc level to the Vpp level. As a result, the potential of only the word line selected by the address signal Add is set to the Vpr level and the potential of the other word lines (non-selected word lines) is set to the GND level.

On the other hand, at the time of erasing, the potential V.sub.H is set to the Vcc level. Further, the potential V.sub.L is set to the GND level so as to set all of the addresses into the non-selected state, that is, set the decoder signals SEL for all of the word lines to the "L" level, and in this state, the latch signal LAT is changed from the "H" level to the "L" level. As a result, first, all of the word lines are latched in the non-selected state. Next, if address selection is sequentially effected only for those of the word lines which are not desired to be subjected to the erasing process, only the decoder signals SEL for these word lines are set to the "H" level and latched data is inverted to set a selected state. In this state, if the potential V.sub.L is changed from the GND level to the negative potential Ver, the potentials of only those of the word lines which are latched in the non-selected state are set to the negative potential Ver to effect the erasing operation (the relation between the selected state and non-selected state is opposite to that for the word line to be subjected to the erasing process). The word line set in the selected state is kept at the Vcc level and is not subjected to the erasing process.

Thus, desired operations can be effected in the respective modes requiring the level-shift.

Next, the readout operation is considered. At the time of data readout, since the potential of the word line is normally set at the Vcc level, the address signal Add is decoded with the latch signal LAT set at the "H" level, the potential V.sub.L set at the GND level and the potential V.sub.H set at the Vcc level. At this time, the latch circuit 21 and level-shift circuits 22 and 23 transfer the input signal as it is and the decoding operation is delayed by time corresponding to the gate delay.

Now, the construction of the above decoder circuit is compared with that of a source erasable flash memory. In the source erasable type circuit, only the source is set to a high potential with the control gate of the cell transistor kept at the GND level at the time of erasing. Therefore, it is not necessary to bias the word line to a negative potential, and there occurs no difference between the selected and non-selected word lines, and the latch circuit 21 and level-shift circuit 22 become unnecessary. As a result, the access time in the negative gate erasable type row decoder circuit is deteriorated by insertion of the latch circuit 21 and level-shift circuit 22. Particularly, as shown in FIGS. 1 and 2, since the conventional level-shift circuit has a feedback type circuit construction and the ratio of the areas of the P-channel MOS transistor and the N-channel MOS transistor is unbalanced to forcedly effect the inverting operation, the gate delay becomes larger in comparison with a normal inverter or the like. Further, a case wherein transistors of a Vcc circuit system and transistors of a circuit operated on high voltages at the time of writing and erasing are separately formed, the gate oxide film of the former transistor is made thin to set the threshold voltage Vth thereof low, and the gate oxide film of the latter transistor is made thick to set the threshold voltage Vth thereof high in order to cope with a lowering in the power supply voltage (for example, a lowering from 5 V to 3.3 V) is considered. The above construction is made because the performance becomes extremely low if the transistor whose gate oxide film is made thick to set the threshold voltage Vth high in order to cope with the high-voltage operation is operated by the power supply voltage Vcc which is lowered. However, with the construction shown in FIG. 3, it becomes necessary to operate the high-voltage transistor by the voltage Vcc at the time of readout, thereby further delaying the operation.

Accordingly, a first object of this invention is to provide a level-shift circuit capable of suppressing the gate delay and enhancing the operation speed.

A second object of this invention is to provide a level-shift circuit capable of reducing access time when it is applied to the row decoder circuit of a negative gate erasable flash memory.

Further, a third object of this invention is to provide a level-shift circuit which can effect the level-shift of "H" and "L" levels in one stage, latch an input signal and cope with a lowering in the power supply voltage without lowering the operation speed and which is suitable for the row decoder circuit of a negative gate erasable flash memory.

A fourth object of this invention is to provide a semiconductor memory device having a level-shift circuit capable of suppressing the gate delay and enhancing the operation speed.

A fifth object of this invention is to provide a negative gate erasable flash memory having a level-shift circuit capable of reducing access time in the row decoder circuit thereof.

Further, a sixth object of this invention is to provide a negative gate erasable type flash memory including a row decoder circuit having a level-shift circuit which can effect the level-shift of "H" and "L" levels in one stage, latch an input signal and cope with a lowering in the power supply voltage without lowering the operation speed.

The above first to third objects can be attained by a level-shift circuit comprising a first inverting circuit operated with a voltage between a potential of a first potential supplying source and a potential of a second potential supplying source used as a power supply voltage; a second inverting circuit having an input terminal connected to an output of the first inverting circuit and an output terminal connected to an input terminal of the first inverting circuit and operated with a voltage between the potential of the first potential supplying source and the potential of the second potential supplying source used as a power supply voltage; first and second transistors of a first conductivity type whose current paths are serially connected between the input terminal of the first inverting circuit and a third potential supplying source, the gate of the second transistor being supplied with an input signal whose high level is set at a potential of a fourth potential supplying source and whose low level is set at a potential of the third potential supplying source; third and fourth transistors of the first conductivity type whose current paths are serially connected between the input terminal of the second inverting circuit and the third potential supplying source; a control circuit for shifting a low level of a first control signal to the potential of the second potential supplying source and supplying the level-shifted first control signal to the gates of the first and third transistors to control the conduction states thereof; and a logic circuit for supplying a logical signal to the gate of the fourth transistor in response to the input signal to control the conduction state thereof; wherein an output signal is derived from at least one of the output terminals of the first and second inverting circuits.

With the above construction, the first and second inverting circuits constitute a latch circuit and the latching operation of the latch circuit is controlled according to the level of the control signal. When the control signal is at the high level, data corresponding to the input signal and an inverted signal thereof is latched, and when the control signal is at the low level, latched data is held. The first and second inverting circuits are operated with a voltage between the first and second potential supplying sources used as a power supply voltage and an output signal whose levels are shifted to the potentials of the first and second potential supplying sources is derived from at least one of the output terminals of the first and second inverting circuits.

According to the level-shift circuit with the above construction, since the feedback type circuit construction is not used and the inverter circuit construction is used, the gate delay is suppressed and the operation speed can be enhanced. Further, since the level-shift of both of the "H" and "L" levels can be effected in one stage, the access time can be reduced when the level-shift circuit is applied to the row decoder circuit of a negative gate erasable type flash memory. Further, since the level-shift of the "H" and "L" levels can be effected in one stage and the operation of latching an input signal can be effected, it can cope with a lowering in the power supply voltage without lowering the operation speed and can be suitably used for the row decoder circuit of the negative gate erasable type flash memory.

The above fourth to sixth objects can be attained by a semiconductor memory device comprising an address buffer to which an address signal is input; an address latch circuit supplied with an output signal of the address buffer; an address counter for counting an input of the address signal; an address multiplexer supplied with output signals from the address buffer, address latch circuit and address counter, for selecting one of the output signals and outputting the selected output signal to an address bus; a redundancy ROM for storing a defective address or addresses; a comparator for comparing an address signal output to the address bus with the defective address stored in the redundancy ROM and outputting a coincidence signal when the compared addresses are coincident with each other; a row pre-decoder for decoding an address signal output to the address bus, the row pre-decoder being de-activated at the time of erasing and when the coincidence signal is output from the comparator; a main decoder supplied with a row pre-decoder signal output from the row pre-decoder and having a main decoder circuit for decoding a row pre-decoder signal output from the row pre-decoder and a first level-shift circuit for shifting the level of a main decoder signal output from the main decoder circuit to select the row of the memory cell array; and a second level-shift circuit for shifting the level of the coincidence signal to select a spare memory cell when the coincidence signal is output from the comparator; wherein the first level-shift circuit includes a first inverting circuit operated with a voltage between a potential of a first potential supplying source and a potential of a second potential supplying source used as a power supply voltage; a second inverting circuit having an input terminal connected to an output of the first inverting circuit and an output terminal connected to an input terminal of the first inverting circuit and operated with a voltage between the potential of the first potential supplying source and the potential of the second potential supplying source used as a power supply voltage; first and second transistors of a first conductivity type whose current paths are serially connected between the input terminal of the first inverting circuit and a third potential supplying source, the gate of the second transistor being supplied with an input signal whose high level is set at a potential of a fourth potential supplying source and whose low level is set at a potential of the third potential supplying source; third and fourth transistors of the first conductivity type whose current paths are serially connected between the input terminal of the second inverting circuit and the third potential supplying source; a control circuit for shifting a low level of an erasing signal to the potential of the second potential supplying source and supplying the level-shifted erasing signal to the gates of the first and third transistors to control the conduction states thereof; and a logic circuit for supplying a logical signal to the gate of the fourth transistor in response to the main decoder signal to control the conduction state thereof; the row of the memory cell array is selected according to an output signal of the second inverting circuit; the second level-shift circuit includes a third inverting circuit operated with a voltage between the potential of the first potential supplying source and the potential of the second potential supplying source used as a power supply voltage; a fourth inverting circuit having an input terminal connected to an output of the third inverting circuit and an output terminal connected to an input terminal of the third inverting circuit and operated with a voltage between the potential of the first potential supplying source and the potential of the second potential supplying source used as a power supply voltage; fifth and sixth transistors of the first conductivity type whose current paths are serially connected between the input terminal of the third inverting circuit and the third potential supplying source, the gate of the fifth transistor being supplied with the coincidence signal whose high level is set at the potential of the fourth potential supplying source and whose low level is set at the potential of the third potential supplying source; seventh and eighth transistors of the first conductivity type whose current paths are serially connected between the input terminal of the fourth inverting circuit and the third potential supplying source; a second control circuit for shifting the low level of the erasing signal to the potential of the second potential supplying source and supplying the level-converted erasing signal to the gates of the fifth and seventh transistors to control the conduction states thereof; and a second logic circuit for supplying a logical signal to the gate of the fourth transistor in response to the coincidence signal to control the conduction state thereof; and the spare memory cell is selected according to an output signal of the fourth inverting circuit.

According to the semiconductor memory device with the above construction, since a level-shift circuit having not the feedback type circuit construction but the inverter circuit construction is used, the gate delay is suppressed and the operation speed can be enhanced. Further, since the level-shift of both of the "H" and "L" levels can be effected by use of one level-shift circuit, one level-shift circuit can be used instead of two level-shift circuits and a latch circuit required in the conventional row decoder circuit of the negative gate erasable type flash memory and the access time can be reduced. Further, it is possible to provide a negative gate erasable type flash memory having a level-shift circuit which is provided in the row decoder circuit and in which the level-shift of both of the "H" and "L" levels can be effected in one stage, the operation of latching an input signal can be effected and which can cope with a lowering in the power supply voltage without lowering the operation speed.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a circuit diagram showing the conventional level-shift circuit for effecting the level-shift of "H" level;

FIG. 2 is a circuit diagram showing the conventional level-shift circuit for effecting the level-shift of "L" level;

FIG. 3 is a circuit diagram showing the construction obtained when the level-shift circuits shown in FIGS. 1 and 2 are applied to the row decoder circuit of a negative gate erasable flash memory with much attention given to one word line;

FIG. 4 is a circuit diagram showing an example of the construction of a latch circuit in the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a level-shift circuit according to a first embodiment of this invention;

FIG. 6 is a timing chart for illustrating the operation of the circuit shown in FIG. 5;

FIG. 7 is a circuit diagram showing a level-shift circuit according to a second embodiment of this invention;

FIG. 8 is a circuit diagram showing a level-shift circuit according to a third embodiment of this invention;

FIG. 9 is a circuit diagram showing a level-shift circuit according to a fourth embodiment of this invention;

FIG. 10A is a timing chart for illustrating the operation of lowering the gate potential to solve the problem caused by the withstand voltage of the gate oxide film and the drain withstand voltage in the level-shift circuit in the first to fourth embodiments of this invention;

FIG. 10B is a circuit diagram showing an example of the construction of a potential detection circuit;

FIG. 11 is a circuit diagram showing a row decoder circuit and a peripheral circuit portion relating to the erasing operation, for illustrating an example of the construction obtained when the level-shift circuit of this invention is applied to the row decoder circuit of a negative gate erasable type flash memory;

FIG. 12 is a cross sectional view for illustrating a voltage of application at the time of data writing in a cell transistor of the negative gate erasable type flash memory;

FIG. 13 is a cross sectional view for illustrating a voltage of application at the time of data erasing in a cell transistor of the negative gate erasable type flash memory;

FIG. 14 is a circuit diagram showing an example in which the level-shift circuit of this invention is applied to a row decoder circuit of double word line structure, for illustrating a case wherein the level-shift circuit of this invention is applied to another row decoder circuit;

FIG. 15 is a circuit diagram showing an example of the construction of a main decoder portion in the circuit shown in FIG. 14;

FIG. 16 is a circuit diagram showing an example of the construction of a pre-decoder portion in the circuit shown in FIG. 14; and

FIG. 17 is a circuit diagram showing an example of the construction of a sub-decoder portion in the circuit shown in FIG. 14.

FIG. 5 shows the construction of a level-shift circuit (level conversion circuit) according to a first embodiment of this invention. The level-shift circuit includes P-channel MOS transistors Q9, Q12, N-channel MOS transistors Q10, Q11, Q13 to Q18, a CMOS inverter 24 operated on a power supply potential Vcc and a potential V.sub.L and a CMOS inverter 25. The current paths of the MOS transistors Q9 to Q11 are serially connected between the potentials V.sub.H and V.sub.L, and the current paths of the MOS transistors Q12 to Q14 are serially connected between the potentials V.sub.H and V.sub.L. The gates of the MOS transistors Q9, Q11 are connected to a connection node between the MOS transistors Q12 and Q13, and the gates of the MOS transistors Q12, Q14 are connected to a connection node between the MOS transistors Q9 and Q10. A latch signal LAT is supplied to the gates of the MOS transistors Q10, Q13 to control the ON/OFF states thereof. Further, the backgates of the MOS transistors Q9, Q12 are connected to the potential V.sub.H, and the backgates of the MOS transistors Q10, Q11, Q13, Q14 are connected to the potential V.sub.L. That is, the MOS transistors Q9, Q12 are formed in an N-well region biased by the potential V.sub.H, and the MOS transistors Q10, Q11, Q13, Q14 are formed in an P-well region biased by the potential V.sub.H.

The current paths of the MOS transistors Q16, Q15 are serially connected between the connection node of the MOS transistors Q12 and Q13 and the ground node GND, and the current paths of the MOS transistors Q18, Q17 are serially connected between the connection node of the MOS transistors Q9 and Q10 and the ground node GND. An input signal V.sub.IN is supplied to the gate of the MOS transistor Q15, and an input signal V.sub.IN inverted by the CMOS inverter 25 operated on a voltage between the power supply potential Vcc and the ground potential GND is supplied to the gate of the MOS transistor Q17. Further, an erasing signal ERS is supplied to the gates of the MOS transistors Q16, Q18 via the CMOS inverter 24 operated on a voltage between the power supply potential Vcc and the potential V.sub.L. The backgates of the MOS transistors Q15 to Q18 are connected to the ground node GND. An output signal V.sub.OUT is derived from the connection node between the MOS transistors Q9 and Q10, and an inverted signal V.sub.OUT of the output signal V.sub.OUT is derived from the connection node between the MOS transistors Q12 and Q13.

Next, the operations in the respective modes with the above construction are explained with reference to the timing chart shown in FIG. 6. At the writing time, the latch signal LAT is set to the "L" level, the potential V.sub.L is set to the ground potential GND, and the erasing signal ERS is set to the "L" level. At the address decoding time, the potential V.sub.H is first set at the Vcc level, but after determination, the potential V.sub.H is changed from the Vcc level to the high potential Vpr. Since the MOS transistors Q10, Q13 are set in the non-conductive state by the "L" level of the latch signal LAT, this state is equivalent to a state in which the MOS transistors Q10, Q11, Q13 and Q14 are disconnected from the potential V.sub.L from the DC standpoint. Further, from the AC standpoint, the gate capacitance of the MOS transistor Q11 and the drain capacitance of the MOS transistor Q13 are associated with the node N1 and the gate capacitance of the MOS transistor Q14 and the drain capacitance of the MOS transistor Q10 are associated with the node N2, but the influence by AC can be suppressed to minimum by making the size of the MOS transistors Q10, Q11, Q13, Q14 sufficiently smaller than the size of the MOS transistors Q15 to Q18.

Further, since the gate potentials of the MOS transistors Q16, Q18 are set to the Vcc level and the MOS transistors are set in the conductive state, the sources of the MOS transistors Q16, Q18 can be regarded as being grounded by making the size of the MOS transistors Q16, Q18 sufficiently larger than the size of the MOS transistors Q15, Q17. Therefore, the circuit shown in FIG. 5 becomes substantially equal to the level-shift circuit shown in FIG. 1 at the time of writing and the gate delay caused when V.sub.H is set at Vcc can be regarded substantially equal.

At the verifying time, the operation is similar to that effected at the writing time. Therefore, the level-shift to the "H" level side in the circuit of FIG. 5 is effected in substantially the same manner as in the circuit of FIG. 1.

At the erasing time, the erasing signal ERS is first set to the "L" level, the potential V.sub.L is set to the GND level, the potential V.sub.H is set to the Vcc level and the latch signal LAT is set to the "L" level so as to determine the input signal V.sub.IN. At this time, the output signals V.sub.OUT, V.sub.OUT are respectively set to the Vcc level and GND level when the input signal V.sub.IN is at the "H" level, and respectively set to the GND level (=V.sub.L) and Vcc level when the input signal V.sub.IN is at the "L" level. At this time, if the latch signal LAT is set to the "H" level, the MOS transistors Q9 to Q11 and the MOS transistors Q12 to Q14 effect the inverting operations so as to cause the above-described states to be latched in the above two latches. Next, the erasing signal ERS is set to the "H" level. The gate potential of the MOS transistors Q16, Q18 is set to the potential V.sub.L (=GND level) and the MOS transistors Q16, Q18 are set in the non-conductive state. As a result, the levels of the input signals V.sub.IN and V.sub.IN are not reflected, but since the previous state is latched, the levels of the output signals V.sub.OUT and V.sub.OUT are held. The potential V.sub.L is lowered to a negative potential by a charge pump circuit at the same time that the erasing signal ERS is set to the "H" level. Since the node on the "L" level side of the output signal V.sub.OUT or V.sub.OUT is set at the potential V.sub.L, the node is also set to a negative potential. At this time, since the gate potentials of the MOS transistors Q15, Q17 are set to the Vcc level or GND level, the MOS transistor on the "L" level side is turned ON, but the gate potential of the MOS transistors Q16, Q18 is set at the potential V.sub.L and the MOS transistors Q16, Q18 are set in the OFF state without fail, thereby interrupting the current path to the ground node GND. Therefore, the level-shift to the negative potential can be attained. Even if the size of the MOS transistors Q10, Q11, Q13, Q14 is made smaller than the size of the MOS transistors Q15, Q17, the latch function can be attained without causing any problem.

As described above, the level-shift circuit shown in FIG. 5 can effect the level-shift (level conversion) on the "H" level side and on the "L" level side in one stage of the level-shift circuit.

FIG. 7 shows a level-shift circuit according to a second embodiment of this invention and obtained by omitting the MOS transistors Q10, Q13 in the circuit of FIG. 5. In FIG. 7, portions which are the same as corresponding portions of FIG. 5 are denoted by the same reference numerals and the explanation therefor is omitted. The circuit of FIG. 7 corresponds to the circuit of FIG. 5 in which the latch signal LAT is always kept at the "H" level. However, since the size of the MOS transistors Q15, Q17 can be made sufficiently larger than the size of the MOS transistors Q9, Q10, Q12, Q13, the gate delay will be slightly increased in comparison with the circuit of FIG. 5, but the level-shift function is not influenced at all and the level-shift operation shown by the timing chart of FIG. 6 can be attained.

Next, the R/S type latch function is considered. As is described in the "Description of the Related Art", in the row decoder circuit of a flash memory in which the negative gate erasing is effected, it is necessary to keep the word line which is not desired to be subjected to the erasing process in the selected state and keep the word line from being set to the negative potential. In order to meet the requirement, as shown in FIG. 8, a 2-input NOR gate 26 may be used instead of the inverter 25 in the circuit of FIG. 5. That is, an input signal V.sub.IN is supplied to one input terminal of the NOR gate 26 and a latch signal LAT is supplied to the other input terminal thereof. Further, an output signal of the NOR gate 26 is supplied to the gate of the MOS transistor Q17.

With the above construction, the latch signal LAT is set to the "H" level in a state in which the input signal V.sub.IN is set at the "L" level in the process of latching the output signals V.sub.OUT, V.sub.OUT at the time of erasing. As a result, the output signal V.sub.OUT is latched in the "L" level, that is, in the non-selected state, and an output of the NOR gate 26 is fixed at the "L" level. In a case where it is not desired to be subjected to the erasing process, if an address is selected so as to set the input signal V.sub.IN to the "H" level, the MOS transistor Q15 is turned ON and the output signals V.sub.OUT and V.sub.OUT are respectively set to the GND level and Vcc level and thus inverted into the selected state. After this, even if the input signal V.sub.IN is set back to the "L" level, the output signals V.sub.OUT , V.sub.OUT will not be set back to the selected state since the output signal V.sub.IN of the NOR gate 25 is fixed at the "L" level. Thus, selective application of negative potential like the conventional case can be attained.

As shown in FIG. 9, it is, of course, possible to provide a NOR gate 26 instead of the inverter 25 in the circuit of FIG. 7.

In the circuits of the above first to fourth embodiments, the MOS transistors Q9 to Q14 are operated on the gate potential of .vertline.Vcc.vertline.+.vertline.Ver.vertline., but in a case where the drain withstand voltage and the withstand voltage of the gate oxide film are considered to cause a problem, the gate potential can be lowered to .vertline.Ver.vertline. by lowering the potential V.sub.H, latch signal LAT, input signal V.sub.IN and the power supply voltage Vcc of the inverter 24 (or NOR gate 26) to the ground potential GND while the V.sub.L level is set lower than a preset potential V.sub.T which is lower than Vcc as shown in the timing chart of FIG. 10A. At this time, since the potential difference between the ground potential GND and the potential Ver is higher than Vcc, the latch operation is not influenced. Further, since the potential level of a word line which is not desired to be subjected to the erasing process is not set to the power supply potential Vcc but set to the ground potential GND, it becomes highly resistant to various disturbances.

FIG. 10B shows an example of the construction of a potential detection circuit for determining whether the potential V.sub.L is higher or lower than the potential V.sub.T and detecting the switching timing for lowering the potential V.sub.H to the ground potential GND. The potential detection circuit includes a generator 100 for generating the potential V.sub.L, resistors R1, R2, comparator 110, inverter 120, level shift circuit 130 and inverter 140. The generator 100 outputs a potential V.sub.L ranging from the ground GND level to the potential Ver. The resistors R1, R2 divide the potential difference between a positive reference potential (for example, power supply potential Vcc) and the output potential V.sub.L of the generator 100. The connection node between the resistors R1 and R2 is connected to an inverting input terminal (-) of the comparator 110. A non-inverting input terminal (+) of the comparator 110 is applied with a constant potential used as a reference (for example, it is grounded). The comparator 110 outputs a switching signal which is set to an "H" level or "L" level when the potential at the connection node between the resistors R1 and R2 is higher or lower than the potential V.sub.T, respectively. The switching signal is supplied to the level shift circuit 130. The level shift circuit 130 converts a signal of "H" level (Vcc level) output from a circuit of Vcc power supply system for the generator 100, comparator 110, inverter 120 and the like to a potential of V.sub.H ' level (V.sub.H ' is a constant potential higher than Vcc). The level shift circuit 130 is operated with the potential V.sub.H ' and ground potential GND used as a power supply to shift the "H" level (Vcc level) of the switching signal to V.sub.H ' and then output the same. At this time, the switching signal is output without shifting the "L" level (GND level). The switching signal subjected to the level-shifting by the level shift circuit 130 is supplied to the inverter 140. The inverter 140 is operated with the potential V.sub.H ' and ground potential GND used as a power supply to invert an output signal of the level shift circuit 130 and set the output signal to the V.sub.H level or GND level, respectively, when the potential V.sub.L (erase potential Ver) is higher or lower than the potential V.sub.T. The potential is supplied to the sources of the MOS transistors Q9 and Q12 in the level shift circuit shown in FIGS. 5, 6 to 9.

The table 2 indicates the relation between the various potentials in the respective operation modes.

Next, the operations in the respective modes are explained in detail by taking the circuit of FIG. 5 as an example. The erasing mode is executed in three steps. The first step is to write input data into a latch circuit constructed by a first inverting circuit formed of MOS transistors Q9 to Q11 and a second inverting circuit formed of MOS transistors Q12 to Q14. That is, when an input signal V.sub.IN is input, one of the MOS transistors Q15 and Q17 is turned ON and the other is turned OFF in response to the input signal. At this time, since the erasing signal ERS is set at the "L" level, an output of the inverter 24 is set to the "H" level so as to set the MOS transistors Q16 and Q18 in the ON state. As a result, the potential level of one of the nodes N1 and N2 is lowered to the ground potential GND. For example, data 1 is input as an input signal V.sub.IN to the level shift circuit connected to the word line used for the erasing operation. Data 0 is input as an input signal V.sub.IN to the level shift circuit connected to the word line which is not used for the erasing operation. When a latch signal LAT is set to the "H" level, the MOS transistors Q10 and Q13 are turned ON and the two inverter circuits effect the inverting operation to amplify and latch the potential difference between the nodes N1 and N2. At this time, the potential V.sub.H is positive and is set at the Vcc level, for example, and the potential V.sub.L is set at the potential Ver (GND level).

When the erasing signal ERS is raised to the "H" level, the MOS transistors Q16, Q18 are turned OFF to start the second step. In the second step, the potential V.sub.L is lowered to a negative potential (0>Ver>V.sub.T).

If the potential detection circuit shown in FIG. 10B detects that the potential V.sub.L becomes lower than the potential V.sub.T, the third step is started and the potential V.sub.H is lowered to the ground potential GND. The erasing potential Ver (0>VT.gtoreq.Ver) is applied to the potential V.sub.L to effect the erasing operation. As a result, the potential difference between the potential V.sub.H and the potential V.sub.L is reduced so as to alleviate the stress applied to the MOS transistors Q9 Q14.

After the erasing operation is completed, the potential V.sub.L is raised from Ver (.ltoreq.V.sub.T) to the ground potential GND in the order opposite to the order of the above steps and the erasing mode is terminated.

The levels of the potentials V.sub.H, V.sub.L in the write mode, verify mode, and readout mode are the same as those in the table 1. In the above modes, both of the latch signal LAT and erasing signal ERS are set to the "L" level. As a result, the MOS transistors Q10, Q13 are turned OFF and MOS transistors Q16, Q18 are turned ON. In this state, the circuit of FIG. 5 effects substantially the same operation as the circuit of FIG. 1.

The operation of the respective modes are explained by taking the circuit of FIG. 5 as an example, but substantially the same operation can be attained in the circuit of FIGS. 7 to 9. However, in the circuit of FIG. 7, control of the latch operation by used of the latch signal LAT is not effected.

As described above, since the "H" level-shift, "L" level-shift and the latch function for selection of the presence or absence of the "L" level-shift can be attained in one stage of level-shift circuit, the decoding operation for negative gate erasing can be realized at substantially the same speed as the decoding operation for source erasing. Further, since the level-shift on the "L" level side is effected by use of a latch, the "H" level side potential can be set to the GND level at the time of application of a negative potential so that the operating potential can be lowered. Further, the potential level of the word line to which the negative bias is not applied can be set to the ground potential GND, and the disturbance caused by biasing of the source and gate and application of the stress on the defective word line relieved by the redundancy can be avoided.

FIG. 11 shows an example of the construction obtained when the level-shift circuit of this invention is applied to the row decoder circuit of a negative gate erasable type flash memory. The circuit shown in FIG. 11 contains a row decoder circuit in the flash memory and a peripheral circuit portion relating to the erasing operation. An address signal Add externally supplied is input to an address buffer 31 and an output of the address buffer 31 is supplied to an address multiplexer 32 and address latch circuit 33. An output of the address latch circuit 33 and an output of an address counter 34 are supplied to the address multiplexer 32 which in turn selects one of the outputs of the address buffer 31, address latch circuit 33 and address counter 34 and outputs the selected output to an internal address bus AB. An address signal output to the internal address bus AB is supplied to a row pre-decoder 35 and comparator 36. The row pre-decoder 35 is constructed by AND gates 37, 37, . . . which are supplied with a row address signal RAdd among the address signal supplied via the internal address bus AB. Further, each of the AND gates 37, 37, . . . is supplied with an activation signal PRE output from an NOR gate 38 for the row pre-decoder 35 and the operation thereof is controlled.

The comparator 36 compares an address supplied via the internal address bus AB with a defective address stored in a redundancy ROM 39 and outputs a coincidence signal HIT when the compared addresses coincide with each other. The redundancy ROM 39 stores addresses of the defective cells and the ROM 39 is designed to store bits of a number corresponding to the number of row addresses for row redundancy. On the other hand, in a case where the defective word line is replaced for each line, all of the row addresses are stored in the redundancy ROM 39. Further, in a case where the replacement of word lines is effected for every 2.sup.n lines such as 2 rows, 4 rows, the number of addresses to be stored may be reduced by n bits. Data may be stored by use of a flash memory or a method of storing defective addresses by providing fuses of polysilicon and selectively melting the fuses by laser may be used.

Thus, defective addresses are previously stored in the redundancy ROM 39 and whether the selected address coincides with the defective address or not is always checked by the comparator 36. If the selected address coincides with the defective address, the coincidence signal HIT is set to the "H" level. As a result, the activation signal PRE is set to the "L" level to activate the pre-decoder 35 and set the defective row into the non-selected state, and a spare word line SWL is driven by an output of a level-shift circuit 46 of a spare row decoder 45 to substitute the spare cell. The replacement of the cells is effected in the same manner as in the EPROM. At the time of erasing, since the word lines WL are collectively operated and set into the non-selected state and subjected to the flash erasing process together with the spare row, no particular control by redundancy is effected.

The NOR gate 38 is supplied with the coincidence signal HIT and erasing signal ERS to inhibit the output of the row pre-decoder 35 (fix the output at the "L" level) in the erasing mode when the input address coincides with the defective address.

A row pre-decoder signal RPD output from the row pre-decoder 35 is supplied to a main decoder 40. In the main decoder 40, AND gates 42, 42, . . . and level-shift circuits 43, 43, . . . corresponding to the word lines WL of a memory cell array 41 are provided. As the level-shift circuit 43, the level-shift circuit shown in the first to fourth embodiments is used.

The memory cell array 41 is a cell block which is collectively and simultaneously erased, and although not shown in the drawing, the sources of the cell transistors are commonly connected in the array 41 and biased by an erasing potential at the erasing time. At the other operation time such as writing or readout time, the common sources are grounded. On the other hand, the drains of the cell transistors are commonly connected for each column to respective bit lines arranged to intersect the word lines WL. Since the drains set in the open state at the erasing time as described before, no special decoding operation is necessary and the explanation therefor is omitted here.

In the memory cell array, cell transistors MC having the cross section as shown in FIGS. 12 and 13 are arranged on the rows and columns. FIG. 12 shows the relation of potentials applied at the time of data writing, and FIG. 13 shows the relation of potentials applied at the time of data erasing. That is, a source region 14 and drain region 15 of a second conductivity type are separately formed in the main surface area of a semiconductor substrate 13 of a first conductivity type. A tunnel oxide film 16, floating gate 17, insulative film (which is called an inter-polysilicon insulative film) 18 and control gate 19 are stacked on the channel region between the source region 14 and the drain region 15.

At the writing time, as shown in FIG. 12, the source region 14 is grounded, a potential Vg (Vg=Vpr>Vcc) and potential Vd (Vd>0) are respectively applied to the control gate 19 and drain region 15. With the application of the above potentials, hot electrons are injected into the floating gate 17 to write data. On the other hand, at the erasing time, as shown in FIG. 13, a positive high potential Vs (Vs>0) is applied to the source region 14 and a negative potential Vg (Vg=Ver<0) is applied to the control gate 19 to set up an intense electric field across the tunnel oxide film 16, thereby extracting electrons in the floating gate 17 by a tunnel current (this is called negative gate erasing). In the negative gate erasing, since a negative potential is applied to the control gate 19, the potential applied to the source region 14 can be suppressed to a lower level in comparison with a method of erasing data by applying a ground potential to the control gate (this is called a source erasing method).

The coincidence signal HIT output from the comparator 36 is supplied to the spare row decoder 45 as described above. In the spare row decoder 45, the level-shift circuit of one of the first to fourth embodiments is used and the spare word line SWL connected to the spare memory cell SMC is driven by an output of the circuit 46. In order to simplify the explanation, a case wherein one spare word line SWL is used is shown in FIG. 11, it is, of course, possible to use a plurality of spare word lines and select the word line by use of the spare row decoder 45.

Next, the operation of the above construction is schematically explained. At the time of readout or writing, it is necessary to select the word lines WL in the memory cell array 41 one at a time according to the row address Add. In the circuit shown in FIG. 11, the row address Add designated by an address counter or the like in the chip or an external input is decoded by the pre-decoder 35 and is then further decoded by the main decoder 40 to select one of the word lines WL.

The level-shift circuits 43, 46 are designed to effect the level-shift of both of the "H" level and "L" level in one stage, and the level-shift circuit 43 can effect the operation of latching an output signal of a corresponding one of the AND gates 42, 42, . . . and the level-shift circuit 46 can effect the operation of latching a coincidence signal HIT. Further, the circuit can cope with a lowering in the power supply voltage without lowering the access speed. Therefore, the circuit is suitable for the negative gate erasable flash memory as shown in FIG. 11.

FIG. 14 is a circuit diagram showing an example in which the level-shift circuit of this invention is applied to another row decoder circuit which is the row decoder of a flash memory of double word line structure. The address signal Add is supplied to pre-decoders 51.sub.1, 51.sub.2, 51.sub.3, . . . , 51.sub.n and an output signal PRDa of the pre-decoder 51.sub.1 is supplied to main decoders 52.sub.1, 52.sub.2, . . . are supplied to sub-decoders 53.sub.1, 53.sub.2, . . . , 53.sub.n-1. The memory cell array is divided into sub-arrays 54.sub.1, 54.sub.2, . . . , 54.sub.n-1 and main word lines MWL, MWL, . . . are arranged across the sub-arrays 54.sub.1, 54.sub.2, . . . , 54.sub.n-1. The main word lines MWL, MWL, . . . are connected to the sub-decoders 53.sub.1, 53.sub.2, . . . , 53.sub.n-1 and are respectively driven by the main decoders .sup.52.sub.1, 52.sub.2, . . . In each of the sub-arrays 54.sub.1, 54.sub.2, . . . , 54.sub.n-1, word lines WL are provided. The word lines WL, WL, . . . are connected to memory cells (not shown) and are driven by the sub-decoders 53.sub.1, 53.sub.2, . . . , 53.sub.n-1.

Level-shift circuits having the same construction as one of the level conversion circuits shown in FIGS. 5, 7, 8 and 9 are provided in the pre-decoders 51.sub.1, 51.sub.2, . . . , 51.sub.n and main decoders 52.sub.1, 52.sub.2, . . .

The address signals Add are supplied to the pre-decoders 51.sub.1, 51.sub.2, . . . , 51.sub.n and decoded by the respective pre-decoders. The pre-decoder signal PRDa output from the pre-decoder 51.sub.1 is supplied to the main decoders 52.sub.1, 52.sub.2, . . . , and pre-decoder signals PRDb output from the pre-decoders 51.sub.2, 51.sub.3, . . . , 51.sub.n are respectively supplied to the sub-decoders 53.sub.1, 53.sub.2, . . . , 53.sub.n-1 The word lines WL, WL, . . . are selected by the main decoders 52.sub.1, 52.sub.2, . . . and the word lines WL are selected by the sub-decoders 53.sub.1, 53.sub.2, . . . , 53.sub.n-1 according to the output signals of the main decoders 52.sub.1, 52.sub.2, . . . supplied to the main word lines WL, WL, . . . and pre-decoder signals PRDb output from the pre-decoders 51.sub.2, 51.sub.3, . . . , 51.sub.n.

FIG. 15 shows an example of the construction of main decoders 52.sub.1, 52.sub.2, . . . in the circuit shown in FIG. 14 with much attention given to a pair of main word lines MWLi, MWLi. For example, the pre-decoder signal PRDa is decoded by a main decoder portion 55 constructed by an AND gate and a decoded output is supplied to a level-shift circuit 56. The level-shift circuit 56 has substantially the same construction as the circuit shown in FIG. 5, 7, 8 or 9 and shifts the level of an output signal of the main decoder portion 55 and supplies the level-shifted signal to the main word line MWLi. Further, an output signal of the level-shift circuit 56 is output to the main word line MWLi via an inverter 57 operated with the potentials V.sub.H and V.sub.L used as the power supply voltage.

FIG. 16 shows an example of the construction of the pre-decoders 51.sub.2, 51.sub.3, . . . , 51.sub.n in the circuit shown in FIG. 14 with much attention given to the 1-bit pre-decoder signal PRDb. A pre-decoder portion 58 constructed by an AND gate is supplied with an address signal Add and an output signal of the pre-decoder portion 58 is supplied to a level-shift circuit 59. The level-shift circuit 59 has substantially the same construction as the circuit shown in FIG. 5, 7, 8 or 9, and shifts the level of an output signal of the pre-decoder portion 58 and outputs a pre-decoder signal PRDb.

FIG. 17 shows an example of the construction of the sub-decoders 53.sub.1, 53.sub.2, . . . , 53.sub.n-1 in the circuit shown in FIG. 15 with much attention given to one sub-array 54.sub.1. Each of the word lines WL in the sub-array 54.sub.1 is driven via one of a pair of transfer gates 60.sub.1 and 60.sub.2. The pre-decoder signal PRDb is supplied to one end of the transfer gate 60.sub.1 and the other end thereof is connected to the word line WL. One end of the other transfer gate 60.sub.2 is connected to the above word line WL and the other end thereof is applied with a potential V.sub.L. The gates of an N-channel MOS transistor 61 and a P-channel MOS transistor 62 of the respective transfer gates 60.sub.1 and 60.sub.2 are connected to the main word line MWLi and the gates of a P-channel MOS transistor 63 and an N-channel MOS transistor 64 of the respective transfer gates 60.sub.1 and 60.sub.2 are connected to the main word line MWLi.

In the row decoder circuit with the above double word line structure, the basic operation is the same as that of the row decoder circuit shown in FIG. 11, and the "H" level and "L" level can be converted in one stage by providing the level-shift circuit shown in the first to fourth embodiments in the row decoder circuit. Further, the operation of latching output signals of the AND gates 55, 58 can be effected and a lowering in the power supply voltage can be coped with without lowering the access speed.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and representative devices shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.