DRAM Controller With Background Refresh

This invention relates generally to dynamic random access memory controllers and more particularly to a novel dynamic random access memory controller with a variable refresh cycle.

Memory devices are used on various types of electronic equipment, including general purpose computers, such as "personal computers," as well as special purpose computers, such as electronic switches for telephone systems. One type of a memory device is a dynamic random access memory device ("DRAM"). Typically, electronic devices use DRAM to store information for retrieval at a later time. A memory element of a DRAM can maintain information for only a short period of time, typically less than a thousandth of a second. Accordingly, a DRAM must be periodically "refreshed" to maintain information over longer periods of time. Such refreshes are typically performed at fixed intervals of time. During such a refresh operation ("refresh cycle"), the DRAM is not available for information storage or retrieval operations ("write cycle" and "read cycle," respectively). Thus, periodic refresh cycles occurring at fixed intervals may be detrimental to system performance, such as when the fixed interval refresh cycles interfere with write cycles or read cycles.

The present invention avoids degradation of performance which may be caused by imposing fixed interval refresh cycles on a DRAM. According to one embodiment, with respect to a DRAM having a maximum refresh interval, a DRAM controller performs a background refresh cycle by measuring a time interval after a refresh cycle, monitoring a memory request input of the DRAM for an idle period after a measured time interval substantially less than the maximum refresh interval., and refreshing the DRAM with a refresh cycle upon detecting one of an idle period and a measured time interval of the maximum refresh interval.

FIG. 1 is a block diagram of an example of a microprocessor connected to a DRAM controller of the present invention.

FIG. 2 is a block diagram of one embodiment of a DRAM controller and refresh timer according to the present invention.

FIG. 1 shows an example of a microprocessor and memory configuration. A microprocessor 10 is connected to a DRAM 12 by a data bus 14, and an address bus 16. The data bus 14 may comprise a single connection, or, alternatively, a plurality of parallel connections. Typically, the address bus 16 comprises a plurality of parallel address connections and an address control line 18. It should be noted that "parallel," with respect to the data and address busses, is used in the logical sense (e.g., an 8 bit wide parallel bus) and does not necessarily require the electrical connections to be physically parallel to each other. Typically, the data bus 14 is connected to the memory elements 20 of the DRAM 12 while the address bus 16 and the control line 18 are connected to a DRAM controller 22.

FIG. 2 illustrates memory elements 20 and a portion of the control elements for the DRAM controller 22, including an embodiment of the present invention. The control elements include a bus monitor 32, a refresh timer 34, an arbitration circuit 36, and a refresh controller 38. The refresh controller 38 is connected to the address bus 16 and one or more control lines 18 from the microprocessor. A refresh control line 40 connects the refresh controller 38 to the memory elements 20.

The memory elements 20 are typically refreshed periodically to maintain information stored in the memory elements. In one embodiment, the maximum refresh time interval for the DRAM is 15.3 microseconds (.mu.s). However, alternative DRAMs may have differing maximum refresh time intervals.

In one approach, the DRAM is refreshed when the refresh controller 38 temporarily sets the refresh control line 40 to an active state. The term "refresh strobe" refers to temporarily setting the refresh control line 40 to the active state. The active state may be a logical "high" or "low" signal. The refresh controller 38 is connected to the arbitration circuit 36 via a refresh requested control line 42. The refresh controller 38 issues a refresh strobe on the refresh control line 40 when the refresh requested control line 42 is set to its active state.

In the illustrated embodiment, the refresh timer 34 is connected to the refresh controller 38. The refresh timer 34 is reset when the refresh controller 38 refreshes the memory elements. The reset of the refresh timer 34 may be accomplished with an individual timer reset line 44, as shown in FIG. 2, or, alternatively, with the refresh strobe. The refresh timer 34 includes two outputs, a background refresh control line 46 and a priority refresh control line 48. The refresh timer may be implemented in hardware or software. A hardware timer may include a counter circuit that counts clock pulses of a predetermined period. Alternatively, an R-C discharge circuit may be used.

When the refresh timer 34 is reset, both outputs are set to their respective inactive status. The refresh timer 34 sets the background refresh control line 46 to its active state after a predetermined interval of time has elapsed which is substantially less than the maximum refresh time interval. In one embodiment, the refresh timer 34 sets the background refresh control line 46 to its active state after an interval of time equal to approximately one-half the maximum refresh time interval has elapsed, which is approximately 8 .mu.s. The refresh timer 34 sets the priority refresh control line 48 to its active state after a second predetermined interval of time has elapsed, which is longer than the first predetermined interval of time, but not longer than the maximum refresh time interval. In one embodiment, three fourths of the maximum refresh time interval is selected as the second predetermined time interval. In the illustrated embodiment, the refresh timer 34 sets the priority refresh control line 48 to its active state after approximately 12 .mu.s has elapsed since the last refresh cycle.

In the illustrated embodiment, the bus monitor 32 is connected to the address bus 16, including the address control line 18. In the embodiment shown, the bus monitor 32 monitors the activity of the address control line 18 for an address strobe. The term "address strobe" refers to temporarily setting the address control line 18 to its active state. An address strobe occurs when the microprocessor 10 issues a memory request, such as a read cycle or a write cycle, to a particular DRAM 12. Alternatively, the bus monitor 32 may also monitor the address bus 16 or the data bus 14 for valid addresses or data respectively. A comparitor may be used to determine whether valid addresses or data are present. Activity on the address control line 18 indicates that the microprocessor is executing a read cycle or a write cycle on the memory elements. A lack of activity on the address bus indicates that the DRAM 12 is in an idle period. A lack of activity includes cycles when there is no valid address, or if a valid address is present, the address is outside a range of addresses serviced by the DRAM 12. In this alternative embodiment, the bus monitor 32 sets a bus active control line 50 to its active state when the bus monitor 32 detects a lack of activity on the address bus 16 and/or address control line 18.

A lack of activity on the address bus 16 and/or address control line 18 may be referred to as an "idle period." An idle period does not necessarily indicate that the processor 10 is idle, but rather indicates that a particular DRAM 12 is not being accessed by the processor 10. For example, the processor 10 may be accessing additional DRAM. However, the processor 10 may also be accessing other memory elements, such as SRAM or ROM, or various input/output ports or peripheral devices. Thus, while an idle period may be expected to have a duration approximately equal to a read or write cycle for a DRAM, any given idle period may be shorter or longer than a DRAM read or write cycle.

In the illustrated embodiment, the arbitration circuit 36 is connected to the bus active control line 50, the background refresh control line 46, and priority refresh control line 48. In one embodiment, the arbitration circuit 36 sets the refresh requested control line 42 to its active state when the background refresh control line 46 and the bus activity control line 50 are set to their respective active states. The arbitration circuit 36 also sets the refresh requested control line 42 to its active state when the priority refresh control line 48 is in its active state, regardless of the states of the bus activity control line 50 or the background refresh control line 46. Known logic gates, such as an AND gate and an OR gate, may comprise the arbitration circuit.

In operation of the illustrated embodiment, the refresh timer 34 is reset when the refresh controller 38 refreshes the memory elements. Immediately after a refresh timer 34 is reset, both the background refresh control line 46 and priority refresh control line 48 are set to their respective inactive states. In one embodiment, after about one-half of the maximum refresh time interval of the DRAM has elapsed, the reset timer 34 sets the background refresh control line 46 active. However, various time intervals less than the maximum refresh time interval are contemplated.

In the illustrated embodiment, when the background refresh control line 46 is active, a refresh may be requested by the arbitration circuit 36 depending on the activity of the address bus 16. Should the bus monitor 32 detect an idle period where the address bus 16 is inactive, thereby setting the bus activity control line 50 to its active state, during a time when the background refresh control line 46 is active, the arbitration circuit 36 will set the refresh requested control line 42 active and the refresh controller 38 will generate a refresh strobe to refresh the memory elements 20 and reset the refresh timer 34. Ideally, the entire refresh cycle will be completed prior to the end of the idle period. When a background refresh is thus performed, system performance may be enhanced because the refresh cycle occurred during an idle period for the DRAM 12 and did not interfere with an attempt by the microprocessor 10 to execute a read cycle or a write cycle.

It should be noted that executing such a background refresh does not absolutely guarantee that the processor 10 will not attempt to access the DRAM 12 during a refresh cycle. The likelihood exists that the processor 10 will eventually attempt to execute a memory access during a refresh cycle. In that event, the processor 10 has to wait until the end of the refresh cycle. However, one may adjust the periods for the refresh timer 34, depending on the processor, DRAM, and clock speeds selected, to minimize the possibility of a conflict. Performance may be substantially improved by minimizing conflicts between the processor 10 and the refresh cycle in this way, even if the potential for conflict is not completely eliminated.

Should the address bus 16 remain active, thereby inhibiting a background refresh as described above, the bus timer 34 will set the priority refresh control line 48 to its active state after most (in one example, approximately three fourths) of the maximum refresh time interval has elapsed. When the priority refresh control line 48 is active, the arbitration circuit 36 sets the refresh requested control line 42 active regardless of whether there is any address bus 16 activity. The refresh controller 38 then refreshes the memory elements of the DRAM 20 and resets the refresh timer 34. While a refresh cycle initiated pursuant to a priority refresh may interfere with microprocessor 10 access to the memory elements 20, a priority refresh is preferable to loss of information in the memory elements of the DRAM 20.

The foregoing description is given for clarity of understanding of the invention. It is to be understood that various changes can be made by one skilled in the art to the above described DRAM controller without departing from the scope or spirit of the invention.