Method and Apparatus for Scheduling Instructions for Execution on a Multi-Issue Architecture Computer

1. Field of the Invention

The present invention relates to the field of computer systems, in particular, computer systems that support multiple instruction issues, also known as superscalar computer systems. More specifically, the present invention relates to instruction scheduling performed by compilers targeting these computer systems.

2. Background

Various compiler scheduling techniques are employed in the art for scheduling a basic instruction block targeted for a multi-issue architecture computer system, also known as a superscalar computer system. Their common objective is to find the shortest schedule that maximizes the amount of parallel execution for the basic block. The common constraints they face are in resource and precedence. At any instance in time, the total usage of any type of resources by the instructions to be executed in parallel must not exceed the resources available on the targeted machine for the particular resource type. Additionally, instructions with dependencies on other instructions cannot be scheduled before their dependencies are resolved.

Among these prior-art techniques, list scheduling is probably the most popular, perhaps because of its effectiveness and ease of implementation. Under list scheduling, the "optimal" schedule is determined iteratively using a candidate instruction list comprising candidate instructions that are ready to be scheduled. At each iteration, a candidate instruction is selected for scheduling based on some priority functions. The "best" schedule slot, without violating the resource and precedence constraints, is assigned to the selected instruction. The candidate list is then refreshed, and the process is repeated until the candidate list becomes empty. Typically, the candidate instructions for the candidate instruction list are identified using either a "top down" (predecessor free) or a "bottom up" (successor free) approach, and the priority functions for selecting one of the candidate instructions are evaluated without distinguishing instructions that can be issued with other instructions from instructions that cannot be issued with any other instructions.

For basic blocks that are program loops, software pipelining has been additionally employed to further increase the amount of parallelism by exploiting the repetitive nature of program loops. Under software pipelining, subject also to resource and precedence constraints, a program loop is continuously initiated at constant intervals, before the preceding iterations complete. At steady state, n iterations are concurrently being executed, each iteration potentially having multiple instructions scheduled for parallel execution. Thus, at any instance in time, the total usage of any type of resources by the instructions of one iteration of the program loop to be executed in parallel must not exceed the modulo resources available on the targeted machine for the particular resource type for one iteration of the program loop. As a result, an attempt to list schedule a program loop with software pipelining may fail for a particular schedule size. Therefore, when list scheduling with software pipelining is employed to schedule a program loop, the "optimal" schedule is determined through repeated attempts to schedule the program loop in schedules of various schedule sizes, typically starting with the smallest schedule (maximum compaction) and gradually increasing the schedule size towards the largest schedule (zero compaction). For each attempt, the program loop is list scheduled as described earlier. If the attempt fails, the process is repeated until either an attempt is successful or the largest schedule (zero compaction) is reached.

Since it is not uncommon for programs to include program loops that get executed over and over again, even a single instruction saving in the execution schedule could still potentially mean a large amount of savings in execution time. Therefore, while the prior art list scheduling technique, with or without software pipelining, generally generates pretty effective schedules, it is nevertheless desirable if it can be improved upon. As will be disclosed, the present invention provides an improved method and apparatus for list scheduling instructions of a basic block targeted for a multi-issue architecture computer system.

In the context of the present invention, a squeezed instruction is an instruction that cannot be scheduled for parallel execution with any other instructions on the targeted machine. On the other hand, a non-squeezed instruction is an instruction that can be scheduled for parallel execution with at least one other instruction on the targeted machine.

The improved parallelism in the generated schedules of the basic blocks of a program being compiled is advantageously achieved under the present invention by providing an improved scheduler incorporated with the teachings of the present invention to the code generator of a compiler. The improved scheduler implements the prior-art list scheduling technique with a number of improvements including the differentiation of squeezed and non-squeezed instructions, employing priority functions that factor in the squeezed and non-squeezed instruction distinction for selecting a candidate instruction, tracking only the resources utilized by the non-squeezed instructions, and tracking the scheduling of the squeezed and non-squeezed instructions separately.

More specifically, in one embodiment, the improved scheduler employs a resource utilization array and an instruction tracking array to determine whether a basic block can be scheduled with a schedule of a particular schedule size. The resource utilization array is initialized to a size that is sufficiently large for the targeted machine's architecture. The resource utilization array is used to track only the resources utilized by the non-squeezed instructions. The instruction tracking array is initialized in accordance to the number of instructions in the basic block. The instruction tracking array is used to track the scheduling of the squeezed and non-squeezed instructions separately.

Additionally, in this embodiment, the improved scheduler identifies the candidate instructions for the candidate instruction list using a bottom up (successor free) approach. At each iteration, the improved scheduler selects a candidate instruction to schedule based on the relative chain lengths of the predecessor non-squeezed instruction chains. The presence of squeezed instructions in a predecessor chain is considered only for tie-breaking, in the event that there are more than one predecessor non-squeezed instruction chain having the same longest chain length.

When software pipelining is additionally employed to list schedule a program loop, the improved scheduler repeatedly attempts to schedule the program loop for various schedule sizes as described above, starting with the smallest schedule (maximum compaction) and systematically increasing the schedule size towards the largest schedule (zero compaction) until either an attempt is successful or the largest schedule is reached. However, the improved scheduler factors only the non-squeezed instructions in the smallest schedule (initiation internal) size calculation.

The objects, features, and advantages of the present invention will be apparent from the following detailed description of the presently preferred and alternate embodiments of the invention with references to the drawings in which:

FIG. 1 illustrates an exemplary computer system incorporated with the teachings of the present invention.

FIG. 2 illustrates the software elements of the exemplary computer system of FIG. 1.

FIGS. 3a-3b illustrate one embodiment of the exemplary compiler of FIG. 2.

FIGS. 4a-4b illustrate the resource utilization array and the instruction tracking array employed by the improved scheduler of FIG. 3b to determine whether a basic block can be scheduled with a schedule of a particular schedule size under the present invention.

FIG. 5 illustrates the improved list scheduling technique of the present invention for scheduling a basic block.

FIGS. 6a-6b illustrate the improved list scheduling technique of the present invention for scheduling a program loop when software pipelining is additionally employed.

FIGS. 7a-7b illustrate an exemplary program loop in C and FORTRAN.

FIGS. 8a-8b illustrate the exemplary instructions to be scheduled for the exemplary program loop of FIGS. 7a-7b, and the precedence constraints on scheduling these exemplary instructions.

FIGS. 9a-9h illustrate the process for scheduling the exemplary instructions of FIGS. 7a-7b.

FIGS. 10a-10b contrast the schedules generated for the exemplary instructions of FIGS. 7a-7b under the present invention and the prior art.

In the following description for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well known systems are shown in diagrammatical or block diagram form in order not to obscure the present invention unnecessarily.

Referring now to FIGS. 1, a block diagram illustrating an exemplary multi-issue architecture computer system incorporated with the teachings of the present invention is shown. The exemplary multi-issue architecture computer system 10 comprises a central processing unit (CPU) 12, a memory 14, and an I/O module 16. Additionally, the exemplary multi-issue architecture computer system 10 also comprises a number of input/output devices 18 and 20, and a number of storage devices 22. The CPU 12 is coupled to the memory 14 and the I/O module 16. The input/output devices, 18 and 20, and the storage devices 22 are also coupled to the I/O module 16. The I/O module 16 in turn is coupled to a network.

The CPU 12 comprises an instruction dispatcher (not shown) for fetching and dispatching multiple instructions simultaneously. Additionally, the CPU 12 comprises resources such as integer units, floating point units (not shown) for executing these simultaneously issued instructions in parallel. Except for the manner it is used to practice the present invention, the CPU 12 is intended to represent a broad category of execution units found in many multi-issue architecture or superscalar computers. Similarly, except for the manner they are used to practice the present invention, the memory 14, the I/O module 16, the input/output devices, 18 and 20, the storage devices 22, and the network, are intended to represent a broad category of these hardware elements found in most computer systems. Thus, the constitutions and basic functions of these elements are well known and therefore will not be otherwise further described.

FIG. 2 illustrates the software elements of the exemplary computer system of FIG. 1. Shown are application programs 26 compiled using the compiler 34 incorporated with the teachings of the present invention. The compiled application programs 26 access the runtime libraries 34 for services during execution, which in turn access the operating system 32 for system services. The compiler 34 also accesses the operating system 32 for system services during compilation of application programs 26. Similar to the hardware elements, except for teachings of the present invention incorporated in the compiler 34, these software elements are intended to represent a broad category of similar software elements found in most computer systems. The constitutions and basic functions of these elements are well known and will not be otherwise further described.

While for ease of explanation, the present invention is being described with the compiler incorporated with the teachings of the present invention executing on a multi-issue architecture computer system, it will be appreciated that the present invention may be practiced with the improved compiler executing on a standard scalar computer, only the generated instructions have to be executed on a multi-issue architecture computer.

Referring now to FIGS. 3a-3b, two block diagrams illustrating one embodiment of the compiler of FIG. 2 is shown. As illustrated in FIG. 3a, in this embodiment, the compiler 34 comprises a parser 38, an intermediate representation builder 40, and a code generator 42 incorporated with the teachings of the present invention. The parser 38 receives the source code of a program to be compiled as inputs. In response, it parses the source language statements and outputs tokenized statements. The intermediate representation builder 40 receives the tokenized statements as inputs. In response, it constructs intermediate representations for the tokenized statements. The code generator 42 receives the intermediate representations as inputs. In response, it generates object code for the program. Except for teachings of the present invention incorporated in the code generator 42, these components are intended to represent a broad category of similar components found in most compilers. The constitutions and basic functions of these components are well known and will not be otherwise further described here.

As illustrated in FIG. 3b, in this embodiment, the code generator 42 comprises a translator 44, an optimizer 46, a register allocator 48, a loop unroller 50, a scheduler 52, and an assembly code generator 54. The translator 44 receives the intermediate representations as inputs. In response, the translator 44 builds the loop table, orders instruction blocks, constructs data flow graphs etc. The optimizer 46 receives the intermediate representations and associated information as inputs, including the loop table and the data flow graph. In response, it performs various optimizations. The register allocator 48 receives the optimized intermediate representations and associated information as inputs. In response, it allocates registers of the exemplary multi-issue architecture computer system of FIG. 1 to the instructions being generated. The loop unroller 50 receives the optimized intermediate representations with allocated registers and associated information as inputs. In response, it restructures the instructions being generated, unrolling loops in the instructions being generated for an optimal amount of time consistent with the resources available in the exemplary multi-issue architecture computer system of FIG. 1. The scheduler 52 receives the restructured intermediate representations and associated information as inputs. In response, it further restructures the instructions to be generated for parallelism. Lastly, the assembly code generator 54 receives the optimized, register allocated, and restructured intermediate representations and associated information as inputs. In response, it generates the object code for the program being compiled. Except for the teachings of the present invention incorporated in the scheduler 52, the optimizer 46, the translator 44, the register allocator 48, the loop unroller 50, and the assembly code generator 54, are intended to represent a broad category of similar modules found in most code generators. The constitutions and basic functions of these modules are well known and will not be otherwise further described.

While for ease of understanding, the code generator 42 is being described with the above described embodiment which allocates registers before unrolling the loops in the instructions being generated and scheduling instructions for parallelism, based on the descriptions to follow, it will be appreciated that the present invention may be practiced with other register allocation, loop unrolling and scheduling approaches having different register allocation, loop unrolling and scheduling order.

Referring now to FIGS. 4a-4b, two block diagrams illustrating the resource utilization and instruction tracking arrays employed by the improved scheduler of FIG. 3b are shown. The resource utilization array 56 and the instruction tracking array 58 are employed by the improved scheduler to determine whether a basic block can be scheduled in a schedule of a particular schedule size. The resource utilization array 56 is used to track the resource utilization of the non-squeezed instructions, i.e. those instructions that can be scheduled for parallel execution with other instructions. As will be discussed in further detail later, the resource utilization of the squeezed instruction, i.e. those instructions that cannot be scheduled for parallel execution with any other instruction, are not tracked. The resource utilization array 56 comprises n rows, one for each non-squeezed schedule slot of the schedule under consideration, and r columns, one for each resource element to be tracked. The resource utilization array 56 is initialized in accordance with the schedule size being considered. When list scheduling a basic block without software pipelining, the schedule size is set to a size that is sufficiently large for the targeted machine, which is architecturally dependent. When list scheduling a program loop with software pipelining, the schedule size is set to different sizes for different attempts. The instruction tracking array 58 is used to track and link the scheduling of the squeezed and non-squeezed instructions separately. The instruction tracking array 58 comprises m rows, one for each schedule slot of the uncompacted schedule, and two (2) columns, one each for separately tracking and linking the scheduling of the squeezed and the non-squeezed instructions. Thus, the instruction tracking array 58 is always initialized with the same size.

Referring now to FIG. 5, a block diagram illustrating the improved list scheduling technique of the present invention for scheduling a basic block is shown. Initially, the improved scheduler sets the schedule size (ss), step 61. As described earlier, the schedule size is set to a size sufficiently large for the target machine, which is architecturally dependent. In one embodiment, ss is set to logical infinity. Upon setting the schedule size, the improved scheduler initializes the resource utilization and the instruction tracking arrays, step 62. As described earlier, the resource utilization array is initialized in accordance to the schedule size, whereas the instruction tracking array is initialized in accordance to the uncompacted size of the basic block. Upon initializing the arrays, the improved scheduler builds an instruction candidate list, step 63. Similar to the prior art list scheduling technique, the instruction candidate list may be built using a top down (predecessor free) approach or a bottom up (successor free) approach.

The improved scheduler then evaluates one or more priority functions to select one of the candidate instructions to schedule, step 64. The improved scheduler employs priority functions that distinguish squeezed instructions from non-squeezed instructions. In one embodiment, the improved scheduler selects one of the candidate instructions based on the relative chain lengths of the non-squeezed instruction chains originating from the candidate instructions. The candidate instruction with the longest chain length is selected. In other words, the squeezed instructions are not included in the chain length determinations. However, in this embodiment, the squeezed instructions are used for tie breaking. More specifically, when two candidate instructions have the same chain length, the candidate instruction with more squeezed instructions in its chain is selected over the candidate instruction with less squeezed instructions in its chain. Additionally, when no squeezed instructions are available for tie breaking, the tied candidate instruction has been ready to be scheduled for the longest time is selected over the other tied candidate instructions.

After selecting the candidate instruction, the improved scheduler schedules the selected instruction in one of the available schedule slot, without violating the resource and precedence constraints, step 65. Then, the improved scheduler updates the resource utilization and instruction tracking array accordingly, to denote the usage of a particular resource at a particular schedule slot, and to track and link the scheduled instruction to a schedule slot, step 66. As described earlier, the resource utilization array is updated only if the scheduled instruction is a squeezed instruction, and the appropriate column in the instruction tracking array is updated depending on whether the scheduled instruction is a squeezed or non-squeezed instruction. Upon updating the two arrays, the instruction candidate list is refreshed, step 67. If the refreshed candidate instruction list is non-empty, no branch of step 68, steps 64-67 are repeated. On the other hand, if the refreshed candidate instruction list is empty, yes branch of step 68, the process is terminated.

Referring now to FIGS. 6a-6b, two block diagrams illustrating the improved list scheduling technique of the present invention for scheduling a program loop with software pipelining additionally employed are shown. As illustrated in FIG. 6a, initially the improved scheduler sets the schedule size (ss) to the smallest schedule size possible (maximum compaction) without considering the squeezed instructions, step 71. In other words, if the program loop has five (5) squeezed instructions and seven (7) non-squeezed instructions, and six (6) of the seven (7) non-squeezed instructions can be issued in two-instruction pairs, the smallest schedule size without considering the squeezed instructions is four (4). Upon setting the schedule size, the improved scheduler attempts to schedule the program loop with a schedule of size ss, step 72. If the improved scheduler is successful, no branch of step 73, an optimal schedule is found for the program loop, step 74.

On the other hand, if the improved scheduler is unsuccessful, yes branch of step 73, the schedule size is incremented by one (1), step 75. If the incremented schedule size is still less than the uncompacted size of the program loop, yes branch of step 76, another attempt is made to schedule the program loop with a schedule of size ss, step 72. The process continues until either the improved scheduler is successful in scheduling the program loop with a schedule of size ss, no branch of step 73 or the incremented schedule size equals the uncompacted size of the basic block, no branch of step 76.

FIG. 6b illustrates the process step of attempting to schedule the program loop with a schedule of size ss, step 72, in further detail. The process steps are essentially the same process steps described for scheduling a basic block, except the improved scheduler may fail to find a schedule slot for the selected candidate instruction, steps 81-82, due to the modulo resource constraint. In that event, the attempt has failed, step 83.

Referring now to the remaining figures, an exemplary scheduling of an exemplary program loop under the present invention is illustrated. Although the exemplary scheduling will be illustrated with software pipelining additionally employed, for ease of explanation, an exemplary program loop that does not lend itself to overlapping initiations of iterations will be used. FIGS. 7a-7b illustrate the exemplary program loop in C and FORTRAN. FIGS. 8a-8b illustrate the exemplary instructions in the corresponding program loop to be scheduled, and the precedence constraints of these exemplary instructions. For the purpose of this illustration, it is assumed that the target machine supports the simultaneous issuance of two instructions at a time. However, only an Add and a Multiply instruction can be issued together (non-squeezed instructions). A Divide instruction cannot be issued with any other instruction (squeezed instruction). Additionally, the candidate instructions will be identified using the bottom up (successor free) approach. The relative chain lengths of the predecessor non-squeezed instruction chains of the candidate instructions are uses to select candidate instructions. The presence of squeezed instructions in a predecessor chain is considered only for tie breaking.

As described earlier, the improved scheduler first sets the schedule size to the smallest schedule size possible (maximum compaction) without considering the squeezed instructions. Since there are four Add instructions and two Multiply instructions, thus the smallest schedule size possible, ignoring the Divide instructions, is four. FIGS. 9a-9h illustrate the improved scheduler's attempt to schedule these exemplary instructions with a schedule of size 4. As illustrated in FIG. 9a, the improved scheduler builds a candidate instruction list 98a (using the bottom up approach). At this time, the candidate instruction list 98a comprises instr-4, a Multiply instruction, and instr-8, an Add instruction. Since instr-4, the Multiply instruction, originates a predecessor non-squeezed instruction chain with 4 non-squeezed instructions, which is longer than the 2 non-squeezed instructions predecessor non-squeezed instruction chain which originates from instr-8, the Add instruction, instr-4, the Multiply instruction, is selected over instr-8, the Add instruction, 100a. Since all resources are available, and no instructions have been scheduled at this time, the selected Multiply instruction (instr-4) is scheduled for the latest schedule slot, slot 0. Thus, the multiplication resource is marked used for slot 0, 56a, and instr-4, the Multiply instruction, is tracked in the non-squeezed list and linked to slot 0, 58a.

Next, as illustrated in FIG. 9b, the improved scheduler refreshes the candidate instruction list 98b. At this time, the candidate instruction list 98b comprises instr-3, a Multiply instruction, and instr-8, an Add instruction. Since instr-3, the Multiply instruction, originates a predecessor non-squeezed instruction chain with 3 non-squeezed instructions, which is longer than the 2 non-squeezed instructions predecessor non-squeezed instruction chain which originates from instr-8, the Add instruction, instr-3, the Multiply instruction, is selected over instr-8, the Add instruction, 100b. Since the multiplication resource is used in schedule slot 0, and instr-3 must be executed before instr-4, the selected Multiply instruction (instr-3) is scheduled for slot 1. Thus, the multiplication resource is marked used for slot 1, 56b, and instr-3, the Multiply instruction, is tracked in the non-squeezed list and linked to slot 1, 58b.

As illustrated in FIG. 9c, the improved scheduler refreshes the candidate instruction list again 98c. At this time, the candidate instruction list 98c comprises instr-2, an Add instruction, and instr-8, also an Add instruction. Since both instr-2 and instr-8 originate predecessor non-squeezed instruction chains with 2 non-squeezed instructions. The two Divide instructions in instr-8's predecessor chain are used for tie breaking. As a result, instr-8, the Add instruction, is selected over instr-2, the other Add instruction, 100c. Since the addition resource is available in schedule slot 0, and instr-8 does not have to be executed before any other instructions, the selected Add instruction (instr-8) is scheduled for slot 0. Thus, the addition resource is marked used for slot 0, 56c, and instr-8, the Add instruction, is tracked in the non-squeezed list and linked to slot 1 through instr-4, 58c. It will be appreciated that a newly scheduled instruction may be linked at the beginning or the end of the list associated with a schedule slot.

As illustrated in FIG. 9d, the improved scheduler refreshes the candidate instruction list again 98d. At this time, the candidate instruction list 98d comprises instr-2, an Add instruction, and instr-7, a Divide instruction. Since instr-2, the Add instruction, originates a predecessor non-squeezed instruction chain with 2 non-squeezed instructions, which is longer than the 1 non-squeezed instruction predecessor non-squeezed instruction chain which originates from instr-7, the Divide instruction, instr-2, the Add instruction, is selected over instr-7, the Divide instruction, 100d. Since instr-2 must be executed before instr-3, and the addition resource is available in slot 2, the selected Add instruction (instr-2) is scheduled for slot 2. Thus, the addition resource is marked used for slot 2, 56d, and instr-2, the Add instruction, is tracked in the non-squeezed list and linked to slot 2, 58d.

As illustrated in FIG. 9e, the improved scheduler refreshes the candidate instruction list again 98e. At this time, the candidate instruction list 98e comprises instr-1, an Add instruction, and instr-7, a Divide instruction. Since both instr-1 and instr-7 originate a one non-squeezed instruction predecessor non-squeezed instruction chain, the two Divide instructions in instr-7is predecessor chain are used for tie breaking. As a result, instr-7, the Divide instruction, is selected over instr-1, the Add instruction, 100e. Since instr-7 must be executed before instr-8, the selected Divide instruction (instr-7) is scheduled for slot 1. Thus, the resource utilization array is not updated, 56e, and instr-7, the Divide instruction, is tracked in the squeezed list and linked to slot 1, 58e. By implementation convention, squeezed instructions tracked in the squeezed list and linked to a schedule slot are scheduled after the unsqueezed instructions tracked in the unsqueezed list and linked to the same schedule slot.

As illustrated in FIG. 9f, the improved scheduler refreshes the candidate instruction list again 98f. At this time, the candidate instruction list 98f comprises instr-1, an Add instruction, and instr-6, a Divide instruction. Since both instr-1 and instr-6 originate a one non-squeezed instruction predecessor non-squeezed instruction chain, the Divide instruction in instr-6's predecessor chain are used for tie breaking. As a result, instr-6, the Divide instruction, is selected over instr-1, the Add instruction, 100f. Since instr-6 must be executed before instr-7, the selected Divide instruction (instr-6) is scheduled for slot 1. Thus, the resource utilization array is not updated, 56f, and instr-6, the Divide instruction, is tracked in the squeezed list and linked to slot 1 in front of instr-7, 58f.

As illustrated in FIG. 9g, the improved scheduler refreshes the candidate instruction list again 98g. At this time, the candidate instruction list 98g comprises instr-1, an Add instruction, and instr-5, also an Add instruction. Since both instr-1 and instr-5 originate a one non-squeezed instruction predecessor non-squeezed instruction chain, and there's no squeezed instructions to be used for tie breaking, instr-1, the Add instruction, which has been ready to be schedule for a longer time is selected over instr-5, the other Add instruction, 100g. Since instr-1 must be executed before instr-2, and the addition resource is available in slot 3, the selected Add instruction (instr-1) is scheduled for slot 3. Thus, the addition resource is marked used for slot 3, 56g, and instr-1, the Add instruction, is tracked in the non-squeezed list and linked to slot 3, 58g.

As illustrated in FIG. 9h, the improved scheduler refreshes the candidate instruction list again 98h. At this time, the candidate instruction list 98h comprises only instr-5, an Add instruction. Thus, instr-5, the Add instruction, is selected, 100h. Since instr-5 must be executed before instr-6, and the addition resource is available in slot 1, the selected Add instruction (instr-5) is scheduled for slot 1. Thus, the addition resource is marked used for slot 1, 56h, and instr-5, the Add instruction, is tracked in the non-squeezed list and linked to slot 1 through instr-3, 58h.

Since at this time all instructions have been scheduled, no new candidate instructions will be added to the candidate instruction list as the improved scheduler attempts to refresh the candidate instruction list again. Thus, the candidate instruction list becomes empty. Upon detecting that the candidate instruction list is empty, the improved scheduler terminates the attempt step. The improved scheduler was successful in scheduling the instructions in a schedule with size 4 (not counting squeezed instructions). This schedule is illustrated in FIG. 10a. In contrast, the longer schedule generated under the prior art list scheduling technique is illustrated in FIG. 10b.

While the present invention has been described in terms of presently preferred and alternate embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The method and apparatus of the present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting on the present invention.