Method and Apparatus for Differentially Decoding Signals

The present invention relates to a method and apparatus for decoding signals which have been differentially encoded. The invention is applicable to decoding signals at a receiver which have been digitally modulated.

Transmission systems which use absolute phase modulation to transmit data symbols to a receiver require a phase reference at the receiver in order to demodulate the transmitted modulated symbols. This is normally generated at the receiver from the received modulated signal using a non-linear operator. The phase reference extracted from the received signal will however have a phase ambiguity.

The phase ambiguity problem resulting from extracting the phase reference from the received modulated signal can be overcome by differentially encoding the data symbols as phase differences between successive information bits. For example in binary phase shift keying (BPSK), the binary information bit 1 may be transmitted by shifting the phase of the carrier by 180 degrees in the respective signaling interval relative to the phase of the previous signaling interval. To transmit a binary information bit 0, a zero phase shift occurs from one signaling interval to the next. This encoding takes place in an encoder which precedes the modulator.

Decoding of the differentially encoded BPSK signal is performed conventionally using a phase comparator that compares the phase of succeeding signal intervals of a carrier in order to extract the phase difference between each signaling interval and the next. No phase reference needs to be generated as the information is inferred from the phase differences between successive signaling intervals. A delay of one symbol is however needed at the receiver to allow the carrier phase in each signal interval to be compared with the delayed phase of the carrier in the previous signal interval. The channel used to transmit the differentially encoded signal must be quasi-stationary for the interval between two signal intervals to ensure that phase shifts induced by the channel are approximately the same from one signal to the next.

The use of a differentially coded modulation technique has brought with it a reduction in the bit error rate (BER) performance. This is because a single channel error will result in approximately two errors in decoding because the decoding depends on detecting relative phase differences.

An improvement in performance can be achieved by employing a transmission system with forward error correction (FEC). Errors induced by the transmission channel are corrected using redundancy in the data which is added at the transmitter.

The present invention relates to a method and apparatus in which a differentially coded signal having forward error correction added to the encoded data can be decoded with an improved bit error rate performance.

According to the present invention there is provided a method of decoding a differentially encoded input signal having forward error correction added to the encoded data, the method comprising the steps of, applying the input signal to a differential decoder to decode the data in each differentially encoded signal interval by reference to the date in a previous differentially encoded signal interval, applying the decoded signal to error correcting means to correct errors in the decoded data, and applying to the decoder the corrected decoded data for each signal interval to act as a reference for decoding the data in the succeeding signal interval.

Further according to the present invention, there is provided apparatus for decoding a differentially encoded input signal having forward error correction added to the encoded data the apparatus comprising, a differential decoder to receive the input signal and to decode the data in each differentially encoded signal interval thereof by reference to the data in a previous differentially encoded signal interval, error correcting means to correct errors in the decoded signal from the decoder, and means to supply to the decoder the corrected decoded data from each signal interval to act as a reference for decoding the data in the succeeding signal interval.

In the method and system according to the invention, the data in each signal interval from the decoder is subject to error correction before being used as a reference for decoding the data in the next signal interval. This means that the penalty of doubling the error rate normally associated with differential decoding is removed.

The invention will now be further described, by way of example, with reference to the accompanying drawing which is a block diagram of a signal receiver embodying the invention.

An input bitstream is supplied to a differential decoder 10. The input bitstream consists of an OFDM signal including a sequence of blocks of data. Each block includes a spectrum of carriers which are differentially phase encoded and the encoding includes added forward error correction.

The differential phase encoding of the input bitstream is decoded by the decoder 10 to produce a sequence of bits, which may represent hard or soft decision information, which are passed to a Viterbi decoder 11. The Viterbi decoder functions to correct the decoded bitstream from the decoder 10 in a manner well known. The corrected bitstream is passed to a convolutional encoder 12 to be re-encoded and then passes to an error detect and correct circuit 13. A delay means 14 receives the decoded output from the decoder 10, subjects the output from the decoder 10 to a delay and applies the delayed decoder output to the error detect and correct circuit 13 for comparison with the re-encoded bitstream from the encoder 12. The circuit 13 functions to detect and correct errors in the bitstream and supplies a corrected bitstream through a further delay means 15 to a selection device 16.

A block delay device 17 receives the input bitstream and delays the input by one block before application to the selection device 16. The selection device makes a selection between the delayed input from the delay means 15 and the delayed input from the block delay 17. The selection is based on an algorithm which determines whether an error burst at the output of the error correction subsystem including the decoder 11, the encoder 12 and the error detect and correction circuit 13 would lead to correct data in the input bitstream being changed. If such an error burst is detected, the selection device 16 selects the signal from the block delay 17 for application to the differential decoder 10. Alternatively, the signal from the delay means 15 is selected for application to the differential decoder 10. It will be apparent that the delay imposed by the delay means 15 is used to make each block of the input bitstream coincident with the preceding corrected block taking account of the processing time required by the elements 11, 12 and 13.

The differential decoder 10 decodes the data within each signal interval of the input bitstream by reference to the data supplied by way of the selection device 16. When the selection device selects corrected data from the delay means 15, each symbol which is in error in the input bitstream is corrected before it is used as a reference for decoding the succeeding symbol. By this means, the penalty of doubling the error rate which is normally associated with differential encoding is avoided.