Method for Manufacturing Semiconductor Device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an impurity region in the substrate of a semiconductor device.

In semiconductor fabrication technology, it is important to achieve active device characteristics as close to the ideal as possible while making dimensions small enough for VLSI applications. This requires reducing parasitic conduction paths and series resistances as well as maintaining threshold voltage control and minimizing the leakage current of the device. The more complex the layout of a semiconductor chip, the more difficult it is to deal with crossing wires, that is, conducting paths on the chip that overlap.

To minimize the wiring complexity on a chip, a so-called "buried contact" technique is usually employed in the fabrication process of a semiconductor device since it enables a more compact layout. A "buried contact" is essentially an ohmic connection between a doped semiconductor region (such as semiconductor substrate or impurity regions) and a highly conductive layer (such as polycrystalline silicon or metallization layers). In FET technology, "buried contacts" facilitate gate layout by providing means for electrical contact between the polysilicon and diffusion layers that do not require metal coverage as does the butting contact.

A conventional method of forming a buried contact in a FET process is shown in FIGS. 1a-1e (PRIOR ART). As shown in FIG. 1a, the starting silicon wafer is a lightly doped p-type substrate 1. The initial step is to define the field oxide layer 2 in order to expose those areas of silicon that will receive implantations or diffusions to form the required active devices. The field oxide layer 2 provides isolation between adjacent transistors. The isolation scheme could be enhanced by providing channel-stop implants into the isolation regions under the field oxide layer 2 (not shown in the figures for simplicity). A threshold-adjust implant could also be provided to set the desired threshold of the FET device (again not shown in the figures, for simplicity). A thin oxide film 3 is then formed. A buried-contact window (contact hole 5) is patterned by selectively etching the oxide film 3. This step is included in many design processes, for example, in the case of an NMOS inverter having a load device. The use of a load device makes it necessary to provide for a connection between the gate and source of the load transistor. In this case, the thin oxide film 3 actually represents the gate oxide.

After the formation of contact hole 5, a polycrystalline silicon (Poly Si) layer 4 is deposited on the entire surface of the substrate 1 (FIG. 1b) and doped n-type with either an implant or vapor doping using POCl.sub.3 as a diffusion source, for example. Subsequently, the n.sup.+ -polysilicon layer 4 acts as a phosphorus doping source for the silicon exposed in the opened area of the oxide film (contact hole 5) to form an n-type impurity region 6 in the substrate 1, as shown in FIG. 1c. The Poly-Si layer 4 is then patterned by any conventional etching method either to form a wiring layer or to define the gates of the active devices as in the case of an inverter structure having driver and load devices (shown in FIG. 1d). Note that the Poly-Si layer 4 contacts the silicon at contact hole 5. The phosphorus used to dope the polysilicon can diffuse directly into the silicon below it, so that an ohmic contact exists between the polysilicon and the underlying n.sup.+ -region 6, thus, establishing a connection between the source and gate of the load device. The connection is made this way to avoid the additional space requirement that would be necessary if metal were used to strap the gate and source of the load together in the case of the above-mentioned NMOS inverter. After the patterning of the polysilicon, an n.sup.+ diffusion (or implant) is performed. This step requires no mask, since the field oxide and polysilicon define the diffusion regions 7, 8 and 9. In this particular case, the diffusion's purpose is not only to define the source and drain of the transistors, but also to provide a conducting path that interconnects the two transistors, as shown in FIG. 1e.

In practice, diffusion in microcircuits is always carried out through windows cut in the mask that is placed on the slice. The dopant source provides impurities which diffuse at right angles to the semiconductor surface as well as parallel to it (i.e., laterally). In the method described above, phosphorus is deeply diffused in both the vertical and horizontal directions. FIG. 2 shows the distribution of impurity concentration when the diffusion of phosphorus is performed at 900.degree. C. for 40 minutes. The depth of the impurity region is about 0.6 .mu.m ›X.sub.j (vertical) !. The diffusion length in the lateral direction ›x.sub.i (horizontal) ! from the edge of the contact hole is about 0.45 .mu.m ›x.sub.i (horizontal) !=0.75.times.X.sub.j (vertical). In other words, the lateral penetration is about 75% of the penetration in the vertical direction for concentrations that are two or more orders of magnitude below the surface concentration. Lateral diffusion effects may result in a situation where the electric field associated with one impurity region will punch through to the adjacent impurity region due to the fact that the depletion regions surrounding the two adjacent n-type impurity regions are nearly touching under the field oxide layer, particularly at high applied voltages. Thus, lateral penetration facilitates the overlapping of adjacent depletion regions which, in turn, could short out the corresponding devices resulting in a considerable flow of current. This places a limitation on the allowable degree of device scaling and renders miniaturization of elements on a chip quite difficult.

Another disadvantage of the buried-contact scheme (in the particular example illustrated in the PRIOR ART figures) is that the depletion-mode transistor which is acting as the load of the NMOS inverter is not a self-aligned gate MOS field-effect transistor (MOSFET). The buried-contact mask defines the source diffusion of the load transistor, and the polysilicon mask defines the drain diffusion. Therefore, the channel length is subject to mask misalignment errors. In general, buried contacts are subject to a rather complex set of design rules, require an extra mask level, and sometimes reduce yield and reliability due to the above-mentioned problems.

It is an object of the present invention to provide an improved method of manufacturing a semiconductor device having shallow impurity regions.

It is another object of the present invention to provide an improved method of manufacturing a semiconductor device having shallow impurity regions in which lateral diffusion effects are reduced to manageable proportions.

It is, yet, another object of the present invention to provide an improved method of manufacturing a field-effect transistor having shallow impurity regions that minimize misalignment errors and having buried contacts of high reliability without the deleterious effects of the punch-through phenomena.

According to the invention, a method of manufacturing a semiconductor device comprises the steps of: introducing arsenic into a predetermined portion of a silicon body; and introducing phosphorus into said predetermined portion after said step of introducing arsenic, thereby forming in the silicon body an N-type impurity region including arsenic and phosphorous. The thus formed impurity region is shallow and has minimal lateral diffusion effects.

FIG. 1a-1e (Prior Art) illustrate a conventional method of manufacturing a semiconductor device having impurity regions and buried contacts.

FIG. 2 is a graph showing the distribution of impurity concentration according to the conventional method.

FIGS. 3a-3c illustrate a process in accordance with one embodiment of the present invention.

FIG. 4 is a graph showing the distribution of impurity concentration according to the embodiment of the present invention shown in FIGS. 3a-3c.

FIGS. 5a-5d illustrate a process in accordance with a second embodiment of the present invention.

FIGS. 3a-3c are sectional views depicting a process in accordance with a first embodiment of the present invention to form a buried contact. With reference to FIG. 3a, the initial step is isolation patterning, wherein a field oxide layer 12 having a thickness of 3000-5000 .ANG. is formed by selectively oxidizing the surface of a P-type monocrystalline silicon substrate 11 to expose those areas of silicon that will receive implantations or diffusions. An N-type silicon substrate with a P-type well may be employed instead of the P-type silicon substrate 11. An insulating film 13 having a thickness of 100-150 .ANG. is formed by oxidation on the exposed surface of the Si substrate which is surrounded by the field oxide layer 12.

Referring to FIG. 3b, a first Poly-Si layer 17 having a thickness of about 1000 .ANG. is formed by blanket deposition on the entire surface using low pressure chemical vapor deposition (LPCVD) for the protection of the oxide film 13. At this time, as a pre-treatment of Poly-Si deposition, a chemical treatment which does not contain HF may be carried out. Then, a photoresist 18 is formed having a window patterned in accordance with the buried contact portion. Using the photoresist 18 as a mask, first Poly-Si layer 17 is selectively removed by reactive ion etching (RIE) and the oxide film 13 is also selectively removed by wet etching with NH.sub.4 F to expose the substrate 11. Thus, a contact window 15 is formed in the buried contact portion. Arsenic is introduced through the contact hole 15 into the substrate at the buried contact portion by ion implantation at an acceleration energy of 40 KeV and at a dose of 1.times.10.sup.15 cm.sup.-2 to form an impurity region 16. Alternatively, the oxide film 13 grown on the surface of the buried contact portion may be removed after the ion implantation of arsenic.

Referring to FIG. 3c, after the removal of photoresist 18, a second Poly Si layer 20 having a thickness of 3000 .ANG. is formed by blanket deposition on the entire surface using LPCVD in an atmosphere of oxygen with the concentration of ppm order. Phosphorus is diffused for 30-40 minutes at 900.degree. C. through second Poly-Si layer 20 into the substrate at the buried contact portion using POCL.sub.3 as a diffusion source. Thus, an impurity region 19 into which both arsenic and phosphorus have been introduced is formed. Then, first and second Poly-Si layers are patterned by a conventional etching process to form either a wiring layer or a gate layer. In this embodiment, the distribution of phosphorus in the impurity region 19 is more shallow than that of arsenic as shown in FIG. 4. Phosphorus diffuses to a level that is more shallow when compared with the prior art process in which arsenic is not implanted into the substrate. This is a phenomenon discovered by the applicant. In this way, a shallow impurity region is obtained and excellent field punch-through characteristics and high packing densities are achieved without the formation of parasitic conduction paths between isolated devices on a chip.

Alternatively, ion implantation of arsenic in the above-mentioned embodiment may be performed after the deposition of second Poly-Si layer 20. Such ion implantation destroys the native oxide formed between second Poly-Si layer 20 and the substrate 11. In this case, a second Poly-Si layer 20 having a thickness of about 500 .ANG. is desirable. Moreover, the formation of the first Poly-Si layer 17 may be omitted. The subsequent steps are performed in accordance with the desired layout, for example, the inverter circuit layout shown in the prior art.

FIGS. 5a-5d are sectional views depicting a process in accordance with a second embodiment of the present invention to form source and drain impurity regions of a MOS transistor. With reference to FIG. 5a, the initial step is isolation patterning, wherein a field oxide layer 22 having a thickness of 3000-5000 .ANG. is formed by selectively oxidizing the surface of a P-type silicon substrate 21 to expose those areas of silicon that will receive implantations or diffusions. An N-type silicon substrate with a P-type well may be employed instead of the P-type silicon substrate 21. A gate oxide film 23 having a thickness of 100-150 .ANG. is formed by oxidation on the exposed surface of the Si-substrate which is surrounded by the field oxide layer 22. A threshold-adjust implant in which boron is introduced into the substrate in the device active area surrounded by the field oxide layer 22 is performed. Then, a Poly-Si gate electrode 24 is formed on the gate oxide film 23.

Referring to FIG. 5b, arsenic is introduced into the substrate by ion implantation at an acceleration energy of 40-60 KeV and at a dose of 1.times.10.sup.15 -5.times.10.sup.15 cm.sup.-2 to form source and drain impurity regions 25a and 25b. Then, as shown in FIG. 5c, phosphorus is introduced into source and drain formation regions by ion implantation at an acceleration energy of 20-30 KeV and at a dose of 1.times.10.sup.15 -5.times.10.sup.15 cm.sup.-2 to form source and drain impurity regions 26a and 26b. The acceleration energies of arsenic and phosphorus are chosen to make the peak depth of phosphorus concentration more shallow than that of arsenic concentration.

Arsenic and phosphorus impurities are activated by heat treatment to form a source region 27a and a drain region 27b, as shown in FIG. 5d. Alternatively, arsenic and phosphorus may be introduced into the substrate 21 after the selective removal of the gate oxide film 23 from the surface of the source and drain formation regions. Moreover, phosphorus may be introduced using a diffusion source.

In this embodiment, phosphorus does not deeply diffuse into the substrate during heat treatment, so that shallow source and drain regions are obtained. The formed impurity regions have high junction breakdown voltages due to the smooth profile at the edge portion of the phosphorus implant. Moreover, lateral diffusion is also minimized so that self-alignment of the source and drain regions to the gate electrode layer is achieved with minimal overlapping. Therefore, this method is well suited to the manufacturing of semiconductor devices with high packing densities and minimum parasitic conductive paths.