Method for Forming a Semiconductor Device With a Graded Lightly-Doped Drain Structure

1. Field of the Invention

The present invention relates to a semiconductor transistor, and particularly, to a method for forming a metal-oxide-semiconductor field effect transistor (MOSFET) with a graded lightly-doped drain (LDD) structure.

2. Description of the Prior Art

As metal-oxide-semiconductor (MOS) devices are scaled down, short channel effect and hot carrier reliability problems become the major constrains. Most attempts to solve these problems have been discussed in references such as that disclosed by Ryuichi Izawa et al., "The Impact of N- Drain Length and Gate-Drain/Source Overlap on Submicrometer LDD Devices for VLSI," IEEE Electronic Device Letters, VOL. EDL-8, NO. 10, October 1987, pages 480-482, and that disclosed by Ching-Yeu Wei et al., "Buried and Graded/Buried LDD structures for Improved Hot-Electron Reliability," IEEE Electronic Device Letters, VOL. EDL-7, NO. 6, June 1986, pages 380-382 which are hereby incorporated by reference. In these references, their attempts have focused on reducing the lateral electric field strength by making the p-channel to n+ drain transition less abrupt, including the phosphorous source-drain junctions, the arsenic-phosphorous source-drain junction, and the lightly-doped drain (LDD) structure in conjunction with an oxide sidewall spacer.

However, the performance of the MOS devices is degraded in the LDD structure due to an increase in its series resistance, and due to a reduction of the carrier mobility in the channel and out diffusion regions, as discussed by Y. Pan et al., "Hot-Carrier Induced Electron Mobility and Series Resistance Degration in LDD NMOSFET's," IEEE Electronic Device Letters, VOL. 15, NO. 12, December 1994, pages 499-501 which is hereby incorporated by reference.

Another problem encountered in the MOS devices with LDD sidewall spacers is drain-to-substrate leakage caused by the crystalline defects at the sidewall edge. To solve this problem, a process is disclosed by Shigeo Onishi et al., "A Mechanism of the Sidewall Process Induced Junction Leakage Current of LDD Structure," J. Electrochem. Soc., VOL. 138, NO. 5, May 1991, pages 1439-1443 which is hereby incorporated by reference. In this reference, a smoothly shaped sidewall is formed by an anisotropic and a subsequent isotropic etch, effectively suppressing the defects.

In accordance with the present invention, a method is provided for forming a MOSFET with a graded lightly-doped drain (LDD) structure. In one embodiment, a semiconductor substrate is provided which has a gate region formed thereon. Next, a silicon nitride layer is formed on the substrate and the gate region, and ions are then implanted into the substrate. A spin-on-glass film is coated over the silicon nitride layer, followed by reflowing the spin-on-glass film, and etching back the spin-on-glass film to form a first spacer on sidewalls of the gate region, wherein the first spacer has a concave surface inwards on a surface of the first spacer. Ions are further implanted into the substrate through the silicon nitride layer using the gate region and the first spacer as a mask, thereby forming a graded doping profile in the substrate. After removing the first spacer and the silicon nitride layer, a dielectric layer is deposited over the gate region and the substrate, followed by etching back the dielectric layer, thereby forming a second spacer on sidewalls of the gate region. Finally, the substrate is annealed to smooth the graded doping profile in the substrate.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIGS. 1-6 show cross-sectional views illustrative of various stages in the fabrication of a MOSFET with a graded lightly-doped drain (LDD) structure in accordance with the present invention.

FIG. 1 shows a cross-sectional view illustrative of a semiconductor substrate 10 and a thin gate oxide layer 12 formed thereon. On the gate oxide layer 12 is a polysilicon gate region, which includes a polysilicon region 14 and a silicon oxide region 16 (such as TetraEthOxySilane, TEOS) formed on the polysilicon region 14. Next, a dielectric layer 18, such as a silicon nitride layer, used as a pad layer, is then deposited over the gate region and the substrate 10. In this embodiment, the silicon nitride layer 18 is deposited using a conventional low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) to a thickness of about 50-300 angstroms.

In FIG. 2, a low dose (about 5.times.10.sup.12 -5.times.10.sup.14 atoms/cm.sup.2) and low energy (about 5-100 keV) lightly-doped drain (LDD) implant is performed to the substrate 10 via the silicon nitride layer 18, resulting in the source/drain region 20 as shown in FIG. 2.

Referring to FIG. 3, a sloping spacer 22 is formed on the sidewall of the gate region (14 and 16). This spacer 22 has a concave surface inwards in the middle on the surface of the spacer 22. In this embodiment, this spacer 22 is formed by firstly coating a thick spin-on-glass (SOG) film, followed by a standard reflowing process and then etching back the spin-on-glass (SOG) film.

Next, a second implant is performed through the slopping spacer 22 and the silicon nitride layer 18, resulting in a graded doping profile in the substrate 10 as shown in FIG. 4. It is noted that this graded profile substantially reduces junction leakage caused by the crystalline defects at the sidewall edge.

Subsequently, the SOG spacer 22 is removed, for example, by HF solution, wherein the silicon nitride layer 18 acts as a mask to the substrate 10, the gate oxide layer 12 and the gate region (14 and 16). Further, the silicon nitride layer 18 is then removed, for example, by H.sub.3 PO.sub.4 solution.

Another dielectric spacer 24 is further formed on the sidewalls of the gate region (14 and 16) as shown in FIG. 5. In this embodiment, this dielectric spacer 24 is formed by firstly depositing a dielectric layer 24, such as a silicon oxide layer or a silicon nitride layer, on the gate region (14 and 160) and the gate oxide layer 12, followed by etching back this dielectric layer 24.

To complete the present invention, the substrate 10 is subjected under a high temperature (about 700.degree.-1150.degree. C.) thermal anneal to form shallow source/drain 20 junction, which has a smoothly gradual doping profile. According to the present invention, conventional problems, such as series resistance, hot channel effect, and junction leakage, could be substantially improved.

Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from the spirit which is intended to be limited solely by the appended claims.