Voltage Level Shifter and Method

The invention relates to circuits, such as emitter followers, which are useful in precisely shifting a voltage level, and more particularly to a voltage level shift circuit for use in an instrumentation amplifier that is operable from a single power supply, and even more particularly to improvements which produce a constant voltage level shift in a PNP emitter follower transistor, especially a lateral PNP emitter follower transistor.

FIG. 1 shows a PNP emitter follower input circuit which is believed to be the closest prior art. This circuit is used in an instrumentation amplifier such as the AMP04 instrumentation amplifier marketed by Analog Devices, Inc. In FIG. 1, level shift circuit 1 includes a lateral PNP transistor 2 having its collector connected to ground, its base connected to receive an input signal V.sub.IN, and its emitter connected to an output conductor 8 and also to one terminal of a constant current source 3. (Such a transistor is referred to herein as an "emitter follower transistor".) The other terminal of constant current source 3 is connected to +V.sub.CC.

A problem with the circuit shown in FIG. 1 is that the base-emitter voltage of lateral PNP transistor 2 is highly dependent on the collector-emitter voltage thereof, which is equal to V.sub.OUT. Consequently, the base-emitter voltage of transistor 2, and hence the voltage level shift from V.sub.IN to V.sub.OUT, can range from approximately 30 millivolts within the range of V.sub.IN. This is unacceptable for a high precision circuit such as an instrumentation amplifier. The subsequent description of FIG. 3 indicates a shortcoming of a prior art instrumentation amplifier, wherein the input voltage can not be at or close to ground if only a single power supply is used.

It would be desirable to have a voltage level shift circuit that produces a shift which is independent of the value of the input voltage. It also would be desirable to have a way of stabilizing the collector-emitter voltage of a lateral PNP transistor functioning as an emitter follower to produce a constant voltage level shift. Similarly, it would be desirable to have a way of stabilizing the source-drain voltage of a field effect transistor functioning as a source follower to produce a constant voltage level shift.

It also would be desirable to have a low cost high precision integrated circuit instrumentation amplifier that permits both inputs to be at or close to ground and yet is operable from only a single power supply.

Accordingly, it is an object of the invention to provide a voltage shift circuit which produces a constant voltage shift, independently of the input voltage.

It is another object of the invention to provide a technique for stabilizing the collector-emitter voltage of lateral PNP transistor used as an emitter follower or the drain-source voltage of a field effect transistor used as a source follower.

It is another object of the invention to provide a low cost, precision integrated circuit instrumentation amplifier that allows both inputs to be at or near a ground voltage yet is operable from only a single power supply.

Briefly described, and in accordance with one embodiment thereof, the invention provides a precision voltage level shift circuit which includes an emitter follower input circuit including a first transistor having a base receiving an input voltage, an emitter coupled to an output terminal and a first current source. A load element is coupled between a collector of the input transistor and a first supply voltage conductor. A second transistor has a base coupled to the collector of the first transistor and an emitter coupled to a second current source. A differential amplifier has a first input coupled to the output terminal, a second input coupled to the emitter of the second transistor, and an output coupled to the load element. In one embodiment the first transistor is a lateral PNP transistor having the characteristic that its base-emitter voltage is strongly dependent on its collector-emitter voltage. The second transistor is a lateral PNP transistor, with its collector coupled to its base. Alternatively, the collector of the second transistor is coupled to the first supply voltage conductor, in which case the second transistor can be a substrate PNP transistor. (Those skilled in the art know that a "substrate PNP" transistor is one that includes P+ silicon wafer substrate material as its collector region, an N-type epitaxial layer on the P-type substrate as its base region, and a P-type region diffused or implanted in the N-type epitaxial layer as its emitter region.) In one preferred embodiment the load element is a P-channel JFET coupled between the collector of the first transistor and the first supply voltage conductor, with the output of the differential amplifier being coupled to the gate electrode of the P-channel JFET. The differential amplifier operates to maintain the voltage drop across the load element at a level such that the emitter of the second transistor is equal to the voltage of the emitter of the first transistor to thereby maintain the collector-emitter voltage of the first transistor at the nearly constant value of the base-emitter voltage of the second transistor. In one embodiment of the invention two of the voltage level shift circuits are used as input stages coupled between first and second input voltages of a single-supply instrumentation amplifier and non-inverting inputs of first and second operational amplifiers thereof, to allow the first and second input voltages to be at ground. In one embodiment of the invention the transistors are MOS field effect transistors (MOSFETs).

FIG. 1 is a schematic diagram of the closest prior art.

FIG. 2 is a schematic diagram of a preferred embodiment of the invention.

FIG. 3 is a schematic diagram illustrating use of the circuit of FIG. 2 in an instrumentation amplifier.

FIG. 4 is a schematic diagram of a modification to the embodiment of FIG. 2.

FIG. 5 is a schematic diagram of an alternative embodiment of the invention.

FIG. 6 is a schematic diagram of another embodiment of the invention.

Referring to FIG. 2, voltage shift circuit 1A includes a lateral PNP emitter follower transistor 2, the base-emitter voltage V.sub.BE(2) of lateral PNP transistor 2 is known to be a strong direct function of the collector-emitter voltage V.sub.CE(2) thereof. The input voltage V.sub.IN is applied to the base of PNP transistor 2. The emitter of lateral PNP transistor 2 is connected by output conductor 8 to one terminal of a constant current source 3, the other terminal of which is connected to +V.sub.CC. Preferably, a constant current I.sub.1 is supplied by current source 3. The output voltage V.sub.OUT is produced on conductor 8 and is equal to one V.sub.BE(2) voltage above V.sub.IN. The collector of lateral (or vertical) PNP transistor 2 is connected to the source of P-channel junction field effect transistor 4, the drain of which is connected to ground.

In accordance with the present invention, the collector of lateral PNP transistor 2 also is connected to the base and collector of a second lateral PNP transistor 5, which in FIG. 2 is connected as a diode-connected transistor. The emitter of diode-connected lateral PNP transistor 5 is connected by conductor 7 to the inverting input of a differential amplifier 9 to one terminal of a constant current source 6. Preferably, a constant current I.sub.2 is supplied by current source 6. The other terminal of current source 6 is connected to +V.sub.CC. The non-inverting input of differential amplifier 9 is connected to output conductor 8. The output of differential amplifier 9 is connected to the gate electrode of P-channel JFET 4.

The circuit shown in FIG. 2 maintains the collector-emitter voltage V.sub.CE2 of PNP input transistor 2 at a constant voltage as follows. Differential amplifier 9 maintains the voltage on conductors 7 and 8 at the same value by producing whatever feedback signal is needed on conductor 10 to vary the channel resistance of JFET 4 so that its source-drain voltage plus the base-emitter voltage V.sub.BE(5) of transistor 5 results in the voltage on conductor 7 being exactly equal to the voltage on conductor 8. This causes the collector-emitter voltage V.sub.CE(2) of lateral PNP transistor 2 to be equal to the base-emitter voltage V.sub.BE(5) of PNP transistor 5. Since the constant current I.sub.2 supplied by current source 6 flows through PNP transistor 5, its base-emitter voltage V.sub.BE(2) is very constant. With the voltages on conductors 7 and 8 being maintained equal by the action of differential amplifier 9, the collector-emitter voltage V.sub.CE(2) of transistor 2 also is essentially constant, so the voltage shift from V.sub.IN to V.sub.OUT therefore is essentially constant, independent of the magnitude of V.sub.IN.

Note that it is desirable that the base-emitter voltage V.sub.BE(5) of transistor 5 be significantly less (e.g., 50 to 100 millivolts less) than the V.sub.BE(2) base-emitter voltage of lateral PNP transistor 2, and that this voltage difference be greater than the source-drain voltage of P-channel JFET 4. If this condition is met, then differential amplifier 9 will maintain the collector-emitter voltage V.sub.CE(2) equal to a constant value equal to V.sub.BE(5) when V.sub.IN is anywhere in the range from zero volts to nearly plus V.sub.CC. Note also that V.sub.BE(5) can be made smaller in value than V.sub.BE(2) by increasing the ratio of I.sub.1 to I.sub.2 and/or decreasing the ratio of the emitter area of lateral PNP transistor 2 to the emitter area of PNP transistor 5.

FIG. 3 shows how the voltage shift circuit 1A of FIG. 2 is incorporated into a well known basic instrumentation amplifier. (The voltage shift circuits of subsequently described FIGS. 4-6 also can be used.) Instrumentation amplifier 20 includes a first operational amplifier 21 connected between a +5 volt supply voltage conductor 18 and ground conductor 19. A fixed reference voltage V.sub.REF is coupled via a resistor 22 to the inverting input of operational amplifier 21. The non-inverting input of operational amplifier 21 is coupled by a first voltage level shift circuit 1A-1 to receive a first input signal V.sub.IN1. The output of operational amplifier 21 is connected by a resistor 23 to the inverting input thereof. The output of operational amplifier 21 also is connected by a resistor 24 to the inverting input of a second operational amplifier 26, which also is biased between +5 volts and ground. The non-inverting input of operational amplifier 26 is connected to the output of a second voltage shift circuit 1A-2. A second input voltage V.sub.IN2 is applied to the input of voltage shift circuit 1A-2. The inverting input of operational amplifier 26 is coupled by resistor 25 to the inverting input of operational amplifier 21. The inverting input of operational amplifier 26 is also coupled by resistor 27 to the output of operational amplifier 26, on which the output voltage V.sub.OUT is produced. Resistors 22 and 27 can have a resistance R1 of 100 kilohms, and resistor 23 can have a resistance R2 of 25 kilohms.

The instrumentation amplifier of FIG. 3 is identical to the prior art except for voltage shift circuits 1A-1 and 1A-2. In the prior art, V.sub.IN1 and V.sub.IN2 are applied directly to the non-inverting inputs of operational amplifier 1A-1 and 1A-2, respectively. If V.sub.IN1 is at zero volts in the prior art instrumentation amplifier, then the output of operational amplifier 2-1 would necessarily be below ground in order to provide the feedback necessary to keep the inverting input thereof at the same zero voltage. This, of course, is not permissible in an integrated circuit implementation of the instrumentation amplifier in which only a single power supply providing ground on conductor 19 and +5 volts on conductor 18 is utilized. Consequently, a shortcoming of the closest prior art instrumentation amplifier is that it becomes inoperative if the input voltage V.sub.IN1 is brought close to ground.

However, when the voltage level shift circuits 1A-1 and 1A-2 of the present invention are coupled between V.sub.IN1 and V.sub.IN2 and the non-inverting inputs of operational amplifiers 21 and 26, respectively, then V.sub.IN1 and V.sub.IN2 can be at ground, yet the operational amplifiers 21 and 26 will continue to operate properly. For example, with the above values of R1 and R2, and with V.sub.IN1 and V.sub.IN2 both equal to zero volts, the voltages applied to the inverting inputs of both operational amplifiers 21 and 26 will be (for example) +0.6 volts. The output of operational amplifier 21 will be 0.4 volts, and it will operate properly as a feedback amplifier. The constant V.sub.BE voltage drop for the input transistor 2 results in the precision necessary for an instrumentation amplifier. V.sub.OUT will be equal to the value of V.sub.REF.

Thus, a low cost integrated circuit precision instrumentation amplifier operable from a single power supply is obtained, wherein both input voltages V.sub.IN1 and V.sub.IN2 can be at ground without disrupting circuit operation.

Referring now to FIG. 4, voltage shift circuit 1B is identical to the circuit 1A shown in FIG. 2, except that the collector of PNP transistor 5 is no longer connected to its base, and instead is connected to ground conductor 15. Transistor 5 is be formed as a PNP substrate transistor in a typical bipolar integrated circuit manufacturing process. This construction is efficient for reducing the ratio of the emitter area of lateral PNP transistor 2 to the emitter area of PNP transistor 5 to achieve the desired 50 to 100 millivolt difference between V.sub.BE(2) and V.sub.BE(5) mentioned above.

In FIG. 5, voltage shift circuit 1C is similar to the circuits 1A and 1B described with reference to FIGS. 2 and 4, except that P-channel JFET 4 has been replaced with an NPN transistor 4A. The dotted lines 17A and 17B between the collector of transistor 5 and its base or conductor 15 are alternative connections. To obtain the desired circuit operation for V.sub.IN equal to or very close to ground, it would be necessary for the difference between V.sub.BE(2) and V.sub.BE(5) to be equal to or exceed the V.sub.CE(SAT) of PNP transistor 4A.

Referring to FIG. 6, the above principles can be easily implemented using a CMOS process, wherein P-channel MOSFETs 2A and 5A replace PNP transistors 2 and 5, respectively, in FIG. 2, and an N-channel MOSFET 4B replaces NPN transistor 4A of FIG. 5. The optional connection of the drain of P-channel MOSFET 5A to either its base or ground conductor 15 is shown by dotted lines 17A and 17B.

While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make the various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. It is intended that all combinations of elements and steps which perform substantially the same function in substantially the same way to achieve the same result are within the scope of the invention.