US 5,805,608 AGrant
Clock Generation for Testing of Integrated Circuits
Issue Date:1998-09-08
•14 Claims
•10 Drawing Sheets
Abstract
In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK.
Metadata
Assignee
- Samsung Electronics Co., Ltd.
Inventors
- Sanghyeon Baeg
- Edward Yu
Application Information
Application Number:US 7339089
Filing Date:1996-10-18
Priority Date:1996-10-18
Art Unit:275
Classifications
IPC:
G01R 3128
Field of Search:
37136439532732422.3;22.5;22.6;22.31;22.32;22.36;27.4;27.7490;528183.06;183.19;183.1119;292;296765
Patent Drawings (10 sheets)
Description
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
Background of the Invention
The present invention relates to integrated circuits, and more particularly to generating clocks for integrated circuit normal and testing operations.
Some integrated circuits include testing circuitry to facilitate circuit testing during debugging and manufacturing. One example of such circuitry is the JTAG boundary scan standard described in C. M. Maunder and R. E. Tulloss, "The Test Access Port and Boundary-Scan Architecture" (IEEE Computer Society Press, 1990). The testing circuitry includes latches to hold test data. Test data are provided to the circuit input pins and possibly scanned into the latches. The integrated circuit, or a portion thereof, is clocked to simulate normal operation. Output test data are observed on the output pins. Output test data are possibly scanned out of the latches which could have captured data when the normal operation was simulated. Clock signals are generated to scan data in and out and to simulate normal operation. It is desirable to provide a simple clock generation circuitry that can generate suitable clocks for the integrated circuit testing.
Summary
The present invention provides clock generation methods and circuitry for an integrated circuit. Clock generation circuitry is suitable to generate clocks both for normal operation and for testing. The clocks generated for testing include the JTAG boundary scan clock and scan clocks for internal shift register chains used to test internal (non-boundary) function blocks. The clocks generated for testing include also clocks suitable to simulate normal operation.
To simplify generation of clocks for internal scan chains, the clock generation circuitry allows generation of internal scan clocks from the standard JTAG clock input pin TCK. Scan clock generation from pin TCK is convenient for chip debugging. Alternatively, the internal scan clocks can be generated from a separate test clock pin or pins. This facilitates providing an interface between the integrated circuit and existing testing equipment used in integrated circuit manufacturing environments.
The clocks to simulate normal operation can be generated from the TCK pin. The clocks generated from the TCK pin are well controlled because the TCK pin is well controlled.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.
Brief Description of the Drawings
FIG. 1 is a block diagram of an integrated circuit having testing circuitry according to the present invention.
FIG. 2A is a circuit diagram of a clock generator used in FIG. 1.
FIG. 2B is a circuit diagram illustrating a clock/data multiplexer of the circuit of FIG. 1.
FIG. 2C is a block diagram of a portion of the testing circuitry of FIG. 1.
FIG. 2D is a block diagram of a portion of the circuit of FIG. 2C.
FIGS. 2E and 2F are circuit diagrams of portions of the circuit of FIG. 2D.
FIG. 3 illustrates modes that can be entered via JTAG instructions in the circuit of FIG. 1.
FIG. 4 is a block diagram of testing circuitry according to the present invention.
FIG. 5 is a block diagram of hardware test environment for the circuit of FIG. 1.
FIGS. 6 and 7 illustrate test schemes according to the present invention.
Description of Preferred Embodiments
FIG. 1 is a block diagram of an integrated circuit (IC) 110. IC 110 includes testing circuitry to facilitate the integrated circuit testing. In some embodiments, circuit 110 is a Multimedia Signal Processor (MSP7.TM.) developed at Samsung Semiconductor, Inc. of San Jose, Calif. That processor is described in U.S. patent application Ser. No. 08/699,303 filed Aug. 19, 1996 by C. Reader et al. and entitled "Methods and Apparatus for Processing Video Data". That patent application is incorporated herein by reference. The MSP testing circuitry is described in detail in Appendices A-C herein. In particular, Appendix E includes Verilog code for the testing circuitry.
The testing circuitry includes test control circuit 120 (FIG. 1). Circuit 120 can function as a control circuit for boundary scan testing in accordance with the IEEE Standard 1149.1 (sometimes referred to as JTAG Version 2.0, or just the JTAG standard). That standard is defined in "IEEE Standard Test Access Port and Boundary-Scan Architecture" (IEEE Inc., Oct. 21, 1993) incorporated herein by reference. See also C. M. Maunder, R. E. Tulloss, "The Test Access Port and Boundary-Scan Architecture" (IEEE Computer Society Press, 1990) incorporated herein by reference.
In addition to boundary scan testing, test control circuit 120 is suitable for internal testing as defined below.
IC 110 includes 5 pins defined by the JTAG standard that are connected to circuit 120. Those pins are TCK (test clock input), TMS (test mode select input), TDI (test data input), TDO (test data output), and TRST.sub.-- N (test reset input, active low). The clock input on pin TCK is used not only during the JTAG boundary scan testing, but also for internal testing. In particular, the pin TCK provides scan clock signals for scanning data in and out of internal scan chains 126.1 through 126.17. Each chain 126.i includes a shift register built of LSSD (level sensitive scan design) latches. LSSD latches are described, for example, in M. Abramonici et al., "Digital Systems Testing and Testable Design" (1990) hereby incorporated herein by reference. Some embodiments of IC 110 include more than 17 scan chains or fewer than 17 scan chains. For one MSP embodiment, the 17 scan chains, and the respective MSP function blocks incorporating these chains, are shown in Appendix A, Table 2 as chains 1-17. (Chain 18 is the MSP boundary scan chain. Chain 19 is the boundary chain of the ARM7 processor embedded in the MSP.) Each internal chain 126 in Table 2 is a JTAG test data register which can be selected by a respective JTAG private instruction listed in Appendix A, Table 5.
Each internal chain 126.x receives non-overlapping scan clocks sca.sub.-- x, scb.sub.-- x for scanning test data. In a "single internal scan" operation, only one of chains 126 is scanned. The respective clocks sca, scb are derived from the TCK clock as described below. Some testing environments provide good control over the TCK and, therefore, good control is provided over the clocks sca, scb. In particular, the TCK frequency is well controlled, and TCK can be started or stopped at any time. See, for example, the testing environment described in Section 1.11 in Appendix A. Therefore, clocks sca, scb are also well controlled in the single scan operation.
IC 110 also has a multiple internal scan mode in which all the chains 126.1 through 126.17 are scanned simultaneously. This mode is suitable for manufacturing, when a number of standard tests are to be run quickly. In this mode, clocks sca, scb are derived from non-overlapping clocks provided on test clock input pins TCA, TCB. TCA and TCB are dedicated test clock input pins in some embodiments. Using separate test clock pins TCA, TCB provides well controlled clocks sca, scb and also simplifies interface between IC 110 and existing manufacturing test equipment such as Schlumberger ITS 9000. Separate clock pins TCA, TCB also facilitate use of ATPG (Automatic Test Pattern Generator) software such as Sunrise.TM. which is ATPG software available from ViewLogic of San Jose, Calif.
Each chain 126.x includes also a scan-in data input si.sub.-- x and a scan.sub.-- out data output so.sub.-- x. In the single scan operation, input si.sub.-- x receives data from the JTAG pin TDI. Of note, in the single scan mode, only one chain 126.i is scanned. The output so.sub.-- x provides data to the JTAG output pin TDO.
In the multiple internal scan operation, inputs si.sub.-- x receive data from MSP pins 130, and outputs so.sub.-- x provide data to MPS pins 132. In normal (non-testing) operation, pins 130 and 132 are bidirectional pins. See Appendix A, Section 1.6.5. The single and multiple internal scan modes are described in U.S. patent application Ser. No. 08/733,132 filed by S. Baeg on the same date as the present application, entitled "Adaptable Scan Chains for Debugging and Manufacturing Test Purposes", incorporated herein by reference.
During testing, function blocks that include chains 126 may be clocked to simulate normal operation. The function blocks are clocked by clocks CLKOUTs both when normal operation is simulated during testing and when normal operation actually takes place. During testing, the clocks CLKOUTs can be derived from the TCK clock. Alternatively, these clocks can be derived from normal system clocks CLKINs provided on inputs 140 and used for normal operation. Deriving CLKOUTs from TCK allows one to have good control over CLKOUTs. Of note, in some embodiments the clocks CLKINs are free running (and hence not well controlled).
In some tests, clocks CLKOUTs are taken from test clocks mult.sub.-- clk1, mult.sub.-- clk2 on respective pins AD05.sub.-- MT5, AD04.sub.-- MT4. In normal mode these pins are bidirectional pins used for other purposes.
Internal tests use JTAG controller 144 (TAP controller), JTAG instruction register 148, JTAG instruction decoder 152, and other JTAG circuitry in JTAG block 156. Use of boundary scan JTAG circuitry for internal testing, and use of the JTAG clock pin TCK to generate clocks for internal testing, simplifies the internal testing circuitry and reduces the clock input pin count.
The TCK clock is provided to JTAG block 156 to control the operation of the JTAG circuitry as known in the art. TCK is also connected to test clock generator 160. Clock generator 160 generates from the TCK clock two non-overlapping clocks jsca, jscb having the same frequency as TCK. Clock/data multiplexer 164 receives the clocks jsca, jscb and also receives the clock signals psca, pscb from respective test clock pins TCA, TCB. In some manufacturing tests, clocks psca, pscb are non-overlapping clocks having equal frequencies.
In the single internal scan operation, multiplexer 164 provides clocks jsca, jscb on respective outputs sca.sub.-- x, scb.sub.-- x of a chain 126.x selected by JTAG block 156. The remaining clocks sca.sub.-- i, scb.sub.-- i are held low (at VSS). In the multiple scan operation, multiplexer 164 provides the clocks psca, pscb on respective outputs sca.sub.-- x, scb.sub.-- x to all chains 126.
In the single scan operation, multiplexer 164 receives the TDI data from JTAG block 156 via line 166 and provides the data to the selected chain on the respective output si.sub.-- x. All the scan-out outputs so.sub.-- i of chains 126 are connected to respective inputs of multiplexer 168 in block 156. The output of MUX 168 is connected to pin TDO. In the single scan operation, the data scanned out to output so.sub.-- x of the selected chain 126 go to MUX 168, and then to the pin TDO.
In multiple internal scan operation, multiplexer 164 receives data from pins 130. In some embodiments, there are only 10 pins 130. Chains 126 are reconfigured to provide 10 chains (some of the chains are combined). The chain reconfiguration is described in the aforementioned patent application "Adaptable Scan Chains for Debugging and Manufacturing Purposes", Application Ser. No. 08/733,132. Multiplexer 164 provides the data from pins 130 to ten of the outputs si.sub.-- x. Ten scan chain outputs so.sub.-- y of the ten reconfigured chains are provided on respective ten pins 132.
Multiplexer 164 is controlled by signals INSS from JTAG block 156.
Clocks jsca, jscb are also provided to system clock generator 174. Clock generator 174 also receives: 1) normal mode clocks from inputs 140; 2) clock mult.sub.-- clk1 from pin AD05.sub.-- MT5; and 3) clock mult.sub.-- clk2 from pin AD04.sub.-- MT4. In the normal operation, clock generator 174 generates CLKOUTs from the normal clocks 140. In non-scan test operations (for example, in BIST), clock generator 174 generates the output clocks CLKOUTs from normal clocks 140, scan clocks jsca, jscb, and/or clocks mult.sub.-- clk1, mult.sub.-- clk2, as described below. Clock generator 174 is controlled by signals from JTAG block 156.
FIG. 2A is a circuit diagram of one embodiment of test clock generator 160. Pin TCK is connected to an input of inverter 204. The output of inverter 204 is connected to the input of inverter 208 and to one of the two inputs of NAND gate 214. The output of inverter 208 is connected to the other input of gate 214. The output of gate 214 is connected to a set (S) input of data flip flop 220. Flip flop 220 is positive-edge triggered. When the set input is low, the flip flop output Q is high.
Pin TCK is connected to the clock input of flip flop 220. The data input D of flip flop 220 is connected to VSS (ground in some embodiments). The data output Q of flip flop 220 is connected to CMOS buffer 230. The output of buffer 230 is connected to one of the two inputs of NOR gate 240. The other input of gate 240 is connected to the output of inverter 246 whose input is connected to pin TCK. The output of gate 240 is connected to the input of buffer 250. The output of buffer 250 provides the signal jscb.
Pin TCK is also connected to the input of inverter 260. The output of inverter 260 is connected to one of the two inputs of NAND gate 264. The other input of gate 264 is connected to pin TCK. The output of gate 264 is connected to the set input of flip flop 270 which is identical to flip flop 220. Pin TCK is connected to the input of inverter 274 whose output is connected to the clock input of flip-flop 270. The data input of flip flop 270 is connected to VSS. The direct output Q of flip flop 270 is connected to the input of buffer 280 whose output is connected to one of the two inputs of NOR gate 284. The other input of gate 284 is connected to the output of inverter 288 whose input is connected to the output of inverter 274. The output of gate 284 is connected to the input of buffer 292. The output of buffer 292 provides the signal jsca.
In some embodiments, inverter 208 is nine serially connected CMOS inverters. Inverter 260 is also nine serially connected CMOS inverters. Each of buffers 230, 280 is 24 serially connected CMOS inverters.
Clock/data multiplexer 164 includes a separate multiplexer 164.x (FIG. 2B) for each chain 126.x. In multiplexer 164.x, data output si.sub.-- x is the output of multiplexer 310. The data inputs D0, D1 of multiplexer 310 received respective signals psi.sub.-- x, jsi. Signal jsi is a data signal received from pin TDI via line 166 (FIG. 1) in the single internal scan mode. Input psi.sub.-- x receives data in multiple internal scan operation from one of pins 130 or from a scan output of another chain 126.i. (As described above, in the multiple internal scan mode several chains 126 can be combined into a single chain.) The select input S of multiplexer 310 is connected to input mult.sub.-- n of multiplexer 164.x. In the signal names, suffix ".sub.-- n" indicates that the signal is active low. Signal mult.sub.-- n is asserted (driven low) by block 156 to indicate the multiple internal scan mode.
The scan operation in the multiple internal scan mode is indicated by a signal "mult.sub.-- scan.sub.-- mode" on the MSP pin AD03.sub.-- MT3 (not shown) which is a bidirectional pin in normal operation. See Appendix A, Table 14. When mult.sub.-- n is asserted (low), mult.sub.-- scan.sub.-- mode is asserted to configure function blocks for the scan operation.
When the input S of multiplexer 310 is low, multiplexer 310 selects its input D0, that is, psi.sub.-- x. When the select signal S is high, multiplexer 310 selects D1 (jsi).
Signal mult.sub.-- n is connected to select inputs S of multiplexers 314, 318. When mult.sub.-- n is low, multiplexer 314 selects input psca connected to pin TCA (FIG. 1), and MUX 318 selects pscb connected to TCB. When mult.sub.-- n is high, MUX 314 selects input jsca from clock generator 160, and multiplexer 318 selects input jscb from clock generator 160.
The output of multiplexer 314 is connected to input D1 of multiplexer 322. The output of multiplexer 318 is connected to input D1 of multiplexer 326. Multiplexers 314, 318, 322, 326 are identical to multiplexer 310. The output of multiplexer 322 provides signal sca.sub.-- x. The output of multiplexer 326 provides signal scb.sub.-- x.
The inputs D0 of multiplexers 322, 326 are connected to VSS.
The select input S of multiplexer 322 is connected to the output of OR gate 330. Gate 330 ORs the outputs of OR gate 334 and NOR gate 338. One of the two inputs of gate 334 is connected to the output of inverter 348 whose input is connected to input mult.sub.-- n. The other input of gate 334 is connected to the output of inverter 352 whose input is connected to a system reset signal mrst.sub.-- n.
One of the two inputs of NOR gate 338 is connected to input bist.sub.-- cnt of multiplexer 164.x. The other input of NOR gate 338 is connected to the output of NAND gate 356. One of the two inputs of gate 356 receives signal shiftdr from JTAG block 156. Signal shiftdr is a standard JTAG signal indicating that the JTAG controller is in state Shift.sub.-- DR. See the aforementioned book "The Test Access Port and Boundary-Scan Architecture", page 41 (FIG. 4-8). The other input of gate 356 is connected to input dr.sub.-- x.
The select input S of multiplexer 326 is connected to the output of OR gate 360. One of the two inputs of gate 360 is connected to the output of OR gate 334. The other input of gate 360 is connected to the output of NOR gate 364. One of the two inputs of gate 364 is connected to input bist.sub.-- cnt. The other input of gate 364 is connected to the output of NOR gate 368. The two inputs of gate 368 are connected to respectively inputs dr.sub.-- x, corsdr.
Inputs mrst.sub.-- n, mult.sub.-- n, shiftdr, dr.sub.-- x, corsdr, bist.sub.-- cnt are the outputs of JTAG block 156. Input mrst.sub.-- n receives a system reset signal. During normal operation or testing, this signal is high.
Signal mult.sub.-- n is generated by JTAG instruction decoder 152. This signal is asserted when JTAG controller 144 receives a multiple scan chain instruction (a private instruction described in Appendix A, Table 6) and the controller is in the Run-Test/Idle state. When mult.sub.-- n is low, multiplexers 322, 326 select their inputs D1, and the clocks on TCA, TCB are provided to outputs sca.sub.-- x, scb.sub.-- x.
When mult.sub.-- n is high, the inputs D1 of multiplexers 322, 326 receive respective signals jsca, jscb. The select inputs S of multiplexers 322, 326 receive signals depending on signals shiftdr, dr.sub.-- x, corsdr, and bist.sub.-- cnt. Signal bist.sub.-- cnt generated by JTAG instruction decoder 152 is high when JTAG controller 144 receives instruction BIST or GBIST shown in Appendix A, Table 9, or any of the instructions in Table 7 or the last instruction "ARM7 intest/BIST" in Table 4. These are private instructions for BIST. The high bist.sub.-- cnt causes multiplexers 322, 326 to provide the clock signals jsca, jscb on respective outputs sca.sub.-- x, scb.sub.-- x.
Signal corsdr is driven high by JTAG block 156 in the JTAG controller states Shift-DR and Capture-DR. Signal dr.sub.-- x is driven high by JTAG block 156 when the corresponding chain 126.x is selected as a test data register by JTAG controller 144. When dr.sub.-- x is high, it enables multiplexers 322, 326 to select respectively jsca, jscb when the respective signal shiftdr, corsdr is high. Thus when dr.sub.-- x is high, the respective chain 126.x can be scanned or can capture data in the single scan mode.
FIG. 2C illustrates a portion of clock generator 174. Clock generator 174 includes a multiplexer 410 for each single-bit output on clock lines CLKOUTs. FIG. 2C illustrates multiplexers 410.1, 410.2 that generate non-overlapping system clocks clk1i, clk2i. Each of clocks clk1i, clk2i appears on output CLKOUT of respective multiplexer 410. Each multiplexer 410 has three clock inputs TCLK, CLKIN, jm.sub.-- clk. One of the three clocks, or zero, is provided on multiplexer output CLKOUT depending on the select inputs ck.sub.-- bypass, ck.sub.-- jtag.sub.-- cntl, clk.sub.-- cnt, mf.sub.-- mode. Input syn.sub.-- clk receives a synchronizing signal. When the select inputs change, the change becomes effective (i.e., CLKOUT switches to a different clock) on the rising edge of the synchronizing signal.
Each MUX 410 satisfies the following rules:
If mf.sub.-- mode=1, then MUX 410 selects TCLK, i.e., CLKOUT=TCLK;
if mf.sub.-- mode=0, and ck.sub.-- bypass=0, then CLKOUT=CLKIN;
if mf.sub.-- mode=0, ck.sub.-- bypass =1, and ck.sub.-- jtag.sub.-- cntrl=1, then CLKOUT=jm.sub.-- clk;
if mf.sub.-- mode=0, ck.sub.-- bypass=1, ck.sub.-- jtag.sub.-- cntrl=0, and clk.sub.-- cnt=0, then CLKOUT=0;
if mf.sub.-- mode=0, ck.sub.-- bypass=1, ck.sub.-- jtag-cntl=0, and clk.sub.-- cnt=1, then CLKOUT=CLKIN;
when CLKOUT is changed to CLKIN, the change always takes place when CLKIN is low.
The inputs mf.sub.-- mode of all multiplexers 410 receive a signal mf.sub.-- mode.sub.-- i (manufacturing mode internal) from JTAG instruction decoder 152. Signal mf.sub.-- mode.sub.-- i is asserted high by instruction decoder 152 when the decoder decodes the multiple scan instruction (Appendix A, Table 6). Multiplexers 410 select the inputs TCLK. Inputs TCLK are connected as shown in Appendix C, at lines B28-B43. In each of the equations in lines B28-B43, the left-hand side is a signal generated by a respective multiplexer 410 on its output CLKOUT. Thus, in lines B28, B29, the left-hand sides clk1i, clk2i are generated by respective multiplexers 410.1, 410.2. The right-hand side is a clock signal delivered to input TCLK of the respective multiplexer 410. Thus, input TCLK of multiplexer 410.1 receives signal test.sub.-- sys.sub.-- clk1; input TCLK of multiplexer 410.2 receives test.sub.-- sys.sub.-- clk2. Signals test.sub.-- sys clk1, test.sub.-- sys.sub.-- clk2 are signals mult.sub.-- clk1, mult.sub.-- clk2 (FIG. 1). The two signals are nonoverlapping clocks having equal frequencies.
The TCLK inputs of multiplexers 410 corresponding to lines B39-B43 in Appendix C are connected to the normal mode clock inputs 140 (FIG. 1).
Inputs ck.sub.-- bypass of all multiplexers 410 receive signal ck.sub.-- bypass.sub.-- i. When mf.sub.-- mode.sub.-- i=0 and ck.sub.-- bypass.sub.-- i =0, multiplexers 410 select their normal mode inputs CLKIN. These inputs are connected as shown in lines B45-B60 in Appendix C. In particular, as shown in lines B45, B46, multiplexers 410.1, 410.2 receive on their inputs CLKIN the respective clocks clk1, clk2 generated by clock generator 430 from the system clock sysclk provided on pin MSPCK. Pin MSPCK is one of inputs 140 (FIG. 1). As shown in line B48, the multiplexer 410 generating the clock arm7.sub.-- clk receives on its input CLKIN the clock clk1/2 (clock clk1 divided by 2). Multiplexer 410 corresponding to line B49 receives the inverse of that clock. The remaining multiplexers 410 receive the signals as shown in Appendix B.
Signal ck.sub.-- bypass.sub.-- i is bit 11 of the MCR (memory control register) described in Appendix A, Table 12. MCR is one of JTAG design-specific data registers.
Inputs ck.sub.-- jtag.sub.-- cntl of all multiplexers 410 receive the signal ck.sub.-- jtag.sub.-- cntl.sub.-- i from JTAG block 156. ck.sub.-- jtag.sub.-- cntl.sub.-- i is MCR bit 12. If ck.sub.-- jtag.sub.-- cntrl.sub.-- i=1 (high), and mf.sub.-- mode.sub.-- i=0 and ck.sub.-- bypass=1, multiplexers 410 select their inputs jm.sub.-- clk. These inputs are connected as shown in Appendix C, lines B62-B77. In particular, in multiplexers 410.1, 410.2, these signals are connected to VSS (lines B62, B63). In the multiplexer generating the clock clk1.sub.-- e (line B64) input jm.sub.-- clk receives signal jtag.sub.-- mem.sub.-- clk1 which is a version of jsca (FIG. 1). In normal operation, clk1.sub.-- e is similar to clk1i but is slightly earlier than clk1i ("e" stands for "early").
In multiplexer 410 generating arm7.sub.-- clk (line B65), input jm.sub.-- clk receives signal jtag.sub.-- arm.sub.-- clk which is a version of jsca. In the remaining multiplexers 410, inputs jm.sub.-- clk receive VSS.
Inputs clk.sub.-- cnt of all multiplexers 410 receive signal clk.sub.-- cnt.sub.-- i. Signal clk.sub.-- cnt.sub.-- i is generated by clock counter 420 (FIG. 2C) in JTAG block 156. This signal is used for internal tests that require one or more function blocks to be clocked by their normal clocks for a certain number of cycles of the main system clock sysclk. Clock sysclk is delivered to clock counter 420. Clock counter 420 keeps the clock count in MCR bits 1-10 (clk.sub.-- cnt.sub.-- 0 through clk.sub.-- cnt.sub.-- 9).
When a predetermined number of sysclk cycles is to be counted, JTAG block 15G selects MCR as a JTAG test data register and shifts the number of cycles into the MCR. When the test begins, clock counter 420 asserts clk.sub.-- cnt.sub.-- i high for the specified number of cycles of sysclk.
If mf.sub.-- mode.sub.-- i=0, ck.sub.-- bypass.sub.-- i=1, ck.sub.-- jtag.sub.-- cntl=0, and clk.sub.-- cnt=1, multiplexers 410 select their inputs CLKIN, as in normal mode. See lines B78-B93 in Appendix C.
If mf.sub.-- mode.sub.-- i=0, ck.sub.-- bypass.sub.-- i=1, ck.sub.-- jtag.sub.-- cntl.sub.-- i=0, and clk.sub.-- cnt=0, then all multiplexers 410 drive their outputs CLKOUT to 0 (Appendix C, lines B94-B109).
In multiplexers 410.1, 410.2, the inputs syn-clk receive signal clk1. Similarly, in other multiplexer pairs which receive in normal mode a pair of non-overlapping clocks, the inputs syn.sub.-- clk are connected to one of the two clocks connected to inputs CLKIN of the pair. This is true, for example, for multiplexers 410 generating the clocks PCICK1, PCICK2. In the remaining multiplexers 410, the input syn.sub.-- clk is connected to the input CLKIN.
FIG. 2D is a block diagram of a single multiplexer 410 (all the multiplexers 410 are identical to each other). Inputs ck.sub.-- bypass, ck.sub.-- jtag.sub.-- cntl, clk.sub.-- cnt, mf.sub.-- mode, syn.sub.-- clk are connected to respective inputs ck.sub.-- bpass, ck.sub.-- jtag.sub.-- cntrl, clk.sub.-- cnt, mf.sub.-- mode, synclk of control circuit 510 whose diagram appears in FIG. 2E. Inputs TCLK, CLKIN, jm.sub.-- clk, mf.sub.-- mode of MUX 410 are connected to respective inputs D0, D1, D2, S0 of circuit 520 whose diagram appears in FIG. 2F. The circuit 510 outputs ctrl2, sctrl0, sctrl0n, sctrl1, sctrl1n, sctrl2, sctrl2n are connected to respective inputs S2, or SYNS0, SYNS0N, SYNS1, SYNS1N, SYNS2, SYNS2N of circuit 520. The output CLKOTN of circuit 520 is connected to circuit 530 which consists of 8 inverters connected in parallel. The output of circuit 530 provides the output signal CLKOUT.
As shown in FIG. 2E, the input synclk of circuit 510 is connected to the clock inputs of positive-edge triggered data flip flops 610, 620, 630. The Q outputs of the three flip flops provide respective signals sctrl0, sctrl1, sctrl2. The complementary outputs QN of the three flip flops provide respective complementary signals sctrl0n, sctrl1n, sctrl2n. Flip flops 610, 620, 630 are identical to each other.
The input mf.sub.-- mode of circuit 520 is connected to the data input D of flip flop 610 and to one of the two inputs of NOR gate 640. The output of gate 640 is connected to the data input of flip flop 620. The second input of gate 640 is connected to the output of AND gate 644. One of the two inputs of gate 644 is connected to input ck.sub.-- bpass of circuit 510. The other input of gate 644 is connected to the output of NAND gate 650. One of the two inputs of gate 650 is connected to the output of inverter 654. The input of inverter 654 is connected to input ck.sub.-- jtag.sub.-- cntl of circuit 510. The other input of circuit 650 is connected to input clk.sub.-- cnt of circuit 510.
Input mf.sub.-- mode is connected to the input of inverter 660 whose output is connected to one of the three inputs of NAND gate 664. The other two inputs of gate 664 are connected respectively to input ck.sub.-- bpass of circuit 510 and to the output of gate 650. The output of gate 664 is connected to the input of inverter 670. The output of inverter 670 is connected to the data input D of flip flop 630 and to the output ctrl2 of circuit 510.
As shown in FIG. 2F, inputs SYNS0, SYNS0N of circuit 520 are connected respectively to the NMOS and PMOS gates of pass gate 710. (Pass gate 710 has an NMOS and a PMOS transistors connected in parallel). The input D of gate 710 is connected to the output of inverter 714. The input of inverter 714 is connected to the output of AND gate 718. The two inputs of gate 718 are connected to respective inputs S0, D0 of circuit 520.
Inputs SYNS1, SYNS1N of circuit 520 are connected respectively to the NMOS and PMOS gates of pass gate 730 identical to gate 710. The input D of gate 730 is connected to the output of inverter 734. The input of inverter 734 is connected to input D1 of circuit 520.
Inputs SYNS2, SYNS2N are connected respectively to the NMOS and PMOS gates of pass gate 740. Gate 740 is identical to gate 710. The data input of gate 740 is connected to the output of inverter 744. The input of inverter 744 is connected to the output of AND gate 748. The two inputs of gate 748 are connected to respective inputs S2, D2 of circuit 520.
The data outputs of pass gates 710, 730, 740 are connected to the input of inverter 754 and the output of inverter 760. The output of inverter 754 is connected to the input of inverter 760. The output of inverter 754 is also connected to the inputs of inverters 764, 768. The outputs of inverters 764, 768 are connected to output CLKOUTN of circuit 520.
The embodiments described above and in the appendices below do not limit the invention. In some embodiments, the invention is implemented using CMOS technology, but other technologies are used in other embodiments. The invention is defined by the appended claims.
Appendix A
Test and normal modes in MSP are described in this chapter. All those modes are controlled by a JTAG controller using five JTAG pins only.
1.2 Application and Assumptions
All the test schemes, which are described in the following sections are implemented to aid MSP hardware testing during the processes of both prototype debugging and manufacturing test.
This material assumes that users know IEEE 1149.1 JTAG protocols and LSSD type scan properties. Please refer to following material for more information in LSSD, JTAG, and MSP specification.
Test Compiler Reference Manual Ver. 3.2a (Synopsys, Inc. 1994)
IEEE Standard 1149.1-1990: IEEE Standard Test Access Port and Boundary Scan Architecture, 1990
Preliminary MSP-1EX System Specification, Samsung Semiconductor Inc. 1996
1.3 Features
LSSD type scan design
Independent scan operation for each functional block
Parallel scan operation for manufacturing test
Two boundary scan chains for MSP and ARM7
All JTAG basic instructions, intest, extest, and sample/preload
Memory access operation
BIST clock generation
1.4 Test methodology abstract
MSP testing is aided with various test schemes, which incorporate LSSD (Level Sensitive Scan Design) type scan design, JTAG controller, and mixing techniques of DFT (Design For Testability) and BIST (Built In Self Test) for memory test.
The control blocks in MSP are made to be fully scannable. The data path blocks are partially scanned to reduce hardware penalty. The scan chains are partitioned by functional block to aid debugging.
There are two boundary scan chains for MSP and ARM7, which are controlled using one JTAG controller. The JTAG control logic is able to scan boundary scan chains as well as the internal scan chains.
To debug and test in silicon, hybrid DFT method is used for the cache memory. It is a combined method of DFT, JTAG, and BIST. The automatic comparison scheme has been embedded for cache to reduce test time while MARCH C algorithm is executed. The memories are controlled using memory control register located inside the JTAG controller.
1.5 Conceptual JTAG Requirements
The general requirements that JTAG controller should provide are discussed. They are specified in the points of functional debugging rather than board level testing.
Boundary scan for MSP and ARM7 core: arbitrary functional vectors should be supplied to the scan chain, which implies that a clock pulse in clock pads can be emulated through the scan chain. The tri-state and bi-directional controls should be possible in a group of related signals such as data bus. Arbitrary patterns from the off-chip and internal logic are captured and shifted to TDO pin. It should be able to drive the external chip and internal logic via the boundary scan cell for interconnection test and internal logic testing respectively. At least one of boundary scan operation guarantees that all the internal state machines are frozen until the boundary scan cells are updated by JTAG controller.
Scan in/out test for functional blocks: scan chains are partitioned by the functional block unit. Exceptions can be made if a block has much less scan cells compared to other blocks. Scanning in and out arbitrary values should be possible for every scan cell. During the scan operations for functional blocks, all the internal ff/latches except the selected chain, boundary scan cells, cache, and register should hold the previous values. This is critical for efficient silicon debugging process. In other words, all the data registers, boundary scan, ARM7 boundaries scan should be independently controllable.
Generation of system clock in test mode: the MSP chip is executed as many system clock cycles as users want. This is performed in two ways in terms of clock pulse generation. First, the clock pulses are generated using boundary scan cell assigned to clock ports. This will be extremely slow because it requires scanning all the boundary scan cells three times to create one pulse (0-1-0). In case of the system clock this feature is not supported. The capture only boundary scan cell is used. If the TCK is 20 MHz, about 24 Khz clock can be emulated using the boundary scan chain in MSP. Note that the boundary scan length in MSP is 270 bits long. Secondly, the clock pulse can also be generated using the JTAG clock. One pulse of the JTAG clock, TCK is the same as one system clock pulse. This is very fast compared to the previous one. The second way of clock generation is implemented for the main system clock only. Other clocks are emulated using the boundary scan chain.
Embedded memory access via JTAG: the memories, IDC and register file inside MSP are controlled through JTAG interface in test mode. Read and write operation to an arbitrary location are provided. Any read/write operations to one RAM should not affect the contents in the other RAMs.
Multiple independent scan: the multiple scan chains are configured based on the number of scan cells rather than functional blocks. They are scanned simultaneously. JTAG controller is responsible for providing the circuitry of the scan chain reorganization.
JTAG instructions: all the basic JTAG instructions should be implemented in addition to the instructions to provide the functionalities specified in above items in this section. During JTAG instruction change, all the boundary scan cells are not changing, all ff/latches freeze their state, and memories hold their current contents. This will help predict the current state during the prototype debugging process.
1.6 Classified JTAG Operations
This section discusses the implementation issues of the JTAG requirements discussed in the previous section. JTAG operation in MSP design can be classified into six different categories. Each category can have a little variation depending on its application. You will see the matching instructions for the categories in the section of JTAG design details. The six different categories are normal operation, boundary scan operation, single internal scan operation, memory access operation, multiple internal scan operation, and pseudo system clock operation modes. They are discussed in the following subsections.
1.6.1 Normal operation
All the functional and memory blocks are operating as they are supposed to. All the shared input and output pins and test logic are properly redirected to provide legal signals in this mode. This mode is entered by enabling JTAG standard signal, TRST.sub.-- N (=0).
1.6.2 Boundary scan operation
Two boundary scan chains are implemented. They are for MSP and ARM7 core. All the I/O ports in MSP and ARM7 have their appropriate boundary scan cells except the five JTAG related pins. The specific boundary scan cells for the scan chains can be found in the sections of MSP boundary scan and ARM7 boundary scan. The two boundary scan chains will share one JTAG controller and must be independently scannable. Intest, extest, and sample/preload instructions for both scan chains are implemented.
1.6.3 Single internal scan operation
In this mode, JTAG takes over the hardware control in terms of data transfer inside MSP. All the functional blocks, which have scan chains in them can be independently scanned in or out. "Independently" means that the scan chains which are not selected do not change their states. Only the selected block takes a scan input from TDI port and updates the scan chain.
This scan mode is primarily used for chip debugging. You can set and observe the values in scan chains whenever you want. Since only one scan chain can be accessed at a time, it is as if there were only a single chain in terms of testing time. It is not a good candidate for production test even though it can be used for the purpose.
1.6.4 Memory access operation
The vd.sub.-- ram and tag.sub.-- ram in IDC (Instruction Data Cache) are selected and accessed at the same time. The data.sub.-- ram can be independently accessed. Any address in the RAMs can be independently read and written in this mode. The memory operations are executed serially by scan chain and JTAG controller.
When one memory is accessed for read and write operations, the other memories do not change their contents. Below is how you access the memories.
1. Change to single scan mode and select the RAM block. Scan in the necessary data. At this time, you can set the address counter, and the data to be written. Since this is the scan mode, no memory write operation should be performed.
2. Go out of single scan mode and step into memory access operation. In this mode, a memory to be tested can be selected. JTAG controller provides a select signal for each memory. They are data.sub.-- ram.sub.-- test.sub.-- en, vt.sub.-- ram.sub.-- test.sub.-- en, and register.sub.-- file.sub.-- test.sub.-- en. Only one of them can be active at a time.
3. Once one memory is selected, memory and address counter control signals can be controlled using JTAG. The control names are mem.sub.-- we, mem.sub.-- hwd, mem.sub.-- compare, mem.sub.-- add.sub.-- u/d, mem.sub.-- add.sub.-- cnt, mem.sub.-- add.sub.-- reset, and mem.sub.-- add.sub.-- set. Their usages can be found in the section of JTAG interface signals.
1.6.5 Multiple internal scan operation
In addition to the single scan mode, there is multiple scan mode in which 10 different scan chains are accessed simultaneously from MSP I/O ports. They are basically reorganized from the existing scan chains based on the scan ff/latch counts.
Multiple scan chain operation is implemented with production test in mind. 10 scan flip-flops can be accessed in every clock cycle. Furthermore, no JTAG instruction switching is necessary to have a specific function block scanned as in single scan mode.
The ten scan inputs are shared with normal functional bidirectional pins. The names are ad06.sub.-- si0, ad07.sub.-- si1, ad08.sub.-- si2, ad09.sub.-- si3, ad10.sub.-- si4, ad11.sub.-- si5, ad12.sub.-- si6, ad13.sub.-- si7, ad14.sub.-- si8, ad15.sub.-- si9. The ten test pins are muxed with the normal bidirectional pins, ad16.sub.-- so0, ad17.sub.-- so1, ad18.sub.-- so2, ad19.sub.-- so3, ad20.sub.-- so4, ad21.sub.-- so5, ad22.sub.-- so6, ad23.sub.-- so7, ad24.sub.-- so8, ad25.sub.-- so9.
The two input ports, tca and tcb are used for scan clock stimulus. Since the two ports are dedicated for testing, it does not give any limitation for test generation. Note that they are not coming from the JTAG controller but from a tester.
On the tester during manufacturing, MSP is set to multiple scan mode, in which the boundary scan cells are in transparent mode. So that all the test vectors in normal ports can be applied through boundary scan cells.
The signal which tells the JTAG is in the multiple state can be used to direct the bidirectional I/O cells. It avoids the preprocessing step to direct the bidirectional pins.
1.6.6 Pseudo system clock operation
After the scan chains have been loaded, some portion of MSP needs to be executed in single or multiple clocks during prototype debugging. JTAG controller generates two non overlapping clocks, jsca, jscb which will be muxed internally with the two system clocks, clk1, clk2. The main difference from the normal mode is clock source. In this mode, the clocks are coming from the JTAG controller instead of from system clock. It is called pseudo system clock. The clocks from the output of the muxes affect the system operation. Currently, the pseudo system clock is hooked up to the IDC block only. While the clocks are applied, other system clocks are frozen.
In this mode, you can apply JTAG generated clocks for the duration of user specified number of clock cycles. However, clock counting is not implemented inside the JTAG controller. It is provided through a proTEST-PC and AVL (see the section on "hardware test environment").
1.7 Signal overview in the test modes
The overview diagram is shown in FIG. 3. All six different modes can be entered through the JTAG instructions. This means there are no dedicated I/O pins to switch back and forth between the modes. A JTAG instruction should be loaded first before you go to the desired mode.
Table 1 shows the general picture of the important signals in the six different modes. Three kinds of clocks, system clock, scan clock, and pseudo system clock, are used to support the different test modes. The view of the clocks in MSP are shown in FIG. 4. System clock refers to the two non overlapping clocks, clk1 and clk2, which are derived from system clock. One of those will be connected to the normal clock port of scan flipflops and scan latches depending on the application.
Scan clock is two non overlapping clocks for scan operation, which will be connected to scan clock ports for every scan flipflops and scan latches. The scan clocks are generated by either JTAG controller or MSP input pads, tca and tcb. They will be selected appropriately depending on the test modes. In the single scan mode, two scan clocks, jsca, jscb are pulsed to a selected functional block and two clock ports, tca, tcb stay at logic 0. In the multiple scan mode, jsca and jscb stay at logic 0 and tca and tcb are enabled.
Pseudo system clock is also two non overlapping clocks which are generated by JTAG controller. They are the same signals as scan clocks, jsca and jscb. However they are going to a different place at this time, which is the normal clock port instead of scan clock port. Notice that the single scan and pseudo system clock modes are not supposed to happen at the same time. The clock is named as pseudo system clock because they are used for system execution rather than scan operation. The clocks will be denoted as psca, pscb.
Functional block in table 1 refers to any hardware module in MSP design. It could be multiplier, FALU etc. Memory blocks are either IDC or register file. Input pins refer to MSP input or inout pads except JTAG input pins. Output pins refer to MSP output or inout pads except TDO pin.
In the normal mode, the system clocks, clk1, clk2 are pulsed, which basically executes the MSP as stated in the MSP specification. Scan clocks, sca and scb should not be active (sca=0, scb=0). If they are active, the scan flipflops and latches in the MSP go to unknown states. Pseudo system clock is inactive. So that the clocks which are carried to all sequential elements are coming from the system clock pin, mclk, instead of JTAG controller. All the test logic should not affect the normal functionality.
In the boundary scan mode, no clock is active. The boundary scan chains are shifting values via JTAG generated clocks. All functional blocks are freezing their states during scan operation.
In the single scan mode, only one block can be selected and scanned in or out using scan clocks. During this period, only five JTAG pins are accessed. Other I/O pins are not significant. For the same reason in normal mode, the system clock should not be active. All memory write should be disabled during this period.
In the memory test, the pseudo system clock is used for memory read and write operations. Input and outputs are not significant in this mode too since all data to be processed are in scan chain in the memory block. All the memory controls are steered by the memory control register which resides in JTAG control logic.
Multiple scan mode uses the scan clock which are coming from input pads, tca and tcb. The ten scan input ports and ten scan output ports are used to supply scan data instead of the JTAG port, TDI.
Pseudo normal mode uses the clock from JTAG to execute the MSP. In this mode the boundary scan cells at MSP I/O are not transparent but in intest mode. So that the input is steady in this mode.
1.8 Clock control scheme via JTAG controller
Clock control scheme is incorporated to help the prototype debugging. The scheme implements clock stop, clock generation on demand, and clock restart. For the control signals, refer to special control registers in 1.10.4. Please refer to the clock specification for MSP clocks.
Clock stop: when clock stop request is made from JTAG controller to clock generator, the clocks to MSP, system clock, pci clock, and codec clocks stops at the first rising edge of each clock after clock stop request is made.
Clock stop request is made in two different ways. The first simple way is to issue the request regardless of the system state. The second way is to request after MSP is ready to stop clocks. JTAG controller broadcasts the clock shutdown notice to MSP and make stop request to clock generator after it recognizes the idle status from MSP. Currently, only vector core is implemented to issue its idle status to JTAG controller.
Clock generation on demand: Any number of clock cycles up to 1024 may be requested to clock generator through control register in JTAG controller. The number of clocks are for the system clock. Other clocks are generated in ratio with the system clock. The clocks which are generated on demand are the same as the original clocks. The request is made after the clocks are stopped.
Clock restart: when clock restart is requested, all the clocks start after the first rising edge of the clocks.
1.9 Global Reset Operation
System reset can be performed using the scan chains embedded in MSP chip. In this operation, the master reset signal goes low (active low) and remains there for the duration of reset operation.
Since the JTAG clock, TCK is not running in the normal operation, the system clock should be used to shift data into scan chains. Because the TCK is not running at this time, this can not be considered as one of JTAG instructions.
The functionality of this scheme is that when the master reset is low, the logic "0" value is shifted to all scan ff/latches. The conditions to be satisfied in reset operation are listed below.
The system clocks "clk1" and "clk2", and all other clocks which affect the scan ff/latches need to be disabled (clk1=0, clk2=0). This guarantees that only one kind of clock, which is scan clock, is applied to the scan ff/latches. This requires adding control logic to clock ports.
The system clock is used to generate the scan clocks, sca, scb. Since the scan operation need to be very slow, normal free running clock should not be used. The system clock will be divided by 2.
The master reset should be low enough to shift the reset value to scan ff/latches. The failure of not satisfying it will cause improper operation.
This operation has been implemented inside the JTAG controller section.
1.10 JTAG Design Details
This section describes MSP JTAG design issues, instructions, and their codes which are available. All the functionalities described in the previous sections can be achieved using the instructions described in this section.
The instruction decoder in JTAG controller was designed for possible 38 custom instructions. Currently 1 instruction is reserved for a future application. Out of 36, 17 instructions have an associated internal data register.
Serial output of each data register and an instruction register is muxed and connected to the TDO pin. When selected, by an instruction, data from the TDI pin can be serially shifted through the selected data register, or the instruction register, and observed at the TDO pin.
In all JTAG circuits, MSB is the leftmost bit and the typical signal name looks like this "DATAN:0!". When integrating with other circuits this standard should be followed, for correct signal interconnections.
1.10.1 Requirements
The following items must be satisfied for JTAG controller to properly operate.
Input pins: TDI and TMS input pins must have an onchip pull-up register. If these pins are left unconnected by the user, JTAG controller inputs are still logic high. All JTAG input pins must be connected logic high or low level under all operating conditions, for proper operation of the JTAG controller.
Clock skew: Boundary scan register being about 270 bit long clock drivers should be designed and laid out such that there is minimum skew between bit 0 clock input and bit 270 clock input. JTAG controller is designed to work up to clock frequency of 40 Mhz maximum.
Clock condition: the clocks conditions to be observed during internal scan operation are listed below.
1. The clocks going to the normal clock port in scan latches have to be disabled.
2. The clocks going to the normal clock port in scan flipflops have to be disabled.
1.10.2 Internal scan chains in MSP
The internal scan chains for JTAG controller are organized by functional block unit for effective chip debugging purposes. All internal scan chains are listed in table 2. The current scan chain partition does not affect the final testing time during production because the scan chains will be reorganized for production test purposes based on the number of scan cells in a chain. However it does affect the way MSP chip is debugged.
1.10.3 JTAG Instructions
JTAG instructions are described in tables 4 through 10. They are classified based on the JTAG operation classes discussed in the section of classified JTAG operations. "Test name" is the name of each instruction and imposes its application. The instruction code has to be shifted into the instruction register in the JTAG controller before accessing a specific data register. Register selected shows the data register which can be accessed in each instruction.
Table 4 shows the instructions for boundary scan in MSP. Eight of them are for MSP boundary scan chain. They select either MSP boundary scan chain or bypass register depending on their application. When boundary scan chain is selected, vectors can be loaded into the scan chain. Otherwise, MSP boundary scan is not accessible.
Three instructions in table 4 are for the ARM7 boundary scan chain. They select the ARM7 boundary scan chain.
Table 3 shows the control signals for boundary scan cell and system clock bypass signal. There are four mode signals to control two boundary scan chains for MSP and ARM7, which are itemized below. Please refer to the table of JTAG I/O signals in the next section for the explanation of other control signals, MSP.sub.-- bs.sub.-- disable, ARM7.sub.-- bs.sub.-- disable, and sys.sub.-- clk bypass.
MSP Mode.sub.-- I: MSP boundary scan input cell mode signal
MSP Mode.sub.-- O: MSP boundary scan output cell mode signal
MSP Mode.sub.-- C: MSP boundary scan control cell mode signal
ARM7 Mode.sub.-- I: ARM7 boundary scan input cell mode signal
ARM7 Mode.sub.-- 0: ARM7 boundary scan output cell mode signal
When a mode signal is low, the boundary scan cell becomes transparent to take inputs from normal input ports. When it is high, the output of boundary scan cells depends on the update latch in the boundary scan cell. (Please refer to the KGL75 data book for the details about boundary scan cells).
Table 5 shows internal scan chains for all functional blocks which can be accessed via JTAG controller. There is only one instruction for multiple scan mode in table 6.
The table 7 shows the memory access instructions. Three memories in IDC block can be controlled by JTAG controller. Data RAM and register file have their own instructions. Vd RAM and Tag RAM are accessed simultaneously. There is one more instruction available for future. It could be for ROM or another embedded RAM. MCR is memory control register which is located in JTAG controller.
Table 8 shows the default instruction when system is powered up. Table 9 shows the instruction for generating pseudo system clock which is actually coming from the JTAG pin TCK rather than the system clock. Thus you can control the number of clock cycles via the JTAG interface. Table 10 shows the available instructions for future application.
1.10.4 Special Control Registers
There are two special registers which are controlled by JTAG controller. They are used to control the internal logic or observe the status of the MSP system. The names are MCR (Mode Control Register) and OCR (Observation Control Register). The control signals for each control register are shown below.
1.10.5 Test scenarios using JTAG instructions 1.10.5.1 Debugging steps
A debugging process of MSP will involve taking a couple of steps, which are predefined and will be repeated. The brief steps to follow are described below. This is how to use the JTAG instructions during the procedure.
Step 0: Issue clock stop request: when you want to stop the clock for any reason while MSP is executing its operations, the clock stop flag needs to be issued first. It is issued through JTAG control logic. Then the flag is broadcast to every necessary functional block. JTAG instructions MCR/BIST1 or MCR/BIST2 can be used to issue the signal.
Step 1: Observing internal state: the next step is to know when to step into the JTAG controlled modes from the normal mode. In this mode, the internal state can be observed through OCR (Observation Control Register). The clock stop will not be activated until JTAG observes all signals from all the functional blocks. While MSP is executing its operations, the states can be observed through the TDO pin. The instruction to be used is monitor.
Step 2: Stopping the clocks: since the necessary states have been observed, you can stop all types of clocks when the system is idle. Clock stop is required to be able to scan the appropriate scan registers. You can selectively stop the clocks depending on how you set up the values in MCR. You should not scan the cell for the blocks for which normal clock is running. The clock stop signal is being issued while MSP is running with system clock. Any of the four instructions, MCR/BIST1, MCR/BIST2, MCR/BIST3, and MCR/BIST4 can be used to issue the clock stop signal. MCR/BIST1 and MCR/BIST2 can issue the signals while boundary scan cells are in transparent mode. The others can issue the clock stop signals while all input signals are blocked.
Step 3: Scanning the internal states: now, every clock is bypassed, so that there are no free running clocks. You can scan the appropriate blocks. You can use instructions 9-10 to scan the boundary of ARM7 blocks. The instructions 12 through 28 can be used to scan the functional blocks. Instructions 35 and 36 can be used to generate the fast clocks, which are coming from TCK. Before the clocks are restarted, you want to take the necessary setup in MSP. For instance you need to take care of the state machine of generating the half clocks like ARM clock.
Step 4: Restarting the clocks: now the system clock can be restarted by setting the values in MCR. The same instructions as in step 2 can be used in this step. Before starting clocks again, the clock stop flag will be reset to logic "0".
1.10.5.2 Manufacturing test operation
The manufacturing test mode can be entered using multiple scan instruction. Once decoded for this mode, the MSP is configured as follows.
10 bidirectional pins are configured as input ports
10 bidirectional pins are configured as output ports
1 bidirectional pin is configured as an input port of clk1
1 bidirectional pin is configured as an input port of clk2
1 bidirectional pin is configured as an input port of scan.sub.-- mode
The other bidirectional pins are controlled as in the normal mode
The ARM7 clock, which is same as I/O clocks is applied as the clk2
PCI clocks use the clk1, clk2
The scan clocks are generated by the two input pins, tca, tcb
All codec clocks are supplied from codec clock ports.
1.10.5.3 ARM7 execution
ARM7 is executed using the ARM7 intest instruction. The ARM7 boundary scan cells are not transparent. The input and output of ARM7 are applied and observed through the boundary scan chain.
The clock is generated from TCK to speed up the clock application. The three inputs, prog32, data32, and bigend are required to change its signal when mclk is high. To achieve it, the update signal is separate from the update signals of other boundary scan cells.
It should be noted that the mclk is shared with the I/O clock. Once the clock of ARM7 is triggered the state of the other blocks can be changing.
1.10.5.4 Cache and register file access
Load the MCR/BIST4 instruction, which selects the MCR as data register and blocks the input and output signals. The bist clock is generated in this mode to speed up the operations. By controlling the MCR, the read and write can be performed.
The clocks which go to cache and register file are muxed with test clock. The memory operation should not disturb the state in other logic blocks.
1.10.5.5 Vector only execution
Vector only execution requires considering the output of ARM7 block as the input of VP blocks. Use ARM7 boundary scan access instructions to do it.
1.10.5.6 Intest and Extest
Use intest and extest instructions.
1.10.6 JTAG interface signals
All JTAG interface signals are listed in table 11.
1.11 Hardware Test Environment
The hardware test environment is shown in FIG. 5. AVL (ASCII Vector Language) is both a test vector language, designed specifically for boundary scan testing, and a boundary scan test tool. It merges traditional parallel vector oriented Automated Test Equipment (ATE) languages with serial boundary scan testing defined by IEEE Standard 1149.1.
The proTest-PC is a PC-based test controller board capable of generating and receiving IEEE Std 1149.1 signals for testing components, boards and systems. AVL and proTest-PC are the products of AIS (Alpine Image Systems, Inc.).
During test process, all the test vectors for MSP will be formatted serially via AVL language and applied to MSP through proTest-PC board. Test vectors are the vectors which are applied to MSP I/O or scan chains. To ease the test vector application for all functional blocks, which is performed serially, AVL macros need to be developed to access particular location in scan chains. The communication will be made through the fine JTAG pins only. Please refer to following documents for more information.
AVL User's Guide, V1.80, Alpine Image Systems, Inc, 1995
User's Guide for proTEST-PC, V3.01, Alpine Image Systems, Inc, 1995
1.12 Embedded RAM Test Scheme
1.12.1 IDC
FIG. 6 shows the test scheme for IDC block. Test logics are inserted to blocks, CCU and IDC. All dotted lines stand for the signals in normal mode. CCU block provides the mux logics for the addresses in test and normal modes. Address is generated with 9 bit counter with set, reset, up/down, and count enable functions. All counter operation should be synchronous with the system clock, clk1. The four counter control signals, mem.sub.-- add.sub.-- ud, mem.sub.-- add.sub.-- cnt, mem.sub.-- add.sub.-- reset, and mem.sub.-- add.sub.-- set, are provided by JTAG controller. The first two bits in the MSB side need to be connected for the bank selection.
32 bit ben.sub.-- idc signals are set to logic 1 during testing the memory. There are two signals which select between test and normal signals. Vt.sub.-- ram.sub.-- test.sub.-- en is for testing vd.sub.-- ram and tag.sub.-- ram. Data.sub.-- ram.sub.-- test.sub.-- en is for data.sub.-- ram testing. If the signals are logic high, test data is selected.
IDC blocks have comparators embedded for automatic comparison while MARCH C algorithm is being applied. There are 6 memory control signals which are also provided by JTAG controller. Mem.sub.-- compare enables the comparison between input and output registers. If there is any error occurred, the output of comparator will produce logic 0. Otherwise, it is logic 1. All the I/O registers are in scan chain, through which input and output access can be made.
Mem.sub.-- hwd signal enables holding the data in the write register when it is logic 1. Please refer to MSP spec. for other memory control signals, mem.sub.-- we, mem.sub.-- data.sub.-- cs, mem.sub.-- vt.sub.-- cs, and mem.sub.-- vclear. The names are the same as in the normal mode signals except they starts from "mem".
1.12.2 Register file
The test scheme specified for the register file is targeted to easily access the register file in test mode. Since there is no comparator logic embedded as in IDC, it is not practical to apply MARCH type algorithm to this memory.
FIG. 7 (register file test scheme) shows the overall scheme for test environment. The dotted lines represent the normal signals. There are three regions, data path, reg.sub.-- file, and EXE block. All the logic in the left hand side of the bold line belongs to EXE block except the reg.sub.-- file block. The EXE block provides the mux logic to select the address and control signals between test and normal modes. The test mode selection signal, reg.sub.-- file.sub.-- test.sub.-- en and the three memory control signals, mem.sub.-- we1, mem.sub.-- we2, and mem.sub.-- cex are provided by the JTAG control logic. If reg.sub.-- file.sub.-- test.sub.-- en is high, test data is selected.
The addresses are generated by 6 bit counter with set, reset, up and down, and count enable. All count operation are synchronous with system clock, clk1. The input and output registers are located in data path blocks as specified in the FIG. 7. All the I/O registers need to be scanned. 32 bit ben signals are tied to logic 1 in the test mode.
Free running clock is provided to register file. Capture scan register is attached to the output of it.
1.13 MSP Boundary Scan
All the I/O pads in MSP have appropriate boundary scan cells. There are 270 boundary scan cells connected in one scan chain. The sequence and cells are listed in table 13.
1.13.1 Boundary scan cell selection
The current available JTAG cells in KGL75 are listed below. Their matching JTAG standard cells are shown in table 15. The boundary scan chain for MSP uses the LSSD type scan cells. The difference from the KGL75 is using two non overlapping clocks to shift through boundary scan chain. KGL75 boundary scan cells are used for boundary scan of ARM7.
JTBI1: Bi-directional I/O boundary scan cell.
JTCK: Special input, such as clock input, boundary scan cell
JTIN1: Input boundary scan cell
JTINT1: Three-state control internal boundary-scan cell
JTOUT1: Output boundary scan cell
The rules of selecting appropriate boundary scan cells are stated below.
For every input cell including clock inputs except GND, VDD, and VCC pins, use JTIN1.
For every bidirectional cells, use JTBI1.
For every output cells, use JTOUT1.
For t/s(tri-state) pins, add a JTINT1 cell. Use only one tri-state control cell for a group of signals such as AD31:0!.
For the pins with o/d(open drain), Use a JTINT1 cell.
For the pins with s/t/s(ststained tri-state) is same as t/s in terms of boundary scan cell selection.
1.13.2 Boundary scan cell sequence
The boundary scan is chained in the counter-clock direction from TDI input. Please refer to MSP pin layout for more information.
Input cell comes first in case of bidirectional pins.
If there is tri-state pins, the tri-state control boundary scan cell, JTINT1, comes before the cells.
If there are many tri-state pins in a sequence, only one tri-state control cell is inserted before the first tri-state pins in the sequence.
1.13.3 Design details
All ADxx signals have the same tri-state enable signals. So only one control boundary scan cell is enough to control 32 bit AD signals. However, to properly control the signals in the multiple scan mode, four more control boundary scan cells have been inserted. As a result, a total of five control boundary scan cells is used for AD bus. The five control boundary scan cells take one normal control signal from MSP core and produce five control signals.
1.14 ARM7 Boundary Scan
The boundary scan cell selection has been treated as the way in the MSP boundary scan cell selection. Refer to the previous section for more information. The names and scan order are described in the table 14.
Claims
We claim:
1. An integrated circuit comprising: one or more function blocks; an input for receiving one or more test signals for testing the integrated circuit, the one or more test signals including a test clock to scan test data in and/or out of the integrated circuit and also to clock one or more of the function blocks during testing; an input for receiving one or more normal clocks to clock one or more of the function blocks during normal operation and during testing; and a clock selection circuit for selecting either the test clock or one or more of the normal clocks to clock one or more of the function blocks; wherein the clock selection circuit comprises a counter for clocking one or more of the function blocks for a predetermined number of cycles of one or more of the normal clocks when the clock selection circuit selects one or more of the normal clocks for testing; and wherein: in normal operation, the one or more normal clocks are used to clock the one or more function blocks; in a first test operation, the test clock is used as a scan clock to scan test data in and/or out of the integrated circuit; in a second test operation, the test clock is used to provide one or more clocks for clocking one or more of the function blocks; and in a third test operation, one or more of the normal clocks are used to clock one or more of the function blocks for the predetermined number of cycles of one or more of the normal clocks.
2. The integrated circuit of claim 1 wherein the one or more test signals are JTAG boundary scan signals, the integrated circuit comprises a JTAG test data register, and the predetermined number of cycles is to be provided to the integrated circuit by being shifted into the JTAG test data register.
3. The integrated circuit of claim 1 wherein the predetermined number of cycles is to be provided to the integrated circuit through the input for receiving the one or more test signals.
4. The integrated circuit of claim 1 wherein the clock selection circuit is to select the clocks under the control of one or more of the test signals.
5. The integrated circuit of claim 1 wherein the one or more function blocks comprise a memory, and in the second test operation the test clock is used to clock the memory.
6. The integrated circuit of claim 1 further comprising one or more pins for receiving a test clock signal C1 in a fourth test operation in which the clock C1 is used to generate at least one clock which in normal operation is generated internally from one or more of the normal clocks, wherein in the normal operation the one or more pins are used for signals other than test clock signals.
7. The integrated circuit of claim 1 wherein the test signals are JTAG boundary scan signals.
8. A method for testing an integrated circuit, the method comprising: in a first test operation, the integrated circuit receiving a test clock on an input for receiving one or more test signals and using the test clock to scan test data in and/or out of the integrated circuit; in a second test operation, using the test clock to provide one or more clocks for clocking one or more of the function blocks of the integrated circuit; and in a third test operation, clocking one or more of the function blocks with one or more normal clocks which are to clock one or more function blocks in normal operation of the integrated circuit, and using a counter to continue the third test operation for a predetermined number of cycles of one or more of the normal clocks.
9. The method of claim 8 wherein the one or more test signals are JTAG boundary scan input signals, the method further comprising shifting the predetermined number of cycles into a JTAG test data register of the integrated circuit for the third test operation.
10. The method of claim 8 further comprising the integrated circuit receiving the predetermined number of cycles on the input for receiving the one or more test signals.
11. The method of claim 8 further comprising selecting a clock for clocking one or more function blocks, the selecting being controlled by one or more of the test signals.
12. The method of claim 8 wherein the one or more function blocks comprise a memory, and the second test operation comprises using the test clock for clocking the memory.
13. The method of claim 8 further comprising, in a fourth test operation, the integrated circuit receiving a test clock signal C1 on one or more pins and using the clock signal C1 to generate at least one clock which in normal operation is generated by the integrated circuit from one or more of the normal clocks, wherein in the normal operation the one or more pins are used for signals other than test clock signals.
14. The method of claim 8 wherein the test signals are JTAG boundaries scan signals.
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