Data Detection Method and Apparatus in Data Storage Device

The present invention relates to a data detection method and apparatus, and more particularly, to a data detection method and apparatus for detecting data recorded in a data storage device using a threshold value which varies according to a pattern of the recorded data.

A fast data storage device having a huge capacity for facilitating storing a great quantity of data is being studied. The general process of detecting the originally recorded data from a signal reproduced from a storage device is as follows. First of all, after high frequency noise of a reproduced analog signal r(t) passing an analog filter is removed, the signal r(t) is sampled into a digital signal r.sub.k by an analog-to-digital converter. The digital signal r.sub.k is equalized by a digital equalizer, and then, a symbol data recorded in the storage device is detected by a detector.

The data to be recorded in the storage device is generally encoded by a run-length limited (RLL) code to facilitate signal detection and timing adjustment of a sampling clock. The condition of run-length (d and k) is to limit the number of same symbols which sequentially appear in a row of recorded binary symbols, for example, +1, -1 or 0, 1. The minimum run-length (d) condition is that the same symbol should continue at least (d+1), and the maximum run-length (k) condition is that the same symbol should continue up to (k+1) at its maximum.

In the case of an optical or a magneto-optical disk storage device, due to the characteristics of recording media such as a laser and disk, the data should be encoded by the RLL code of which the minimum run-length (d) is over one or more to record the data in a higher density. In the case of a magnetic storage device such as an HDD (hard disk driver), since the nonlinear characteristic of a signal occurring in a high frequency data pattern makes the data detection difficult, the data is encoded by the RLL code of which "d" is over one or more to reduce the non-linearity of the signal.

The channel characteristic of the storage device can be generally and simply expressed into (1+D).sup.n (here, n=1, 2, . . . ) or (1-D) (1+D).sup.n (here, n=1, 2, . . . ). Here, "D" denotes 1 unit time delay. Since signal interference increases in a higher density, the channel is shown in a greater n value. In the case of a decision feedback equalizer (DFE, U.S. Pat. No. 5,132,988), an input signal is converted into a target response d.sub.k =a.sub.k, and then, data is detected by a simple threshold value detector. The DFE has merits of providing a simple detecting method and facilitating sampling clock adjustment since the data is detected every clock. However, in the case of a signal where signal interference is serious, a high frequency noise is amplified altogether in a process of equalizing into d.sub.k =a.sub.k, thus lowering detection performance. In the meantime, a partial response maximum likelihood (PRML, U.S. Pat. Nos. 4,571,734, 4,644,564) method, the input signal is converted into the target response of d.sub.k =a.sub.k +a.sub.k-1 or d.sub.k =a.sub.k -a.sub.k-2 to detect the data using a Viterbi decoder. The PRML method exhibits superior detection performance in recording density having signal interference where the channel characteristic is n=1. However, since the Viterbi decoder is used for data detection, the data detection process is fundamentally sophisticated and a clock restoring process is arduous.

To solve the above problems, it is an object of the present invention to provide a method for detecting original data in a data storage device by equalizing a reproduction signal of data encoded by a code of which the minimum run-length is over one or more to a target response of d.sub.k =a.sub.k-1 +2a.sub.k +a.sub.k+1 and detecting a threshold value.

It is another object of the present invention to provide an apparatus adopting the above data detection method.

Accordingly, to achieve the first object, there is provided a data detection method of a data storage device for detecting symbol data a.sub.k from an equalization signal z.sub.k when a digital signal r.sub.k is obtained by sampling a signal r(t) which is obtained by transmitting via a channel or recording on a recording medium a train of binary symbols a.sub.k where k is an integer, the equalization signal z.sub.k is obtained by equalizing the digital signal r.sub.k, the method comprising the steps of: (a) detecting the symbol data a.sub.k by selecting one among threshold values T›a.sub.k-1.sup.k-N ! using a previous symbol sequence a.sub.k-1.sup.k-N and comparing the equalization signal z.sub.k with the selected threshold value; (b) updating a value (1-.mu.)G›a.sub.k+1.sup.k-N !+.mu.z.sub.k, obtained by multiplying a value G›a.sub.k.multidot.1.sup.k-N ! of a RAM read using data sequence a.sub.k.multidot.1.sup.k-N as an address by a first coefficient 1-.mu. and the equalization signal z.sub.k by a second coefficient .mu., respectively, and adding both multiplied results, to a value G›a.sub.k+1.sup.k-N ! of an address a.sub.k-1.sup.k-N of the RAM; and (c) from the updated RAM value output from said step (b) and the data sequence a.sub.l+1.sup.k-N, calculating a threshold value T›a.sub.k-1.sup.k-N ! used in detecting the symbol data a.sub.k in step (a) according to an expression (1) when a.sub.k-1 =a.sub.k-2, ##EQU1## otherwise, according to an expression (2), ##EQU2## wherein "N" is an arbitrary value greater than 1 and symbol a.sub.k-1 has the inverse value of symbol a.sub.k-1.

To achieve the second object, there is provided a data detection apparatus of a data storage device for detecting symbol data a.sub.k from an equalization signal z.sub.k when a digital signal r.sub.k is obtained by sampling a signal r(t) which is obtained by transmitting via a channel or recording on a recording medium a train of binary symbols a.sub.k where k is an integer, the equalization signal z.sub.k is obtained by equalizing the digital signal r.sub.k, the apparatus comprising: RAM updating means for obtaining the average characteristic of the equalization signal z.sub.k from the symbol data a.sub.k and storing and updating the obtained result; threshold value calculation means for calculating an optimal threshold value with resect to each data pattern from the average characteristic of the equalization signal z.sub.k updated in the RAM updating means; and a detector for detecting the value of the symbol data a.sub.k by comparing the equalization signal z.sub.k with the threshold value calculated in the threshold value calculation means.

The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram illustrating a data detection apparatus according to the present invention in a data storage device;

FIG. 2 is a circuit diagram illustrating a preferred embodiment of a RAM updating means of FIG. 1 according to the present invention;

FIG. 3 is a block diagram illustrating a first embodiment of a threshold value calculation means of FIG. 1 according to the present invention;

FIG. 4 is a block diagram illustrating a second embodiment of a threshold value calculation means of FIG. 1 according to the present invention;

FIG. 5 is a block diagram illustrating a third embodiment of a threshold value calculation means of FIG. 1 according to the present invention;

FIG. 6 is a block diagram illustrating a fourth embodiment of a threshold value calculation means of FIG. 1 according to the present invention;

FIG. 7 is a block diagram illustrating a fifth embodiment of a threshold value calculation means of FIG. 1 according to the present invention;

FIG. 8 is a block diagram illustrating a first embodiment of a detector of FIG. 1 according to the present invention;

FIG. 9 is a block diagram illustrating a second embodiment of a detector of FIG. 1 according to the present invention; and

FIG. 10 is a block diagram illustrating a third embodiment of a detector of FIG. 1 according to the present invention.

FIG. 1 is a block diagram illustrating a data detection apparatus according to the present invention in a data storage device. In the drawing, the apparatus comprises an analog filter 11, an analog-to-digital converter 12, a digital equalizer 13, a RAM updating means 14, a threshold value calculating means 15 and a detector 16.

The operation of the apparatus having such a structure shown in FIG. 1 will be now described.

An analog signal r(t) reproduced from the data storage device passes the analog filter 11 during which a high frequency noise of the signal r(t) is removed. Then, the signal r(t) is sampled to an n-bit by the analog-to-digital converter 12 according to a given clock signal and output as a digital signal r.sub.k. The digital signal r.sub.k is converted to a signal z.sub.k of l-bit befitting to detect data in the digital equalizer 13. Here, the digital equalizer 13 is implemented with a linear traversal filter or the DFE. The detector 16 is for detecting a symbol a.sub.k+1 by comparing the output signal z.sub.k of digital equalizer 13 with a threshold value output from the threshold value calculating means 15. Here, an optimal threshold value in each data pattern is used for the detection to reduce an effect by the nonlinear characteristic of the signal and DC offset to detection performance. The optimal threshold value in each data pattern is obtained from the average characteristic of the signal z.sub.k. That is, the RAM updating means 14 is for obtaining the average characteristic of the signal z.sub.k from the symbol a.sub.k+1 and storing and updating the same. The threshold value calculating means 15 is for calculating the optimal threshold value with respect to each data pattern from the average characteristic of the signal z.sub.k output from the RAM updating means 14. Also, the RAM updating means 14 receives an equalization error e.sub.k of the equalization signal z.sub.k instead of equalization signal z.sub.k and a symbol data a.sub.k and update the value of RAM.

FIG. 2 is a circuit diagram showing an embodiment of the RAM updating means 14. The circuit comprises a shift register 21, a RAM 22, first and second multipliers 23 and 25, first and second registers 24 and 27 and an adder 26.

The operation according to the structure of FIG. 2 will be now described.

First, a current binary symbol a.sub.k may have a value of +1 or -1, or 1 or 0.

In FIG. 2, a RAM updating process with respect to a signal z.sub.k-1 is represented with 1 unit time delay since a future symbol a.sub.k+1 is not known in a real implementation.

The RAM 22 is for storing the average of the signal z.sub.k corresponding to a data pattern a.sub.k+1.sup.k-N =›a.sub.k+1, a.sub.k, . . . a.sub.k-N ! and the average is represented as G›a.sub.k+1.sup.k-N !. Here, N denotes the number of previous symbols, and in this case, the address size of the RAM 22 is (N+2). The method of updating the RAM 22 is shown in the following expression (1).

If a value of the previous symbol a.sub.k-1 is already given, values to be taken by three symbol sequence ›a.sub.k+1, a.sub.k, a.sub.k-1 ! have four of ›a.sub.k-1, a.sub.k-1, a.sub.k-1 !, ›a.sub.k-1 , a.sub.k-1, a.sub.k-1 !, ›a.sub.k-1 , a.sub.k-1 , a.sub.k-1 ! and ›a.sub.k-1, a.sub.k-1 , a.sub.k-1 ! Here, a.sub.k signifies the inverse value of a.sub.k. Assuming that data is encoded into a code where the minimum run-length (d) is 1 like a (1, 7) RLL code, there remain only three data sequence since the last data sequence among the above four is not available. In ›a.sub.k-1, a.sub.k-1, a.sub.k-1 ! and ›a.sub.k-1 , a.sub.k-1, a.sub.k-1 !, the a.sub.k is the same as a.sub.k-1, and in ›a.sub.k-1 , a.sub.k-1 , a.sub.k-1 !, the a.sub.k is the same as a.sub.k-1 . Here, considering a signal value by each sequence, a decision boundary for deciding a value of a current symbol a.sub.k to a.sub.k =a.sub.k-1 or a.sub.k =a.sub.k-1 is decided by a signal value of ›a.sub.k-1 , a.sub.k-1, a.sub.k-1 ! and ›a.sub.k-1 , a.sub.k-1 , a.sub.k-1 !.

In the meantime, the detailed operation of each components cf are PAM updating means 14 shown in FIG. 2 will now be described.

The shift register 21 is for receiving the symbol a.sub.k output from the detector 16 of FIG. 1 and outputting data a.sub.k.sup.k-N-1 of (N+2) bits.

The RAM 22 having a capacity of 2.sup.N+2 is for writing an output of the second register 27 using data a.sub.k-1.sup.k-N-2 output from the shift register 21 as a writing address and outputting G›a.sub.k.sup.k-N-1 ! using the a.sub.k.sup.k-N-1 as a reading-out address.

The first multiplier 23 is for receiving the output G›a.sub.k.sup.k-N-1 ! of the RAM 22 and outputting an (l+m) bits signal by multiplying the input value by a predetermined coefficient (1-.mu.). Simultaneously, the first register 24 is for receiving the output signal z.sub.k of the digital equalizer 13 of FIG. 1 and outputting a one-clock delayed signal z.sub.k-1.

The second multiplier 25 is for receiving the output of z.sub.k-1 of the first register 24 and outputting an (l+m) bits signal by multiplying the input value by a predetermined coefficient .mu..

The adder 26 is for adding the output of the first multiplier 23 and the output of the second multiplier 25 and outputting an l-bit signal.

The second register 27 is for receiving the output of the adder 26 and outputting a one-clock delayed signal G›a.sub.k-1.sup.k-N-2 !.

FIG. 3 is a block diagram of a first embodiment of the threshold value calculating means 15 of FIG. 1. In the simplest case of N=1, the following expression (2) is to obtain an optimal threshold value T›a.sub.k-1 !. ##EQU3##

Meanwhile, the detailed operation of each component of the first embodiment of the threshold value calculating means 15 will now be described as shown in FIG. 3.

An adder 31 is for adding ›a.sub.k-1 , a.sub.k-1, a.sub.k-1 ! and ›a.sub.k-1 , a.sub.k-1 , a.sub.k-1 ! both being output from the RAM 22 of FIG. 2 in the RAM updating means 14 of FIG. 1 and outputting the result value.

A divider 32 is for dividing the output of the adder 31 by 2 and outputting the result value.

FIGS. 4 to 7 are circuit diagrams according to a second to fifth embodiments of the threshold value calculating means 15 of FIG. 1. When N is greater than 1, the following expressions (3) and (4) are provided since a data pattern of an input address of the RAM 22 of FIG. 2 should have a minimum run-length d=1. ##EQU4## In case of data sequence a.sub.k-1.sup.k-N which does not satisfy the condition d=1, the value of the RAM is always "0," and accordingly, the threshold value always becomes "0."

The detailed operation of each component of the second embodiment of the threshold value calculating means 15 shown in FIG. 4 is as follows.

An AND gate 41 is for comparing the symbol a.sub.k-1 with another symbol a.sub.k-2 and outputting the result.

A multiplexer 42 is for selectively outputting one sequence a.sub.r from (N+2) bit symbol sequence ›a.sub.k-1 ,a.sub.k-1 , a.sub.k-1.sup.k-N ! and another (N+2) bit symbol sequence ›a.sub.k-1 , a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N+1 ! according to the output of the AND gate 41.

An adder 44 is for adding a value G›a.sub.r ! read from the RAM 22 of FIG. 2 using the output of multiplexer 42 as an address and a value G›a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N ! read from another RAM 22 of FIG. 2 and outputting the result.

A divider 44 is for dividing the output of the adder 43 by 2 and outputting the result.

Next, the detailed operation of each component of the third embodiment of the threshold value calculating means 15 as shown in FIG. 5 will now be described.

An AND gate 51 is for comparing the symbol a.sub.k-1 with another symbol a.sub.k-2 and outputting the result.

A multiplexer 52 is for selectively outputting one of an l-bit output G›a.sub.k-1 , a.sub.k-1 , a.sub.k-1.sup.k-N ! and another l-bit output G›a.sub.k-1 , a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N+1 ! of the RAM 22 of FIG. 2 according to the output of the AND gate 51.

An adder 53 is for adding the output of the multiplexer 52 and a value G›a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N ! read from the RAM 22 of FIG. 2 and outputting the result value.

A divider 54 is for dividing the output of the adder 53 by 2 and outputting the result value.

The detailed operation of each component of the fourth embodiment of the threshold value calculating means 15 as shown in FIG. 6 will now be described.

An AND gate 61 is for comparing the symbol a.sub.k-1 with another symbol a.sub.k-2 and outputting the result.

A first adder 62 is for adding l-bit output G›a.sub.k-1 , a.sub.k-1 , a.sub.k-1.sup.k-N ! and another l-bit output G›a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N ! of the RAM 22 of FIG. 2 and outputting the result.

A second adder 63 is for adding the l-bit output G›a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N ! and another l-bit output G›a.sub.k-1 , a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N+1 ! of the RAM 22 of FIG. 2 and outputting the result.

A multiplexer 64 is for selectively outputting one of the output of the first adder 62 and the output of the second adder 63 according to the output of the AND gate 61.

A divider 65 is for dividing the output of the multiplexer 64 by 2 and outputting the result value.

The detailed operation of each component of the fifth embodiment of the threshold value calculating means 15 as shown in FIG. 7 will now be described.

An AND gate 71 is for comparing the symbol a.sub.k-1 with another symbol a.sub.k-2 and outputting the result.

A first adder 72 is for adding l-bit output G›a.sub.k-1 , a.sub.k-1 , a.sub.k-1.sup.k-N ! and another l-bit output G›a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N ! of the RAM 22 of FIG. 2 and outputting the result.

A first divider 74 is for dividing the output of the first adder 72 by 2 and outputting the result.

A second adder 73 is for adding the l-bit output G›a.sub.k-1, a.sub.k-1, a.sub.k-1.sup.k-N ! and another l-bit output G›a.sub.k-1 , a.sub.k-1 , a.sub.k-1, a.sub.k-1.sup.k-N+1 ! of the RAM 22 of FIG. 2 and outputting the result.

A second divider 75 is for dividing the output of the second adder 73 by 2 and outputting the result value.

A multiplexer 76 is for selectively outputting one of the output of the first divider 74 and the output of the second divider 75 according to the output of the AND gate 71.

FIGS. 8 to 10 are circuit diagrams according to the first to third embodiments of the detector 16 of FIG. 1. In a state where data (a.sub.k-1, a.sub.k-2, . . . ) has already been detected, the symbol a.sub.k is obtained from the signal z.sub.k by the following expression (5).

First, the detailed operation of each component of the first embodiment of the detector 16 as shown in FIG. 8 is as follows.

A RAM 81 having capacity of 2.sup.L .times.2.sup.N is for outputting T›a.sub.k-1.sup.k-N ! using as a reading address an L bit value with respect to a disk track position output from a servo controller (not shown) and the N bit data ›a.sub.k-1.sup.k-N !.

A comparator 82 is for comparing the output signal z.sub.k of the digital equalizer 13 of FIG. 1 with the output T›a.sub.k-1.sup.k-N ! of the RAM 81 and outputting the result.

Next, the detailed operation of each component of the second embodiment of the detector 16 as shown in FIG. 9 will now be described.

A multiplexer 91 is for selectively outputting any one among all the threshold values calculated in the threshold value calculating means 15 of FIG. 1 using data sequence ›a.sub.k-1.sup.k-N !.

A comparator 92 is for comparing the output signal z.sub.k of the digital equalizer 13 of FIG. 1 with the output of the multiplexer 91 and outputting the result.

The detailed operation of each component of the third embodiment of the detector 16 as shown in FIG. 10 will now be described.

A first comparator 101 is for comparing the output signal z.sub.k of the digital equalizer 13 of FIG. 1 with threshold value T›1 . . . 1! and outputting the result.

Comparators 102 of 2.sup.N -1 units is for comparing the output signal z.sub.k of the digital equalizer 13 of FIG. 1 with threshold value T›0 . . . 0! and outputting the result.

A multiplexer 103 is for selectively outputting any one among signals output from 2.sup.N unit comparators 101 and 102 using ›a.sub.k-1.sup.k-N !.

As described above, in the data detection method and apparatus according to the present invention in a data storage device, a signal is detected by obtaining an average characteristic of a signal according to a data pattern and then using an optimal threshold value to detect the signal. Thus, a signal having considerable non-linear distortion and a DC offset can be detected with trust. Here, since the threshold value is obtained considering from an arbitrary N-unit time previous symbol and to current and 1 unit time future symbol, the threshold value is very effective in detecting a signal of considerable non-linear distortion. Also, the threshold value can be adaptively updated, an optimal value can be maintained though the characteristic of a reproduction signal gradually varies according to time.

Further, in the present invention, not only data can be detected with fidelity in a high density compared with the conventional DFE method equalizing the input signal to the target response d.sub.k =a.sub.k, but also the restoration of the sampling clock is easier than that in the PRML method due to the DFE structure.