US 5,805,019 AGrant
Voltage Gain Amplifier for Converting a Single Input to a Differential Output
Issue Date:1998-09-08
•13 Claims
•4 Drawing Sheets
Abstract
The present invention relates to a voltage gain amplifier for converting a single analog input to a differential output and controlling a voltage gain, comprising a single input charging/discharging part, a differential output operational amplifier, a first and second input voltage transferring part, a first and second voltage holding part and a frequency compensating part, and therefore, making it possible to generate a differential input signal, which is used as an input to an ADC(Analog-to-Digital Converter) of an audio CODEC(Coder/Decoder), by using a fully-differential output operational amplifier whose output is transmitted as a differential output. Also, the present invention gives an advantage of making the chip size smaller than the prior art does, resulting from the fact that resistors are replaced by capacitors and switches when integrated into a chip.
Metadata
Assignee
- Hyundai Electronics Industries Co., Ltd.
Inventor
- Yun Tae Shin
Application Information
Application Number:US 7187165
Filing Date:1996-09-24
Priority Date:1996-09-24
Art Unit:255
Classifications
IPC:
H03F 345
Field of Search:
3309;51;86;260;275;282;301
Patent Drawings (4 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a voltage gain amplifier, which consists of analog switches, capacitors and a fully-differential amplifier, used for converting a single analog input to a differential output and controlling a voltage gain.
2. Description of the Prior Art
An Analog-to-Digital Converter(referred to hereinafter as ADC), which adopts an oversampling method in order to support Multimedia Audio and Coder/Decoder(referred to hereinafter as CODEC), uses a sigma-delta modulator that receives an analog signal as an input. The sigma-delta modulator needs a voltage gain amplifier for improving the signal-to-noise ratio and a differential input for improving the dynamic range and power supply rejection ratio.
FIG. 1 shows the schematic structure of a conventional voltage gain amplifier for processing an analog signal. FIG. 2 shows the structure of a conventional programmable voltage gain amplifier. FIG. 3 shows the structure of a conventional voltage gain amplifier for converting an analog signal to a differential output, in which A denotes am operational amplifier, R, R.sub.1 to R.sub.2.spsb.N.sub.+1 denote a registor and S.sub.1 to S.sub.2.spsb.N denote a switch, respectively.
Referring to FIG. 1, the input voltage V.sub.in is inputted to an inversion input part of the operational amplifier A by way of the impedance Z.sub.1, output voltage V.sub.out is fed back to the inversion input part of the operational amplifier A by way of the impedance Z.sub.2, and the non-inversion input part is grounded.
Supposing that impedances Z.sub.1, Z.sub.2 are resisstors R.sub.1, R.sub.2, respectively, and R.sub.1 is smaller than R.sub.2, a voltage gain is: ##EQU1##
That is, the output voltage is amplified by R.sub.2 /R.sub.1 times of the input voltage with an inverse polarity of the input voltage.
Referring to FIG. 2, signals S.sub.1 .about.S.sub.2.spsb.N decoded by the N-bit decoder are used for selecting the switches of the voltage gain amplifier in order to output the desired voltage gain.
However, as this kind of a voltage gain amplifier can not be used as a differential input for a sigma-delta modulator, an inversion amplifier with a voltage gain of 1 is further required, as shown in FIG. 3. Therefore, the prior art has the drawbacks of a large chip size and a difficulty in integrating resistors on the chip.
Summary of the Invention
It is an object of the present invention to provide a voltage gain amplifier for converting a single input to a differential output by discharging a charged voltage in a capacitor with an inverted polarity and a non-inverted polarity, which uses a fully-differential amplifier instead of a single-output inversion amplifier and also uses switches and capacitors instead of resistors, in order to improve the integration density.
In accordance with one aspect of the present invention, a voltage gain amplifier for converting a single input to a differential output includes:
a fully-differential output operational amplifying means, which has an inversion input terminal, a non-inversion input terminal, an inversion output terminal and a non-inversion output terminal, for amplifying the two inputted signals and then outputting the two amplified signals to a first output terminal and a second output terminal, respectively, the phase of the one output signal being opposite to the phase of the other output signal;
a first single input charging/discharging means, connected to said inversion input terminal of said fully-differential output operational amplifying means, for charging/discharging the input voltage V.sub.in ;
a second single input charging/discharging means for providing a signal whose phase is inversed compared with the phase of the signal provided by said first single input charging/discharging means, connected to said non-inversion input terminal of said fully-differential output operational amplifying means;
a first input voltage transferring means, of which one end is connected to said inversion input terminal of said fully-differential output operational amplifying means and the other end is connected to said first output terminal, respectively, for transferring the input voltage by a switching operation;
a second input voltage transferring means, of which one end is connected to said non-inversion input terminal of said fully-differential output operational amplifying means and the other end is connected to said second output terminal, respectively, for transferring the input voltage by a switching operation; and
a frequency compensating means for outputting a first and second output voltage after compensating frequency such that the output signals of said fully-differential output operational amplifying means can be stably operated within a given bandwidth.
Brief Description of the Attached Drawings
FIG. 1 shows a schematic diagram of a conventional voltage gain amplifier for an analog signal;
FIG. 2 shows a schematic diagram of a conventional programmable voltage gain amplifier;
FIG. 3 shows a schematic diagram of a conventional voltage gain amplifier for converting a single input to a differential output;
FIG. 4 shows a circuit diagram of the voltage gain amplifier in accordance with one embodiment of the present invention; and
FIG. 5 shows a circuit diagram of the voltage gain amplifier in accordance with another embodiment of the present invention.
Detailed Description of the Preferred Embodiment
Referring to the attached drawings, the preferred embodiment of the present invention will be fully explained. FIG. 4 and FIG. 5 show the circuit diagram of the voltage gain amplifier in accordance with one embodiment and another embodiment of the present invention, wherein 1 denotes the fully-differential output operational amplifier, 2 denotes the single input charging/discharging part, 3 and 3' denote the input voltage transferring part, 4 and 4' denote the voltage holding part, and 5 denotes the frequency compensating part, respectively.
As shown in FIG. 4, the single input charging/discharging part 2 consists of a first and second charging/discharging part which can charge/discharge the single input voltage V.sub.in by means of the switching operation such that the phase of the output signal of said first charging/discharging part is opposite to the phase of the output signal of said second charging/discharging part but the amplitude of the two output signals is equal.
The fully-differential output operational amplifier 1 amplifies the amplitude of the fully-differential mode signals tramsmitted from an inversion and non-inversion input terminal, and then outputs the amplified signals whose phase is opposite each other to a first and second output terminal.
The input voltage transferring part 3, 3', connected to each input and output terminal of said fully-differential output operational amplifier 1, transfers an input voltage by a switching operation.
The voltage holding means 4, 4', connected to both ends of said input voltage transferring part 3, 3', decrease a high-frequency noise.
The frequency compensating part 5 outputs a first and second output voltage after compensating frequency such that the output signals of said fully-differential output operational amplifying means can be stably operated within a given bandwidth.
Referring to FIG. 4, the first charging/discharging part of said single input charging/discharging part 2 includes the switch S.sub.11 for switching the input voltage V.sub.in, the sampling capacitor C.sub.S+ of which one end is connected to said switch S.sub.11, the switch S.sub.21 connected between the other end of said sampling capacitor C.sub.S+ and the inversion input terminal of said fully-differential output operational amplifier 1, the switch S.sub.22 connected between one end of said sampling capacitor C.sub.S+ and the ground, and the switch S.sub.12 connected between one end of said sampling capacitor C.sub.S+ and the ground.
Also, the second charging/discharging part of said single input ch7/arging/discharging part 2 includes the switch S.sub.13 for switching the input voltage V.sub.in, the switch S.sub.23 connected between said switch S.sub.13 and the non-inversion input terminal of said fully-differential output operational amplifier 1, the sampling capacitor C.sub.S- connected between said switches S.sub.13 and S.sub.23, and switches S.sub.14, S.sub.24 connected in parallel between the sampling capacitor C.sub.S- and the ground.
Said input voltage transferring part 3 consists of the switch S.sub.25 connected to the inversion input terminal of said fully-differential output operational amplifier 1, the capacitor C.sub.H+ connected to said switch S.sub.25, the switch S.sub.26 connected between said capacitor C.sub.H+ and the first output terminal, and the switches S.sub.15, S.sub.16 connected between both ends of said capacitor C.sub.H+ and the ground.
Meanwhile, said input voltage transferring part 3' consists of the switch S.sub.27 connected to the non-inversion input terminal of said fully-differential output operational amplifier 1, the capacitor C.sub.H- connected to said switch S.sub.27, the switch S.sub.28 connected between said capacitor C.sub.H- and the second output terminal, and switches S.sub.17, S.sub.18 connected between both ends of said capacitor C.sub.H- and the ground.
The voltage holding part 4 has the capacitor C.sub.F+ whose one end is connected between the inversion input part of said fully-differential output operational amplifier 1 and said switch S.sub.25 and the other end is connected between the first output terminal of said fully-differential output operational amplifier 1 and said switch S.sub.26.
Also, the voltage holding part 4' has the capacitor C.sub.F- whose one end is connected between the non-inversion input part of said fully-differential output operational amplifier 1 and said switch S.sub.27 and the other end is connected between the second output terminal of said fully-differential output operational amplifier 1 and said switch S.sub.28.
The frequency compensating part 5 includes the capacitor C.sub.C+ connected between the first output terminal and the ground, and the capacitor C.sub.C- connected between the second output terminal and the ground.
Meanwhile, a plurality of switches S.sub.11 .about.S.sub.18, S.sub.21 .about.S.sub.28 are a transmission gate or an NMOS transistor and have a switching operation that in case said switches S.sub.11 .about.S.sub.18 are `on`, said switches S.sub.21 .about.S.sub.28 are `off` by means of the clock which applies to the gate, and on the contrary, in case said switches S.sub.11 .about.S.sub.18 are `off`, said switches S.sub.21 .about.S.sub.28 are `on`. However, the clock frequency f.sub.C is the same.
When said switches S.sub.11 .about.S.sub.14 of the single input charging/discharging part 2 become `on`, the input voltage V.sub.in minus the ground voltage V.sub.ref is charged in said sampling capacitors C.sub.S+ and C.sub.S-, and at the same time, a potential difference between both ends of said capacitors C.sub.H+, C.sub.H- of the input voltage transferring part 3, 3' is 0 voltage.
Meanwhile, when said switches S.sub.11 .about.S.sub.14 of the single input charging/discharging part 2 become `off` and said switches S.sub.21 .about.S.sub.24 of the single input charging/discharging part 2 become `on`, voltage V.sub.in -V.sub.ref, which was charged in said sampling capacitors C.sub.S+ and C.sub.S-, is applied to said inversion and non-inversion input terminal of the fully-differential output operational amplifier 1.
At this time, the two input terminal voltages have a different electric polarity from each other, and are discharged into said capacitors C.sub.H+ and C.sub.H- of the input voltage transferring parts 3, 3'.
Thus, the ratio of the output voltage to the input voltage is: ##EQU2##
Thus, the output voltage is amplified in case C.sub.S+ is greater than C.sub.H+. In the meantime, C.sub.H+ is equal to C.sub.H-, and C.sub.S+ is equal to C.sub.S-.
However, the output signal has high-frequency noises. These high-frequency noises can be eliminated by said capacitors C.sub.F+, C.sub.F- of the voltage holding parts 4, 4' of which the cutoff-frequency, respectively, is: ##EQU3##
In the meantime, said capacitors C.sub.C+ and C.sub.C- of the frequency compensating part 5 enable said fully-differential output operational amplifier 1 to operate stably within a given bandwidth.
Based on FIG. 4, FIG. 5 shows the circuit diagram of the voltage gain amplifier, wherein the voltage gain varies from 0 dB to +22.5 dB with an interval +1.5 dB. That is, 16 different voltage gains are obtained by turning `on` and `off` switches with the help of the switch control signal to which the 4-bit digital signal is decoded by the decoder.
As shown in FIG. 5, said single input charging/discharging part 2 is composed of 4 first charging/discharging parts whose inter-connection is parallel and 4 second charging/discharging parts whose inter-connection is also parallel. Also, said input voltage transferring parts 3, 3' have a 4-stage parallel connection, respectively.
Meanwhile, said capacitors C.sub.1H, C.sub.2H, C.sub.3H, C.sub.4H, C.sub.1S, C.sub.2S, C.sub.3S, and C.sub.4S have the following relation:
C.sub.1H =C.sub.2H
C.sub.3H =2 C.sub.1H
C.sub.4H =4 C.sub.1H
C.sub.1S =C.sub.1H +C.sub.2H +C.sub.3H +C.sub.4H =8 C.sub.1H
C.sub.2S =0.1885.multidot.C.sub.1S
C.sub.3S =0.22404.multidot.C.sub.1S
C.sub.4S =0.26626.multidot.C.sub.1S
As shown in FIG. 4, the clock signal generated by decoding the 4-bit digital signal enables each switch to become turned `on` or `off`.
For example, said switches 1S.sub.11 .about.1S.sub.14, 1S.sub.21 .about.1S.sub.24, 1S.sub.15 .about.1S.sub.18, 1S.sub.25 .about.1S.sub.28, 2S.sub.15 .about.2S.sub.18, 2S.sub.25 .about.2S.sub.28, 3S.sub.15 .about.3S.sub.18, 3S.sub.25 .about.3S.sub.28, 4S.sub.15 .about.4S.sub.18, and 4S.sub.25 .about.4S.sub.28 become turned `on` or `off` in order to obtain a gain of 0 dB. Said switches 1S.sub.11 .about.1S.sub.14, 1S.sub.15 .about.1S.sub.18, 2S.sub.15 .about.2S.sub.18, 3S.sub.15 .about.3S.sub.18, and 4S.sub.15 .about.4S.sub.18 are operated by a clock signal whose phase is opposite to the phase of the clock signal which controls said switches 1S.sub.21 .about.1S.sub.24, 1S.sub.25 .about.1S.sub.28, 2S.sub.25 .about.2S.sub.28, 3S.sub.25 .about.3S.sub.28, and 4S.sub.25 .about.4S.sub.28.
NS.sub.cn is a general expression for said switches, wherein N denotes the stage number, c denotes a clock phase, and n denotes the switch number.
Hence, a fully-differential output voltage gain is: ##EQU4##
Using the clock signal which is manipulated in the above-mentioned method, a voltage gain can be obtained according to the following chart:
As described above, the present invention makes it possible to generate a differential input signal, which is used as an input to an ADC of an audio CODEC, by using a fully-differential output operational amplifier whose output is transmitted as a differential output.
Also, the present invention gives an advantage of making a chip size smaller than the prior art does, resulting from the fact that resistors are replaced by capacitors and switches while integrating.
Claims
What is claimed:
1. A voltage gain amplifier for converting a single input to a differential output, comprising: a fully-differential output operational amplifying means, which has an inversion input terminal, a non-inversion input terminal, an inversion output terminal and a non-inversion output terminal, for amplifying two inputted signals and then outputting the two amplified signals to the inversion output terminal and the non-inversion output terminal, respectively, a phase of the one output signal being opposite to a phase of the other output signal; a first single input charging/discharging means connected to said inversion input terminal of said fully-differential output operational amplifying means, for charging/discharging an input voltage as a first signal; a second single input charging/discharging means for providing a second signal whose phase is inversed compared with a phase of the first signal provided by said first single input charging/discharging means, connected to said non-inversion input terminal of said fully-differential output operational amplifying means; a first input voltage transferring means, of which one end is connected to said inversion input terminal of said fully-differential output operational amplifying means and the other end is connected to said inversion output terminal, for transferring the first signal by a switching operation; a second input voltage transferring means, of which one end is connected to said non-inversion input terminal of said fully-differential output operational amplifying means and the other end is connected to said non-inversion output terminal, for transferring the second signal by a switching operation; and a frequency compensating means for outputting the amplified first and second signals of said fully-differential output operational amplifying means which can be stably operated within a given bandwidth.
2. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 1, further comprising a first and second voltage holding means, one end of the first voltage holding means being connected to said inversion input terminal of said fully-differential output operational amplifying means and the other end of the first voltage holding means being connected to said inversion output terminal, one end of the second holding means being connected to said non-inversion input terminal, the other end of the second holding means being connected to said non-inversion output terminal, for decreasing high-frequency noise.
3. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 2, wherein said first voltage holding means comprises a fifth capacitor connected between the inversion input terminal and the inversion output terminal of said fully-differential output operational amplifying means.
4. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 2, wherein said second voltage holding means comprises a sixth capacitor connected between the non-inversion input terminal and the non-inversion output terminal of said fully-differential output operational amplifying means.
5. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 1, wherein said first single input charging/discharging means comprises: a first switch for switching the input voltage; a first sampling capacitor of which one end is connected to said first switch; a second switch connected between the other end of said first sampling capacitor and an inversion input terminal of said fully-differential output operational amplifying means; a third switch connected between one end of said first sampling capacitor and the ground; and a fourth switch connected between the other end of said first sampling capacitor and the ground.
6. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 5, wherein said second single input charging/discharging means comprises: a fifth switch for switching the input voltage; a sixth switch connected between said fifth switch and a non-inversion input terminal of said fully-differential output operational amplifying means; a second sampling capacitor of which one end being connected between said fifth switch and said sixth switch; and a seventh switch and an eighth switch connected in parallel between the other end of said second sampling capacitor and the ground.
7. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 6, wherein said first input voltage transferring means comprises; a ninth switch connected to the inversion input terminal of said fully-differential output operational amplifying means; a third capacitor, one end of which connected to said ninth switch; a tenth switch connected between the other end of said third capacitor and the inversion output terminal; and an eleventh switch and a twelfth switch each connected between respective end of said third capacitor and the ground.
8. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 7, wherein the first switch, the fourth switch, the fifth switch, the eighth switch, the eleventh switch and the twelfth switch are operated by a clock signal whose phase is opposite to the phase of a clock signal which controls the second switch, the third switch, the sixth switch, the seventh switch, the ninth switch and the tenth switch.
9. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 6, wherein said second input voltage transferring means comprises; a thirteenth switch connected to the non-inversion input terminal of said fully-differential output operational amplifying means; a fourth capacitor, one end of which connected to said thirteenth switch; a fourteenth switch connected between the other end of said fourth capacitor and the non-inversion output terminal; and a fifteenth switch and a sixteenth switch each connected between respective end of said fourth capacitor and the ground.
10. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 9, wherein the first switch, the fourth switch, the fifth switch, the eighth switch, the fifteenth switch and the sixteenth switch are operated by a clock signal whose phase is opposite to the phase of a clock signal which controls the second switch, the third switch, the sixth switch, the seventh switch, the thirteenth switch and the fourteenth switch.
11. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 1, wherein said frequency compensating means comprises: a seventh capacitor connected between the inversion output terminal and the ground; and an eighth capacitor connected between the non-inversion output terminal and the ground.
12. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 1, wherein said first and second single input charging/discharging means are composed of a plurality of charging/discharging parts connected in parallel, respectively, and said first and second input voltage transferring means also have a plurality of input voltage transferring means whose inter-connection is parallel, respectively.
13. A voltage gain amplifier for converting a single input to a differential output as claimed in claim 12, wherein said first and second single input charging/discharging means and said first and second input voltage transferring means have a 4-stage parallel connection, capacitors have the following relations: the capacitance of a first-stage capacitor of said first and second input voltage transferring means is the same as the capacitance of a second-stage capacitor of said first and second input voltage transferring means; the capacitance of a third-stage capacitor of said first and second input voltage transferring means is two times the capacitance of the first-stage capacitor of said first and second input voltage transferring means; the capacitance of a fourth-stage capacitor of said first and second input voltage transferring means is four times the capacitance of the first-stage capacitor of said first and second input voltage transferring means; the capacitance of a first-stage capacitor of said first and second single input charging/discharging means is eight times the capacitance of the first-stage capacitor of said first and second input voltage transferring means; the capacitance of a second-stage capacitor of said first and second single input charging/discharging means is 0.1885 times the capacitance of the first-stage capacitor of said first and second single input charging/discharging means; the capacitance of a third-stage capacitor of said first and second single input charging/discharging means is 0.22404 times the capacitance of the first-stage capacitor of said first and second single input charging/discharging means; and the capacitance of a fourth-stage capacitor of said first and second single input charging/discharging means is 0.26626 times the capacitance of the first-stage capacitor of said first and second single input charging/discharging means.
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