US 5,801,557 AGrant
High Voltage Drivers Which Avoid -V.sub.s Failure Modes
Issue Date:1998-09-01
•7 Claims
•2 Drawing Sheets
Abstract
In a level shifted high voltage MOSgate device driver which drives MOSgate devices such as IGBTs and power MOSFETs, effects of negative voltage swings caused by currents commutating through L.sub.S1 and L.sub.S2 inductances in the power circuits are avoided due to several measures. First, the values of the inductances L.sub.S1 and L.sub.S2 are reduced by keeping short conductor lengths, by other layout/wire bonding techniques to reduce the values of the L.sub.S1 and L.sub.S2 inductances. The external, charging capacitor C.sub.b value is increased substantially to reduce the voltage buildup on the internal circuitry. A typical value is 0.47 .mu.F, for a given circuit, IGBT and layout combination. The size of the C.sub.VCC capacitor is selected to keep the supply voltage as stiff as possible. Preferably, C.sub.VCC is at about ten times the value of the sum of the C.sub.b capacitance in the circuit. The resistance R.sub.b in the bootstrap path is reduced as much as possible, preferably to zero. Finally, a resistor R.sub.COM is optionally added between the common nodes of the driver circuit and the power device circuit.
Metadata
Assignee
- International Rectifier Corp.
Inventors
- Ajit Dubhashi
- Leon Aftandilian
Application Information
Application Number:US 7283091
Filing Date:1996-10-09
Priority Date:1996-10-09
Art Unit:254
Classifications
IPC:
H03B 100
Field of Search:
327108;110;374;382;565-6;482
Patent Drawings (2 sheets)
Description
Related Applications
This application claims the benefit of U.S. Provisional application Ser. No. 60/004,981 filed on Oct. 10, 1995.
Background of the Invention
The present invention relates to level shifted high voltage MOSgate device drivers and, more particularly, to MOSgated device drivers with improved immunity to deleterious effects of commutating currents.
Level shifted high voltage MOSgated device drivers are well known for the drive of bridge connected MOSgated devices, such as IGBTs and power MOSFETs. A family of such devices are sold under the type numbers IR21XX, which are high voltage integrated circuit (HVIC) devices, which each drive two such MOSgated devices per leg of a bridge. FIGS. 1 and 2 show typical configurations for an IR21XX driver (for example, an IR2155) for high side and low side IGBTs 10 and 11 respectively, which are associated with fast recovery diodes 12 and 13, respectively. The H.sub.O and L.sub.O outputs at pins 4 and 2, respectively, turn devices 10 and 11 sequentially on and off to control power flow to the output circuit (not shown).
In operation, when the top device 10 is turned off, the current I.sub.10 commutates to the bottom diode 13, as I.sub.13, as shown in FIG. 3. The current I.sub.13 flows through the inherent inductances L.sub.S1 and L.sub.S2 in series with diode 13, causing the voltage at V.sub.O to go to -V.sub.e. This negative voltage can cause the driver IC 20 to malfunction or blow-up. This problem is even more intense under short circuit conditions.
Summary of the Invention
Accordingly, it is an object of the present invention to provide level shifted high voltage MoSgated device drivers that are built to withstand the deleterious effects of commutating currents.
The foregoing and other objects of the invention are realized by constructing the device such that the internal inherent inductances L.sub.S1 and L.sub.S2 have lower values, which is attained by keeping shorter conductor lengths and positioning the D.sub.b and common (COM) connection in a manner which reduces the inductance path. Furthermore, the device's C.sub.b capacitance is increased in order to reduce the voltage developing on this capacitor. Further expedients involve increasing the size of the C.sub.VCC capacitor to hold the C.sub.VCC voltage as stiff as possible, to ensure that the internal IC diode D.sub.S cannot turn on earlier. Very approximately, the capacitance C.sub.VCC should have a value ten times the total of all C.sub.b capacitors in the system.
The invention further attains its objectives by reducing the resistance R.sub.b and the bootstrap path as much as possible, to cause reduced current flow through the substrate diode. Finally, the invention contemplates providing a resistor R.sub.COM to increase the resistance in the path of the substrate diode D.sub.S and to reduce the charging of C.sub.VCC and the substrate current.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
Brief Description of the Drawings
FIG. 1 is a schematic of a prior art circuit showing a driver IC connected to drive a pair of high voltage devices;
FIG. 2 is a circuit schematic illustrating the operation of the circuit of FIG. 1;
FIG. 3 is a schematic showing the path of the commutating current when the top transistor device is turned off;
FIG. 4 illustrates an embodiment of the present invention;
FIG. 5 is a circuit showing another feature of the present invention;
FIG. 6 is a plot of the capacitor voltage at different capacitance values, to show the reduced peak voltage on the capacitor at higher capacitance values.
Detailed Description of the Invention
To better describe the problem solved by the instant invention, reference is made to FIG. 4 which shows the relevant circuit components and the significant parasitic components. The circuit components include bootstrap diode D.sub.b (22) and a capacitor C.sub.VCC (26). Also shown is the parasitic substrate diode D.sub.S (24) of the IC and the input C.sub.VCC capacitor (26). There are two modes of failure when V.sub.O goes to -V.sub.e.
In the first, the bootstrap diode D.sub.b (22) of FIG. 4 starts to conduct and charges capacitor C.sub.b (28). If the voltage on capacitor C.sub.b (28) exceeds the avalanche rating at the top driver (shown as a zener diode 30), then it destroys the IC 20. In the second mode, the bootstrap capacitor C.sub.b (28) can also charge up through the parasitic IC substrate diode D.sub.S (24). If significant current flows through diode D.sub.S (24), the IC can malfunction, be damaged or destroyed.
In the prior art, not enough attention has been paid to the component layout which causes the L.sub.S1 and L.sub.S2 inductors to increase. Moreover, the C.sub.b capacitor has been sized to hold up the driver voltage for the maximum pulse ON time and not for reducing the voltage buildup.
Prior art solutions to these problems have included adding a current limiting resistance to the bootstrap path and adding resistors, such as resistor 32 and high voltage diodes, such as diode 34 (FIG. 5) to limit the amount of -V.sub.e. This, however, causes a gate voltage spikes and requires additional high voltage diodes.
In accordance with the present invention:
(a) The values of inductance L.sub.S1 and L.sub.S2 are reduced by keeping short conductor lengths and by positioning the V.sub.e connection 38 and "com" connection 36 in FIG. 4 to reduce the inductance path;
(b) The capacitor C.sub.b (28) value increased to cause the capacitance voltage to rise to a reduced value, as shown in FIG. 6. For a size 3 IGBT die (available from International Rectifier Corporation of El Segundo, Calif.), and laying out the parts on an IMS substrate, a capacitance of 0.47 .mu.F is preferably used;
(c) The size of the C.sub.VCC capacitor 26 is increased to hold the V.sub.CC supply (FIG. 4) as "stiff" as possible since, if there are dips in the V.sub.CC voltage during bootstrap charging, the internal IC diode D. (24) can turn on earlier. Preferably, capacitor C.sub.VCC (26) should have a value of ten times the total of all C.sub.b capacitors in the system;
(d) The resistance R.sub.b (40) in the bootstrap path is reduced as much as possible. Resistor R.sub.b (40) limits the charging of capacitor C.sub.b (28) which causes increased current flow through the parasitic substrate diode, which can cause a malfunction. The recommended resistor value is 0 ohms;
(e) A resistor R.sub.COM (42) can be added in line 41 in FIG. 4 to increase the resistance in the path of substrate diode D.sub.S (24). Resistor R.sub.COM (42) also reduces the charging of capacitor C.sub.b (26) and the substrate current.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims
What is claimed is:
1. A driving circuit for high power devices, the circuit comprising: a MOSgate driver and a power switching circuit, the power switching circuit including a first MOSgate transistor and a second MOSgate transistor, the MOSgate driver being connected to and serving to alternately turn on the first and second MOSgate transistors; the power switching circuit having a voltage output node between the first MOSgate transistor and the second MOSgate transistor, and the second MOSgate transistor having associated therewith a recovery diode and inherent inductances L.sub.S1 and L.sub.S2 ; the MOSgate driver comprising an integrated circuit and including an external capacitor C.sub.b connected between a circuit node V.sub.b, and a circuit node V.sub.S of the MOSgate driver circuit, the MOSgate driver circuit further including a common node and a series circuit including a charging capacitor C.sub.VCC, a resistor R.sub.b and a diode D.sub.b connected between the common node and the V.sub.b node; and the MOSgate driver circuit and the power switching circuit being connected as close as possible to one another to obtain short conductor lengths between the node V.sub.S and output node V.sub.O and between the common node and another common node of the power switching circuit, to thereby reduce the values of the inductances L.sub.S1 and L.sub.S2.
2. The circuit of claim 1, in which the capacitor C.sub.b has an increased value, substantially in excess of a capacitance needed to hold up a voltage of the first MOSgate transistor for a maximum pulse ON time, said increased value being determined by the inductances L.sub.S1 and L.sub.S2 and also by the size and type of said MOSgate transistors.
3. The circuit of claim 1, in which a capacitance of the capacitor C.sub.b has a value greater than about 0.47 .mu.F, for IR size 3 "k" type IGBTs.
4. The circuit of claim 1, in which the capacitor C.sub.VCC has a value of at least about ten times the value of the capacitor C.sub.b in the circuit.
5. The circuit of claim 1, in which the value of the resistor R.sub.b is minimized.
6. The circuit of claim 5, in which the value of resistor R.sub.b is about 0 ohms.
7. The circuit of claim 1, including a resistor R.sub.COM of about 1 to 20 ohms between the common node of the MOSgate driver circuit and the common node of the power switching circuit.