Method for Measuring Time and Structure Therefor

The present invention relates, in general, to measuring time, and more particularly, to measuring a time interval between two events using a time to digital converter.

In some applications such as electronic circuit testing, radar ranging, and elementary particle physics, it is often indispensable to be able to measure time at a very high resolution. To achieve a resolution finer than the period of a clock signal, a common approach uses an analog ramp circuit. The analog ramp circuit generates voltage ramp signals, which are used in conjunction with the clock signal to measure a time interval between a start signal and a stop signal. More particularly, the start signal activates a first ramp circuit, which in turn generates a first voltage ramp signal. The voltage increases until the first ramp circuit is deactivated by a leading edge of the clock signal following the start signal. At some time after the start signal, the stop signal activates a second ramp circuit, which in turn generates a second voltage ramp signal. The voltage increases until the second ramp circuit is deactivated by a leading edge of the clock signal following the stop signal. The slope of the each voltage ramps is equal to the rate of the voltage increase with respect to time. The duration of the first voltage ramp and the duration of the second voltage ramp are calculated by dividing the voltage excursions of the first and second voltage ramps by their respective slopes. In addition, the time duration between the leading edge of the clock signal following the start signal and the leading edge of the clock signal following the stop signal is calculated using a counter. This duration is referred to as a clocking interval. The time interval between the start signal and the stop signal is calculated by subtracting the duration of the second voltage ramp from the sum of the duration of the first voltage ramp and the clocking interval.

Circuits used for generating and sensing linear voltage ramps are typically large and complex, and are, therefore, expensive to manufacture on a monolithic integrated circuit. Furthermore, the circuits are not sufficiently accurate for some high resolution measurements. In addition, the cost of building measuring devices using the analog ramp circuits is usually high.

Accordingly, it would be advantageous to have a simple and inexpensive circuit for measuring time and achieving a resolution finer than the period of a clock signal. It is also desirable for the circuit to convert the measured time to a digital value quickly and accurately. It would be of further advantage for the circuit to be sufficiently small to be manufactured as a monolithic integrated circuit.

FIG. 1 is a schematic diagram of a time measurement circuit in accordance with a first embodiment of the present invention;

FIG. 2 is a timing diagram of a clock signal and an event signal applied to the time measurement circuit of FIG. 1;

FIG. 3 is a schematic diagram of a time measurement circuit in accordance with a second embodiment of the present invention; and

FIG. 4 is a timing diagram of clock, start, and stop signals applied to the time measurement circuit of FIG. 3.

Generally, the present invention provides a time measurement circuit and a method for measuring time. In accordance with an embodiment the present invention, the time measurement circuit, also referred as a time to digital converter, includes two digital phase counters and a period counter. The first digital phase counter measures a first time interval between a start signal and a leading edge of a clock signal following the start signal. The second digital phase counter measures a second time interval between a stop signal and a leading edge of the clock signal following the stop signal. The period counter measures a third time interval between the two leading edges of the clock signal. The time interval between the start and stop signals is then calculated by taking the difference between the first and second time intervals and adding the result to the third time interval.

FIG. 1 is a schematic diagram of a time measurement circuit 10 in accordance with a first embodiment of the present invention. In the first embodiment, time measurement circuit 10 is a digital phase counter. Phase counter 10 has a clock input 20 coupled for receiving a clock signal, an event signal input 30 coupled for receiving an event signal, a reset input 40 coupled for receiving a reset signal, a calibration input 50 coupled for receiving a calibration signal, and an output 60 coupled for transmitting a digital output signal. Phase counter 10 includes a decoder 17, a logic gate 18, a delay gate 28, and a resettable storage element 58. In the embodiment illustrated in FIG. 1, logic gate 18 is a logic AND/NAND gate and resettable storage element 58 is a resettable flip-flop. Phase counter 10 further comprises a plurality of serially coupled phase detection elements 41A-41N that generate a digital output signal in response to a time delay between a rising edge of the event signal and a rising edge of the clock signal immediately following the event signal. In the embodiment illustrated in FIG. 1, phase counter 10 includes 31 serially coupled phase detection elements 41A, 41B, . . . , and 41N. Decoder 17 has thirty-one inputs (D.sub.1, D.sub.2, . . . , and D.sub.31) and decodes thirty-one logic states into a five bit binary number. The five bit binary number is transmitted through an output port 60 of decoder 17.

It should be understood that, in accordance with the present invention, the number of serially coupled phase detection elements 41A-41N or the number of inputs in decoder 17 in phase counter 10 is not limited to being thirty-one. The dotted line between phase detection elements 41B and 41N represents any number of phase detection elements. In an alternative embodiment, phase counter 10 includes sixty-three phase detection elements 41A-41N in concatenation. Thus, decoder 17 decodes sixty-three logic states to a six bit binary number.

Each phase detection element 41A-41N includes corresponding reference delay gates 11A-11N, programmable delay gates 21A-21N, and storage elements. By way of example, the storage elements 51A-51N are flip-flops. Each reference delay gate 11A-11N has a differentially configured input serving as a first input of its corresponding phase detection element 41A-41N and a differentially configured output serving as a first delay output of its corresponding phase detection element 41A-41N. Each programmable delay gate 21A-21N has a differentially configured input serving as a second input of its corresponding phase detection element 41A-41N, a differentially configured output serving as a second delay output of its corresponding phase detection element 41A-41N, and a calibration input serving as a calibration input of its corresponding phase detection element 41A-41N. The calibration input is used to adjust the delay time between the input and the delay output of programmable delay gates 21A-21N. Each flip-flop 51A-51N has a differentially configured clock input coupled to the differentially configured output of its corresponding reference delay gate 11A-11N, a differentially configured data input coupled to the differentially configured output of its corresponding programmable delay gate 21A-21N, and an output serving as a logic output of its corresponding phase detection element 41A-41N. Although each reference delay gate 11A-11N is described as a delay gate having a fixed delay time (T1) and each programmable delay gate 21A-21N is described as having a programmable delay time (T2), this is not intended as a limitation of the present invention. As long as each delay gate 11A-11N has a delay time (T1) different from a delay time (T2) of each programmable delay gate 21A-21N, the delay gates 11A-11N and 21A-21N can be either delay gates having fixed delay times or delay gates having programmable delay times.

The first delay output of phase detection element 41A is connected to the first input of phase detection element 41B, i.e., the differentially configured input of reference delay gate 11B. The second delay output of phase detection element 41A is connected to the second input of phase detection element 41B, i.e., the differentially configured input of programmable delay gate 21B. The first and second delay outputs of phase detection element 41B are coupled to the first and second inputs of phase detection element 41N, respectively, through serially coupled phase detection elements which are represented by the dashed and dotted lines in FIG. 1. Although three phase detection elements are shown in FIG. 1, it should be noted that there may be less than three phase detection elements. To achieve a uniform operating condition in all phase detection elements 41A-41N, it is desirable to connect the output of reference delay gate 11N to an dummy gate 12 having the same input impedance as reference delay gates 11A-11N and to connect the output programmable delay gate 21N to a dummy gate 22 having the same input impedance as programmable delay gates 21A-21N. By way of example, dummy gates 12 and 22 are structurally identical to delay gates 11A-11N and 21A-21N, respectively. The logic output of phase detection element 41A, i.e., the true output of flip-flop 51A is connected to a first input (D.sub.1) of decoder 17. The logic output of phase detection element 41B, i.e., the true output of flip-flop 51B is connected to a second input (D.sub.2) of decoder 17. The logic output of phase detection element 41N, i.e., the true output of flip-flop 51N is connected to a thirty-first input (D.sub.31) of decoder 17. The calibration input of each phase detection element 41A-41N is connected to a node 50 for receiving a calibration signal.

Logic gate 18 has a first input serving as clock input 20 of phase counter 10 and a differentially configured output connected to a differentially configured clock input of resettable flip-flop 58. Resettable flip-flop 58 has a reset input serving as reset input 40 of phase counter 10 and a complementary output connected to a second input of logic gate 18. Delay gate 28 has a differentially configured input serving as input 30 of phase counter 10 and a differentially configured output connected to a differentially configured data input of resettable flip-flop 58. The differentially configured output of logic gate 18 is connected to the first input of phase delay element 41A, i.e., the differentially configured input of reference delay gate 11A. The differentially configured output of delay gate 28 is connected to the second input of phase detection element 41A, i.e., the differentially configured input of programmable delay gate 21A. The true logic output of each phase detection element 41A-41N is connected to a corresponding input (D.sub.1 -D.sub.31) of decoder 17. The output port of decoder 17 serves as output 60 of phase counter 10.

In FIG. 1, all delay gates and flip-flops are illustrated as having differentially configured inputs and outputs. Logic gate 18 is also illustrated as having a differentially configured output. A differentially configured input includes a true input and a complementary input. A differentially configured output includes a true output and a complementary output. Complementary inputs and complementary outputs transmit logic signals complementary to the logic signals transmitted by true inputs and true outputs, respectively. It should be understood that in high frequency applications, digital circuit blocks that are differentially configured are less sensitive to signal degradation than digital circuit blocks that are coupled in a single-ended configuration. However, the present invention is not limited to circuits configured differentially. Phase counter 10 can be in a single-ended configuration. In a single-ended configuration, logic gate 18 performs the function of a logic AND gate. It should also be understood that the circuit blocks having differentially configured inputs or outputs are not limited to those illustrated in FIG. 1. In another example, clock input 20 and reset input 40 are differentially configured inputs coupled for receiving a differential clock signal and a differential reset signal, respectively. In addition, inputs D.sub.1, D.sub.2, . . . , D.sub.31 of decoder 17 may be differentially configured for receiving differential logic output signals from the corresponding flip-flops 51A, 51B, . . . , 51N.

FIG. 2 is a timing diagram for a clock signal 120 and an event signal 130. Clock signal 120 is applied to clock input 20 of phase counter 10 shown in FIG. 1. Event signal 130 is a differential signal applied to differentially configured input 30 of phase counter 10 shown in FIG. 1. For the purpose of simplicity, only one component, e.g., the true component, of event signal 130 is illustrated in FIG. 2. A time t.sub.0 represents a rising edge of event signal 130 and a time t.sub.1 represents a rising edge of clock signal 120 immediately following the rising edge of event signal 130.

Phase counter 10 in FIG. 1 measures a time duration from time t.sub.0 to time t.sub.1. The resolution of the measurement is determined by the number of phase detection elements 41A-41N. More particularly, the resolution is determined by the delay of delay gates 21A-21N relative to the delay of corresponding delay gates 11A-11N, and a number that is greater than the number of phase detection elements 41A-41N by one. For example, a resolution that is thirty-two times as fine as the period of clock signal 120 is achieved by using thirty-one phase detection elements 41A-41N, i.e., one less phase detection element than the desired resolution. This resolution is achieved by setting the adjustable delay time (T2) of programmable delay gates 21A-21N in each phase detection element 41A-41N to be longer than the reference delay time (T1) of reference delay gates 11A-11N by an amount of time equal to the quotient of the period of clock signal 120 and the number thirty-two. The calibration of a programmable delay gate is described in U.S. Pat. No. 5,063,311 entitled "Programmable Time Delay Circuit for Digital Logic Circuits", issued to Mavin C. Swapp on Nov. 5, 1991, and assigned to Motorola, Inc. U.S. Pat. No. 5,063,311 is hereby incorporated herein by reference. By way of example, clock signal 120 has a period of, for example, 320 pico-second (ps). Accordingly, phase counter 10 has a resolution of 10 ps when each programmable delay gate 21A-21N is calibrated to have a delay time (T2) which is 10 ps longer than the reference delay time (T1) of each reference delay gate 11A-11N.

It should be understood that, in accordance with the present invention, the period of clock signal 120 is not limited to being 320 ps and the delay time of each programmable delay gate 21A-21N in excess of that of each reference delay gate 11A-11N is not limited to being 10 ps. The resolution of phase counter 10 is equal to the delay time of each programmable delay gate 21A-21N in excess of that of each reference delay gate 11A-11N. It should be noted that the resolution of phase counter 10 has an upper limit equal to the period of clock signal 120 divided by a number that is greater than the number of phase detection elements 41A-41N by one. Therefore, the delay time (T2) of each programmable delay gate 21A-21N in excess of that of each reference delay gate 11A-11N (T1) has a lower limit equal to the period of clock signal 120 divided by a number that is greater than the number of phase detection elements 41A-41N by one.

In operation, resettable flip-flop 58 is first reset to a logic low state by applying a reset signal to reset input 40. Resetting resettable flip-flop 58 places a logic high voltage level at the complementary output of resettable flip-flop 58, which is transmitted to the second input of logic gate 18. Clock signal 120 is applied at clock input 20 and transmitted through logic gate 18 to the clock input of resettable flip-flop 58. Before time t.sub.0, resettable flip-flop 58 is at the logic low state.

At time t.sub.0, a rising edge of event signal 130 reaches the data input of resettable flip-flop 58 via delay gate 28. At time t.sub.1, the first rising edge of clock signal 120 following the rising edge of event signal 130 reaches the clock input of resettable flip-flop 58, resulting in resettable flip-flop 58 switching to a logic high state. A logic low voltage level appearing at the complementary output of resettable flip-flop 58 is transmitted to the second input of logic gate 18, resulting in a logic low voltage level appearing at the true output of logic gate 18. The rising edge of event signal 130 and the first rising edge of clock signal 120 following the rising edge of event signal 130 continue to propagate through phase detection elements 41A-41N.

If time t.sub.0 occurs less than 10 ps before time t.sub.1, the rising edge of event signal 130 will reach the data input of flip-flop 51A after the rising edge of clock signal 120 reaches the clock input of flip-flop 51A because the delay time of programmable delay gate 21A is 10 ps longer than that of reference delay gate 11A. Flip-flop 51A is therefore set to a logic low state. Thus, a logic low voltage level appears at the true output of flip-flop 51A and is transmitted to the first input (D.sub.1) of decoder 17. The rising edge of event signal 130 falls further behind the first rising edge of clock signal 120 as they continue to propagate through phase detection elements 41B-41N. Thus, flip-flops 51B-51N of respective phase detection elements 41B-41N are also set to logic low states, resulting in logic low voltage levels being transmitted from the true outputs of flip-flops 51B-51N to corresponding inputs D.sub.2 -D.sub.31 of decoder 17. With all of its inputs (D.sub.1 -D.sub.31) at a logic low voltage level, decoder 17 generates a phase count of zero in a five bit binary number format (00000) at output 60, indicating that the time interval from time t.sub.0 to time t.sub.1 is less than 10 ps. If time t.sub.0 occurs more than 20 ps but less than 30 ps before time t.sub.1, the rising edge of event signal 130 will reach the data input of flip-flop 51A more than 10 ps but less than 20 ps before the rising edge of clock signal 120 reaches the clock input of flip-flop 51A because the delay time of programmable delay gate 21A is 10 ps longer than that of reference delay gate 11A. Flip-flop 51A is therefore set to a logic high state, resulting in a logic high voltage level being transmitted to the first input (D.sub.1) of decoder 17. Likewise, the rising edge of event signal 130 will reach the data input of flip-flop 51B less than 10 ps before the rising edge of clock signal 120 reaches the clock input of flip-flop 51B because the delay time of programmable delay gate 21B is 10 ps longer than that of reference delay gate 11B. Flip-flop 51B is therefore set to a logic high state, resulting in a logic high voltage level being transmitted to the second input (D.sub.2) of decoder 17. The rising edge of event signal 130 falls behind the rising edge of clock signal 120 as they propagate through the phase detection elements serially coupled to phase detection element 41B. Thus, flip-flops of the corresponding phase detection elements are set to logic low states, resulting in logic low voltage levels being transmitted to the corresponding inputs of decoder 17. Since the first two inputs (D.sub.1 and D.sub.2) are at a logic high voltage level and next twenty-nine inputs are at a logic low voltage level, decoder 17 generates a digital value of two in a five bit binary number format (00010) at output 60, indicating that the time interval from time t.sub.0 to time t.sub.1 is more than 20 ps but less than 30 ps.

For other time differences between the rising edge of event signal 130 and the first rising edge of clock signal 120 following the rising edge of event signal 130, phase counter 10 measures the time differences in a way similar to what is described in the two examples cited supra. The results of the measurement are determined by the number of inputs of decoder 17 at the logic high voltage level.

It should be understood that resettable flip-flop 58 and flip-flops 51A-51N of phase detection elements 41A-41N are not limited to being rising edge triggered as described supra. If resettable flip-flop 58 and flip-flops 51A-51N of phase detection elements 41A-41N are falling edge triggered, phase counter 10 measures a time interval between a rising edge of event signal 130 and the first falling edge of clock signal 120 following the event signal. Furthermore, decoder 17 is not limited to decoding thirty-one logic states into a five bit binary format. In an alternative embodiment, decoder 17 decodes thirty-one logic states into a decimal number and output 60 is a visual display that displays the results of the measurement.

FIG. 3 is a schematic diagram of a time measurement circuit 100 in accordance with a second embodiment of the present invention. In the second embodiment, time measurement circuit 100 is a time to digital converter. Time measurement circuit 100 has a clock input 20' coupled for receiving a clock signal, a first event signal input 30' coupled for receiving a first event signal, e.g., a start signal, a second event signal input 30" coupled for receiving a second event signal, e.g., a stop signal, a reset input 40' coupled for receiving a reset signal, a calibration input 50' coupled for receiving a calibration signal, and an output 360 coupled for transmitting a digital output signal. Time measurement circuit 100 includes a period counter 210, a digital calculator 310, and two digital phase counters, 10' and 10". Although digital phase counters 10' and 10" can serve as time measurement circuits, they are referred to as phase counters with reference to FIGS. 3 and 4 to prevent confusing them with time measurement circuit 100.

Phase counters 10' and 10" are structurally identical to phase counter 10 of FIG. 1. It should be understood that the same reference numerals are used in the figures to denote the same elements. It should be noted that primes (') and double primes (") are included in reference numerals in FIGS. 3 and 4 to denote elements that are common to FIG. 1, but are coupled differently. A clock input (CLK) of phase counter 10' and a clock input (CLK) of phase counter 10" are connected to clock input 20' of time measurement circuit 100. An input (T) of phase counter 10' serves as first input 30' of time measurement circuit 100. An input (T) of phase counter 10" serves as second input 30" of time measurement circuit 100. A reset input (R) of phase counter 10' and a reset input (R) of phase counter 10" are connected together to form reset input 40' of time measurement circuit 100. Calibration inputs (CAL) of phase counter 10' and phase counter 10" are connected together to form calibration input 50' of time measurement circuit 100.

Period counter 210 has a clock input connected to clock input 20' of time measurement circuit 100, a first activation input connected to an activation output 70' (ACT) of phase counter 10', and a second activation input connected to an activation output 70" (ACT) of phase counter 10". The true outputs of the resettable flip-flops (not shown) in phase counter 10' and phase counter 10" serve as activation outputs (ACT) 70' and 70", respectively. Period counter 210 includes an EXCLUSIVE-OR gate 212, a flip-flop 214, an AND gate 216, and a counter 218. EXCLUSIVE-OR gate 212 has a first input serving as the first activation input of period counter 210 and a second input serving as the second activation input of period counter 210. Flip-flop 214 has a clock input serving as the clock input of period counter 210 and a data input connected to an output of EXCLUSIVE-OR gate 212. AND gate 216 has a first input connected to a true output of flip-flop 214 and a second input connected to the clock input of flip-flop 214. Counter 218 has an input connected to an output of AND gate 216 and an output serving as output 260 of period counter 210.

Digital calculator 310 of time measurement circuit 100 has a first input port (A) connected to output 60' (Q) of phase counter 10', a second port (B) connected to output 60" (Q) of phase counter 10", a third input port (C) connected to output 260 of period counter 210, and an output port serving as output 360 of time measurement circuit 100. A first activation input of digital calculator 310 is coupled to activation output 70' of phase counter 10' and a second activation input of digital calculator 310 is coupled to activation output 70" of phase counter 10".

It should be understood that activation output 70' of phase counter 10' is not limited to being represented by the true output of resettable flip-flop 58 of phase counter 10'. In an alternative embodiment, activation output 70' is represented by the complementary output of resettable flip-flop 58 of phase counter 10'. It should be noted that phase counter 10" has the same structure as phase counter 10'. Therefore, the relationship between activation output 70' and the internal components of phase counter 10' is the same as that between activation output 70" and the internal components of phase counter 10".

FIG. 4 is a timing diagram for a clock signal 420 having a period of, for example, 320 pico-second (ps), a start signal 430', and a stop signal 430". Clock signal 420 is applied to clock input 20' of time measurement circuit 100 shown in FIG. 3. Start signal 430' is a differential signal applied to differentially configured input 30' of time measurement circuit 100 shown in FIG. 3. Stop signal 430' is a differential signal applied to differentially configured input 30" of time measurement circuit 100 shown in FIG. 3. For the purpose of simplicity, only the true components of start signal 430' and stop signal 430" are illustrated in FIG. 4. A rising edge of start signal 430' occurs at time t.sub.0 '. The first rising edge of clock signal 420 following the rising edge of start signal 430' occurs at a time t.sub.1 '. A rising edge of stop signal 430" occurs at a time t.sub.2 '. The first rising edge of clock signal 420 following the rising edge of stop signal 430" occurs at a time t.sub.3 '.

Time measurement circuit 100 measures a time interval between two signals. Before a measurement starts, a reset signal is applied to reset input 40'. The reset signal is transmitted to the reset input of phase counter 10', to the reset input of phase counter 10', and to counter 218 of period counter 210. Upon receiving the reset signal, counter 218 is reset to zero and ready to count the number of pulses transmitted to its input. Phase counters 10' and 10" generate a logic low voltage level at activation outputs 70' and 70", respectively. The logic low voltage levels at activation outputs 70' and 70" are transmitted to the first and second inputs of EXCLUSIVE-OR gate 212, respectively. Thus, EXCLUSIVE-OR gate 212 sends a logic low signal to the data input of flip-flop 214, resulting in a logic low voltage level appearing at the true output of flip-flop 214 when a rising edge of clock signal 420 reaches the clock input of flip-flop 214. The logic low voltage level at the true output of flip-flop 214 is transmitted to the second input of AND gate 216 and sets the input of counter 218 to a logic low voltage level, thereby disabling counter 218.

At time t.sub.0 ', a rising edge of start signal 430' reaches input 30' of time measurement circuit 100. At time t.sub.1 ', the first rising edge of clock signal 420 following the rising edge of start signal 430' reaches clock input 20' of time measurement circuit 100. Phase counter 10' generates a first phase count representing a time interval between time t.sub.0 ' and time t.sub.1 ' in the same way as phase counter 10 of FIG. 1 measures the time interval between time t.sub.0 and time t.sub.1 of FIG. 2.

At time t.sub.2 ', a rising edge of stop signal 430" reaches input 30" of time measurement circuit 100. At time t.sub.3 ', the first rising edge of clock signal 420 following the rising edge of stop signal 430" reaches clock input 20' of time measurement circuit 100. Phase counter 10" generates a second phase count representing a time interval between time t.sub.2 ' and time t.sub.3 ' in the same way as phase counter 10 of FIG. 1 measures the time interval between time t.sub.0 and time t.sub.1 of FIG. 2.

At time t.sub.1 ', the first rising edge of clock signal 420 following start signal 430' causes a logic high voltage to appear at activation output 70' of phase counter 10'. Between time t.sub.1 ' and time t.sub.3 ', the first and second inputs of EXCLUSIVE-OR gate 212 are at a logic high voltage level and a logic low voltage level, respectively. Thus, EXCLUSIVE-OR gate 212 generates a logic high voltage level at the data input of flip-flop 214, resulting in flip-flop 214 switching to a logic high state at the first rising edge of clock signal 420 following the rising edge of start signal 430'. The true output of flip-flop 214 transmits the logic high voltage level to the first input of AND gate 216. Therefore, the logic state at the output of AND gate 216 is identical to clock signal 420 appearing at the second input of AND gate 216. Counter 218, upon receiving clock signal 420 via AND gate 216, starts to count the rising edges of clock signal 420.

At time t.sub.3 ', the first rising edge of clock signal 420 following stop signal 430" causes a logic high voltage to appear at activation output 70" of phase counter 10". A logic high voltage levels appears at both inputs of EXCLUSIVE-OR gate 212, generating a logic low voltage level at the data input of flip-flop 214. Thus, a logic low voltage level appears at the true output of flip-flop 214 when the first rising edge of clock signal 420 following the rising edge of stop signal 430" reaches the clock input of flip-flop 214. The logic low voltage level at the true output of flip-flop 214 is transmitted to the second input of AND gate 216 and sets the input of counter 218 to a logic low voltage level, which in turn stops counting.

If the rising edge of start signal 430' arrives at input 30' and the rising edge of stop signal 430" arrives at input 30" of digital converter 100, respectively, within two adjacent rising edges of clock signal 420, the first rising edge of clock signal 420 following the rising edge of start signal 430' is also the first rising edge of clock signal 420 following the rising edge of stop signal 430'. Thus, time t.sub.1 ' is the same as time t.sub.3 '. Under this condition, the two inputs of EXCLUSIVE-OR gate 212 switch from a logic low voltage level to a logic high voltage level simultaneously. Therefore, the output of EXCLUSIVE-OR gate 212 stays at a logic low voltage level. The true output of flip-flop 214 and the output of AND gate 216 also remain at logic low voltage levels, resulting in counter 218 remaining inactive.

Throughout the process, counter 218 generates a period count of the number of pulses of clock signal 420 from time t.sub.1 ' to time t.sub.3 '. The product of the period count and the period of clock signal 420 equals the time interval between time t.sub.1 ' and time t.sub.3 '. The period count is transmitted to output 260 of period counter 210 in a binary number format.

After receiving activation signals from activation output 70' of phase counter 10' and from activation output 70" of phase counter 10", digital calculator 310 combines the first phase count (A) received from output 60' of phase counter 10' via the first input port, the second phase count (B) received from output 60" of phase counter 10" via the second input port, and the period count (C) received from output 260 of period counter 210 via the third input port to generate a time count at output 360 of time measurement circuit 100. The time count represents a time interval between time t.sub.0 ' and time t.sub.2 '. In the example cited supra, each increment of the first phase count (A) and the second phase count (B) represents a time interval equal to the resolution of phase counter 10' and 10", i.e., 10 ps, and each increment in the period count (C) represents a time interval equal to the period of clock signal 420, i.e., 320 ps. Therefore, the time count represents a time interval equal to (320C+10A-10B) ps between time t.sub.0 ' and time t.sub.2 '. It should be understood that the format of the output of time measurement circuit 100 is not limited to a binary format. In one example, the time count is converted to a decimal number and output 360 of time measurement circuit 100 is a visual display that displays the result of the measurement.

The result of the measurement by time measurement circuit 100 is determined by, among other factors, the difference between the time interval from the rising edge of start signal 430' to the first rising edge of clock signal 420 following the rising edge of start signal 430' and the time interval from the rising edge of stop signal 430" to the first rising edge of the clock signal 420 following the rising edge of stop signal 430". Therefore, the actual delay times of logic gate 18 and delay gate 28 of phase counter 10' are inconsequential to the time measurement result as long as phase counter 10" is the same as phase counter 10'.

By now it should be appreciated that a circuit and a method for measuring time have been provided, wherein the resolution of the measurement is finer than the period of a clock signal used in the measurement. A circuit in accordance with the present invention can be used to simulate a clock with a frequency higher than that of the clock signal supplied to the circuit or to simulate a high speed counter. The present invention is applicable not only in the area of high precision time measurement, but also in the area of low power circuitry. A circuit in accordance with the present invention can use a low frequency clock signal source to perform a function which otherwise requires a high frequency clock signal source. As those skilled in the art are aware, low frequency clock signal sources usually consume less power than high frequency clock signal sources. Furthermore, present invention provides a circuit that is fast, accurate, simple, and inexpensive compared with prior art circuits. In addition, the present invention provides a time measurement circuit that can be manufactured as a monolithic integrated circuit.