Method of Converting a Series of M-Bit Information Words to a Modulated Signal, Method of Producing a Record Carrier, Coding Device, Device, Recording Device, Signal, as Well as a Record Carrier

The invention relates to a method of converting a series of m-bit information words to a modulated signal, with m being an integer, in which method an n-bit code word is delivered for each received information word, with n being an integer exceeding m, and the delivered code words are converted to the modulated signal, and in which the series of information words is converted to a series of code words according to rules of conversion, so that the corresponding modulated signal satisfies a predetermined criterion, and in which the code words are spread over at least a group of a first type and at least a group of a second type, while the delivery of each of the code words belonging to the group of the first type establishes a first type of coding state determined by the associated group, the delivery of each of the code words belonging to the group of the second type establishes a second type of coding state determined by the associated group and by the information word associated to the delivered code word and, when one of the code words is assigned to the received information word this code word is selected from a set of code words that depends on the coding state established when the preceding code word was delivered, while the sets of code words belonging to the coding states of the second type do not contain any code words in common, in which the group of the second type comprises at least one codeword being associated with a plurality of information words among which the respective information word is distinguishable by detecting the respective set of which the following codeword is a member.

The invention further relates to a method for producing a record carrier on which a signal is recorded obtained according to said method.

The invention further relates to a coding device for performing the method as claimed, this device comprising an m-to-n bit converter for converting the m-bit information words to n-bit code words, and means for converting the n-bit code words to a modulated signal.

The invention further relates to a recording device in which a coding device of this type is used.

The invention further relates to a signal.

The invention further relates to a record carrier on which the signal is recorded.

Such methods, such devices, such a record carrier and such a signal are known from WO 95/22802 (corresponding to EP-A-94200387.2, PHN 14746). The document relates to a method of converting a series of m-bit information words to a modulated signal, the method being called EFM+. For each information word from the series an n-bit code word is delivered. The delivered code words are converted to a modulated signal. The code words are distributed over at least one group of a first type and at least one group of a second type. For the delivery of each of the code words belonging to the group of the first type the associated group establishes a coding state of the first type. When a code word belonging to the group of the second type is delivered, a coding state of the second type is established. A code word is assigned to the received information word selected from a set of code words which depends on the established coding state. The sets of code words belonging to the coding states of the second type are disjunct. The selected one of the possible coding sets of the second type is determined by the information word associated to the delivered code word. This allows several information words being associated with the same code word, the established coding state being different. In this coding method the number of unique bit combinations that may be used by the code words in the series is enlarged, thereby increasing the coding efficiency. The modulated signal thus obtained may be reconverted to information words by first converting the modulated signal to a series of code words and then assigning an information word to each of the code words from the series in dependence on the code word to be converted and also in dependence on the logical values of the bit string bits which are situated at predetermined positions relative to the code word, which logical values are indicative for the previously established coding state. Furthermore, a recording device and a reading device are disclosed.

The low frequency components of the modulated signal may interfere with other system parameters, such as servo signals in a recording system. Although the above converting method results in a modulated signal with a limited low frequency content, there still is a need to decrease the low frequency components.

Therefore it is an object of the invention to provide means for converting adapted for reducing the low-frequency content of the modulated signal.

According to a first aspect of the invention this object is achieved with a method as in the opening paragraph, characterized in that after establishing the first type of coding state a codeword is selected from the set belonging to the established coding state or from a set belonging to a different coding state of the first type while not violating the predetermined criterion in dependence of a low frequency content of the modulated signal.

According to further aspects of the invention this object is achieved with a signal, a record carrier, a coding device, a recording device and a method for producing a record carrier, as claimed in the claims 2 to 12. The measures according to the invention have the advantage, that the low frequency content (sometimes referred to as DC) of the modulated signal can be decreased, while keeping the same information coding efficiency.

The invention will be further explained with reference to the drawing FIGS. 1 to 9, in which:

FIG. 1 shows a series of information words, a corresponding series of code words and a modulated signal;

FIG. 2 shows a record carrier;

FIG. 3 shows a considerably enlarged portion of the record carrier of FIG. 2;

FIG. 4 shows a recording device;

FIG. 5 shows a decoding and playback device.

FIG. 6 shows a coding device;

FIGS. 7 and 8 show tables in which the relation between the information words and code words is established;

FIG. 9 shows the frequency spectrum of a modulated signal;

FIG. 1 shows three consecutive m-bit information words, in this case, 8-bit information words referenced 1. Information about coding methods can be found in the book by K. A. Schouhamer Immink entitled "Coding Techniques for Digital Recorders" (ISBN 0-13-140047-9). In said title, for example, the so-called EFM modulation system is described which is used for recording information on so-called Compact Discs. The EFM-modulated signal is obtained by converting a series of 8-bit information words to a series of 14-bit code words, three merging bits being inserted into the code words. The code words are selected such that the minimum number of "0" bits situated between the "1" bits is d (2) and the maximum number is k (10). This constraint is also referenced dk-constraint. The series of code words is converted, via a modulo-2 integration operation, to a corresponding signal formed by bit cells having a high or low signal value, a "1"-bit being represented in the modulated signal by a change from the high to the low signal value or vice versa. A "0"-bit is represented by the lack of a change of signal value at a transition between two bit cells. The merging bits are selected such that even in the regions of transition between two code words the dk-constraint is satisfied and that in the corresponding signal the so-called running digital sum value remains substantially constant. The running digital sum value at a specific instant is understood to mean the difference between the number of bit cells having the high signal value and the number of bit cells having the low signal value, calculated over the modulated signal portion situated before this instant. A substantially constant running digital sum value means that the frequency spectrum of the signal does not comprise frequency components in the low frequency area. Such a signal is also referenced a DC-free signal. The lack of low-frequency components in the signal is highly advantageous when the signal is read from a record carrier on which the signal is recorded in the track, because then continuous tracking control unaffected by the recorded signal is possible. Information recording has a constant need for enhancing the information density on the record carrier. In FIG. 1 the three information words 1 have the respective word values "24", "121" and "34". This series of 3 information words 1 is converted to three consecutive n-bit code words, in this case, 16-bit code words referenced 4. The code words 4 form a bit string of bits having a logical "0" value and bits having a logical "1" value. The conversion of the information words is such that in the bit string the minimum number of bits having a logical "0" value positioned between two bits having a logical "1" value is d and the maximum is k, where d is equal to 2 and k is equal to 10. Such a bit string is often referenced a RLL string (RLL=Run Length Limited) with a dk-constraint. The individual bits of the code words will further be referenced x1, . . . , x16, where x1 denotes the first bit (from the left) of the code word and x16 denotes the last bit of the code word.

The bit string formed by the code words 4 is converted to a modulated signal 7 by means of a modulo-2 integration operation. This modulated signal comprises three information signal portions 8 representing the code words 4. The information signal portions comprise bit cells 11 which may have a high signal value H or a low signal value L. The number of bit cells per information signal portion is equal to the number of bits of the associated code word. Each code word bit having a logical "1" value is indicated in the modulated signal 7 by a transition from a bit cell having the high signal value to a bit cell having the low signal value, or vice versa. Each code word bit having the logical "0" value is indicated in the modulated signal 7 by the absence of a change of signal value at a bit cell transition.

Furthermore, the frequency spectrum of the modulated signal 7 is required to include substantially no low-frequency components. Worded differently, the modulated signal 7 is to be DC-free.

In the following an embodiment of the method according to the invention by which the modulated signal can be obtained will be described in detail.

First there is a requirement with respect to the code words that within the code words the dk-constraint is satisfied. The set of all the possible code words satisfying said dk-constraint is divided into at least group of a first type and at least a group of a second type. When a code word is delivered from one of the groups of the first type, a coding state is established which exclusively depends on the group of the first type to which the delivered code word belongs. When one of the code words of the group of the first type is delivered, a coding state is established which depends both on the group of the first type and on the information word represented by the delivered code word. In the embodiment described herein, two groups of the first type can be distinguished i.e. a first group G11 which comprises code words ending in a bits having a logical "0" value, where a is an integer equal to 0 or 1, and a second group G12 of code words ending in b bits having a logical "0" where with b is an integer smaller than or equal to 9 and greater than or equal to 6.

The coding state established by the first group G11 of the first type will henceforth be referenced S1. The coding state established by the second group G12 of the first type will henceforth be referenced S4. The embodiment to be described here only knows one group of the second type. This group comprises code words ending in c bits having a logical "0" value, where c is an integer greater than or equal to 2 and smaller than or equal to 5. This group will henceforth be referenced group G2. In the example to be described here, two coding states i.e. S2 and S3 can be established by the combination of a code word and associated information word.

When the information words are converted to code words, a code word belonging to a set of code words depending on the coding state is assigned to the information word to be converted. The sets of code words belonging to the coding states S1, S2, S3 and S4 will henceforth be referenced V1, V2, V3 and V4, respectively. The code words in the sets are selected such that each bit string that can be formed by a code word from the group that has established a coding state and an arbitrary code word from the set established by this coding state satisfies the dk-constraint. In the case where the coding state S4 is established by the delivery of the previously delivered code word and the coding state thus denotes that the previous code word ends in a bit string having a logical "0" value greater than or equal to 6 and smaller than or equal to 9, code word set V4 which is established by the coding state S4 is only allowed to comprise code words beginning with a maximum of 1 bit having the logical "0" value. For that matter, code words beginning with a larger number of bits having the logical "0" value will have transitional areas between the previously delivered code word and the code word to be delivered, in which areas the number of successive bits having the logical "0" value will not always be smaller than or equal to 10 and thus not satisfy the dk-constraint. For similar reasons, set V1 comprises only code words beginning with a number of bits having the logical "0" value that is greater than or equal to 2 and smaller than or equal to 9.

Sets V2 and V3 of code words belonging to the coding states S2 and S3 contain only code words beginning with a number of bits having a logical "0" value greater than or equal to 0 and smaller than or equal to 5. The code words satisfying this condition are spread over the two sets V2 and V3, so that sets V2 and V3 do not contain any common code words at all. Sets V2 and V3 will be referenced disjunct sets in the following. The spreading of the code words over sets V2 and V3 is preferably such that on the basis of the logical values of a limited number of p bits there can be determined to what set a code word belong. In the example described above, the bit combination x1.x13 is used for this purpose.

Code words from set V2 are recognisable from the bit combination x1.x13=0.0. Code words from set V3 are then recognisable from the combination x1.x13 which is unequal to 0.0. A distinction is made between code words establishing coding state S1 (group G11) on delivery, code words establishing coding state S2 or S3 (group G2) on delivery, and code words establishing the coding state S4 (group G12) on delivery. Set VI comprises 138 code words from group G11, 96 code words from group G2 and 22 code words from group G12.

It will be evident that the number of different code words in set VI is smaller than the number of different 8-bit information words.

Since the code words from group G2 are always followed by a code word from set V2 or a code word from set V3, and, in addition, based on the code word following a code word from group G2 there may be established what set this code word belongs to, a code word from group G2 followed by a code word from set V2 can be unequivocally distinguished from the same code word from group G2, but followed by a code word from set V3. Worded differently, when code words are assigned to an information word, each code word from group G2 can be used twice. Each code word from group G2 together with a random code word from set V2 forms a unique bit combination which is inseparable from the bit combination formed by the same code word and a random code word from the same set V3. This means that 138 unique bit combinations (code words) from group G11 can be used for set V1, 22 unique bit combinations (code words) from group G12 and 2*96 unique bit combinations (code words from group G2 combined with subsequent code words) from group G2. This brings the total number of useful unique bit combinations to 352. The number of unique bit combinations formed with the code words from sets V2, V3 and V4 are 352, 351 and 415, respectively.

FIG. 2 shows by way of example, a record carrier 120 according to the invention. The record carrier shown is one of an optically detectable type. The record carrier may also be of a different type, for example, of a magnetically readable type. The record carrier comprises information patterns arranged in tracks 121. FIG. 3 shows a strongly enlarged portion 122 of one of the tracks 121. The information pattern in the track portion 121 shown in FIG. 3 comprises first sections 123, for example, in the form of optically detectable marks and second sections 124, for example, intermediate areas lying between the marks. The first and second sections alternate in a direction of the track 125. The first sections 123 present first detectable properties and the second sections 124 present second properties which are distinguishable from the first detectable properties. The first sections 123 represent bit cells 12 of the modulated binary signal 7 having one signal level, for example, the low signal level L. The second sections 124 represent bit cells 11 having the other signal level, for example, the high signal level H. The record carrier 12 may be obtained by first generating the modulated signal and then providing the record carrier with the information pattern. If the record carrier is of an optically detectable type, the record carrier can then be obtained with mastering and replica techniques known per se based on the modulated signal 7.

FIG. 4 shows a recording device for recording information, in which the coding device according to the invention is used, for example, the coding device 140 shown in FIG. 6. In the recording device the signal line for delivering the modulated signal is connected to a control circuit 141 for a write head 142 along which a record carrier 143 of a writable type is moved. The write head 142 is of a customary type capable of introducing marks having detectable changes on the record carrier 143. The control circuit 141 may also be of a customary type generating a control signal for the write head in response to the modulated signal applied to the control circuit 141, so that the write head 142 introduces a pattern of marks that corresponds to the modulated signal.

FIG. 5 shows a reading device in which a decoding device according to the invention is used, for example, a decoding device 153 as described below. The reading device comprises a read head of a customary type for reading a record carrier according to the invention which record carrier carries an information pattern that corresponds to the modulated signal. The read head 150 then produces an analog read signal modulated according to the information pattern read out by the read head 150. Detection circuit 152 converts this read signal in customary fashion to a binary signal which is applied to the decoding circuit 153.

An embodiment of the decoding device 153 consists of a logic array that implements the inverse of the coding function. Using the coding tables as described with FIG. 7 words can be uniquely decoded by observing a 15 bit codeword, the two-tuple x1x3 formed by the 1st and 3rd bit of the upcoming codeword, and the number of zeros with which the previous codeword ended. In a formula (see encoding formula described later), the inverse function can be expressed as

Note that observation of the 9 tail bits of the previous codeword Xt-1 is sufficient. From the above it can be seen that error propagation is limited to at most one byte. the logic array that translates (9+15+2) channel bits into 8 user bits can easily be reduced by exploiting a few properties of the code. The 2-bit look ahead is essentially one bit (indicating state 2 or 3) and the 9 bit look-back can be reduced to 2 bits (indicating states 1,2,3 or 4). Look-up is therefore required of (2+15+1) bits into 8 bits.

FIG. 6 shows an embodiment for a coding device 140 according to the invention by which the method described above can be carried out. The coding device is arranged for converting the m-bit information words 1 to the n-bit code words 4 and the number of different coding states can be indicated by s bits. The coding device comprises a converter 60 for converting (m+s+1) binary input signals to (n+s+t) binary output signals. From the inputs of the converter m inputs are connected to a bus 61 for receiving m-bit information words. From the outputs of the converter n outputs are connected to a bus 62 for delivering n-bit code words. Furthermore, s inputs are connected to an s-bit bus 63 for receiving a state word denoting the current coding state. A state word is delivered by a buffer memory 64, for example, in the form of s flip-flops. The buffer memory 64 has s inputs connected to a bus 58 for receiving a state word to be stored in the buffer memory. For delivering the state words to be stored in the buffer memory, s outputs of the converter 60 are used which are connected to bus 58.

Bus 62 is connected to the parallel inputs of a parallel-to-serial converter 66 which converts code words 4 received over bus 62 to a serial bit string to be supplied over a signal line 67 to a modulator circuit 68 which converts the bit string to the modulated signal 7 to be delivered over signal line 70. The modulator circuit 68 may be one of a customary type, for example, a so-termed modulo-2 integrator.

In addition to the code words and state words, the converter applies to a bus 75 or each received combination of information word and state word information which

denotes whether for the associated state word the code word or a pair of code words is assigned to the associated information word,

denotes for each of these assigned code words the change dDSV of the digital sum value caused by the code word as this change would be for a high signal value at the beginning of an information signal portion corresponding to this code word,

denotes whether the number of "1" bits in the code word is odd or even.

For information transfer to a selection circuit 76 the bus 75 is connected to inputs of the selection circuit 76. The selection circuit calculates a running DSV for a portion of the modulated signal. This portion may start at a arbitrary point in the past or at a sync word. In another embodiment the DSV may also be calculated for a future portion, but in that case a memory is needed for temporarily storing the possible sequences of codewords.

Based on this information the selection circuit 76 delivers a selection signal which indicates whether the code word to be fed to the bus 62 with the presented information word has to increase or decrease the DSV value. This selection signal is applied to the converter 60 over a signal line 77. Accordingly the information word is to be converted in accordance with the relations laid down in the tables of FIG. 8a, or in accordance with the relations laid down in the tables of FIG. 8b. Further according to the invention, the converter establishes if a selection from different coding states of the first type is possible. For the tables of FIG. 8 this may be applicable for the in for the actual codeword form other sets. For the actual codeword form other sets of the first type the converter 60 verifies, if the dk-constraint is complied with. If the dk-constraint is not violated, the word from the other set is selectable. In that case the selection of the set to use is based on the selection signal.

The converter 60 may comprise a ROM memory in which the code word tables shown in FIGS. 8a or 8b are stored at addresses determined by the combination of state word and information word applied to the inputs of the converter. In response to the detection signal, the addresses of the memory locations are selected with the code words corresponding to the table shown in FIG. 8a or the addresses of the memory locations with the code words corresponding to the table shown in FIG. 8b. A similar ROM memory may be used for a coding table from FIG. 7, which memory should then also comprise locations for the `don't care` bits as indicated by x.

In the embodiment shown in FIG. 6 the state words are stored in memory 60. Alternatively, it is possible to derive, by a gate circuit, only the state words from the code words delivered to the bus 62.

FIG. 7 shows a coding table according to the invention. The parameters of this example are d=2, k=14, rate=8/15, the If contents are suppressed, the error propagation is limited to at most one byte. Further it has a unique 20 bit sync pattern and uses only 4 tables for encoding and decoding.

An encoder for this embodiment is a device with an 8-bit input, a 15 bit output, and an internal state which are functions of the (discrete) time. The principle of operation can be represented by a conventional finite state machine, a well known concept in the field of computation and automation theory. The encoder can be modeled with four states. We say that the states are connected by edges, and the edges, in turn, are labelled with tags called code words. A word in this embodiment is a 15 bit sequence that obeys the prescribed dk constraints. Each of the four states is characterized by the type of words that enter the given state as follows:

Words entering State 1 end with a `one`

Words entering State 2 and 3 end with {2, . . . ,8} trailing `zeros`

Words entering State 4 end with { 1,9 . . . ,11}trailing `zeros`the words leaving the states are chosen in such a way that the concatenation of words entering a state and those leaving a state obey the dk-constraint. For example, words leaving state 1 start with a runlength of at least two zeros. Words emerging from state 2 and 3 comply with the above runlength constraints, but they also comply with the other constraints.

Words leaving state 3 have been selected such that the first (msb) bit x1, and the third bit x3 are both equal to zero. In a similar fashion, words leaving state 2 are characterized by the fact the two-tuple x1x3 does not equal 00. Obviously, the sets of words leaving state 2 or 3 have no words in common, that is, the two sets are disjoint. The attributes of the four states imply that any walk through a graph stepping from state to state, generates a dk constrained sequence by reading the words tagged to the edges that connect the states.

The encoder graph is defined in terms of three sets: the inputs, the outputs and the states, and two logical functions: the output function Ho and the next state function G().

The specific codeword, denoted by Xt, transmitted by the encoder at instant t is a function of the information word Bt that enters the encoder, but depends further on the particular state, St, of the encoder. Similarly, the next state at instant t+1 is a function of Bt and St. The output function H() and the next state function G() can be written as

Both functions are described by four lists with 256 entries as shown in FIG. 7. The first column shows the information words 0-255. The second column gives the codewords for the State 1 and the third column gives the next coding state (indicated by 1,2,3 or 4). The further columns indicate the respective states S2, S3 and S4. The coding states S1 and S4 are of a first type as described in the EFM+document. The coding states S2 and S3 are of a second type. The words are written in NRZI notation. In the first 16 rows in FIG. 7 some bits are given as an `x` (meaning don't care). This indicates, that for this bit position a 0 or 1 may be used. So two paired words are available for each information word, which differ only on one position. This degree of freedom must be used to minimize the LF content of the modulated signal, also indicated as DC control (DCC).

In the coding table of FIG. 7 words have been paired from information word 132 up to 255 in state S4 with the corresponding words in S1. As described with the DC control a word from S1 may be selected instead of the word of S4, while in coding state S4. For easy decoding the paired words in S1 should be no part of the set of S4. If common words are used in V1 and V4, the should be assigned to the same information word. This has the advantage, that a codeword can be uniquely decoded, without knowing the established state

The DC control is possible in two different ways. Firstly, if the table shows a don't care in the output table, we may use this degree of freedom to optimize the running digital sum. Secondly, if the current state is s=4 and if the runlength constraints with the previous codeword Xt-1 allow so (that is if the juxtaposition of Xt-1 and H(Bt,1) do not violate the dk-constraint). In the embodiment shown in FIG. 7 an additional feature has been accomplished by the constraint that also G(Bt,1)=G(Bt,4). This results in the same codewords being generated consecutively to the current codeword. This has the advantage, that in a system where the decision which codeword to choose for DCC is postponed, the streams of possible sequences are differing only in one location (at the current codeword).

The eases the calculation and memory requirements for the DCC unit. The alternative stream is selected, that minimizes the running digital sum of the encoded sequence. The power spectral density of the embodiment is shown in FIG. 9.

A sync pattern is added to the modulated signal regularly. The definition of a unique and reliable pattern is a 20 bit sequence x0010 00000 00000 00001. Just before the sync pattern starts, the encoder is in a certain state, say s. The actual value of the msb of the sync pattern, denoted by x, is governed by s as follows. If s=2 the x is set to 1 else x=0. After transmission of the sync pattern the encoder is preset to State 1.

For other coding tables constructed under the similar constraints it will also be possible to use paired words from S4, while in coding state S1. However with the table of FIG. 7 no words can be used, because the d,k constraints will be violated. A different coding table, with a different number of coding states of the first type or a different assignment of code words or different word lengths m and n, can be constructed in which the degree of freedom of selecting freely one of the coding states of the first type by assigning paired words can be used to improve the low-frequency properties of the modulated signal.

FIG. 8 shows a coding table with rate 8/16. So m=8 and n=16, the dk-constraints are d=2, k=10. The columns are organized as in FIG. 7, but no x symbol is used for indicating a double word, but instead a main and a substitute table are given. FIG. 8a shows the main coding table and FIG. 8b shows a separate substitute table for the information words 0-87. The codewords of the substitute table may be selected for DC control, as described in the prior art EFM+document. In this embodiment, when in state 1 or 4, according to the invention a codeword may be selected from the other state of the first type, state 4 or 1 respectively. Further sync patterns may be added. The sync patterns have a unique pattern to distinguish them easily, for example a violation of the k constraint by including a series of k+1 zeros. After a sync pattern the state is reset to a predetermined value, for example state 1.

FIG. 9 shows the results of a computer simulation of the code of FIG. 7. The Power Spectral Density is calculated against the frequency, which is given as a ratio in relation to the bit frequency. A good LF performance for the 8/15 rate code is shown by the curve.