SRAM With Stacked Capacitor Spaced From Gate Electrodes

1. A semiconductor integrated circuit device comprising: a first n-channel MISFET and a second n-channel MISFET, each having a gate electrode formed over a principal surface of a substrate; a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed over said principal surface; a first insulating film formed over said gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs; and a capacitor element formed over said first insulating film, wherein said capacitor element is comprised of a first conductive film formed over said first insulating film, a second conductive film formed over said first conductive film, and a dielectric film formed between said first conductive film and said second conductive film, wherein said first conductive film is electrically connected to a source-drain path of said first n-channel MISFET, a source-drain path of said first p-channel MISFET, and said gate electrodes of both said second n-channel MISFET and said second p-channel MISFET, and wherein said second conductive film is electrically connected to a source-drain path of said second n-channel MISFET, a source-drain path of said second p-channel MISFET, and said gate electrodes of both said first n-channel MISFET and said first p-channel MISFET.

2. A semiconductor integrated circuit device according to claim 1, wherein one of said first conductive film and said second conductive film is comprised of an n-type silicon film.

3. A semiconductor integrated circuit device according to claim 1, wherein one of said first conductive film and said second conductive film is comprised of a p-type silicon film.

4. A semiconductor integrated circuit device according to claim 1, further comprising: a capacitor, formed from same level conductive layers from which said first conductive film and said second conductive film are formed, included in an input/output protective circuit of the semiconductor integrated circuit device.

5. A semiconductor integrated circuit device according to claim 1, further comprising a dynamic random access memory having a dynamic random access memory cell, the memory cell of the dynamic random access memory having a capacitor formed from same level conductive layers from which said first conductive film and said second conductive film are formed, and wherein said first and second n-channel MISFETs and said first and second p-channel MISFETs comprise a memory cell of a static random access memory.

6. A semiconductor integrated circuit device according to claim 1, further comprising: a second insulating film formed over said second conductive film; and a third conductive film and a fourth conductive film formed over said second insulating film, wherein said third conductive film is electrically connected between said source-drain path of said first n-channel MISFET and said source-drain path of said first p-channel MISFET, and wherein said fourth conductive film is electrically connected between said source-drain path of said second n-channel MISFET and said source-drain path of said second p-channel MISFET.

7. A semiconductor integrated circuit device according to claim 1, wherein said first conductive film is electrically connected between said source-drain path of said first n-channel MISFET and said source-drain path of said first p-channel MISFET, and wherein said second conductive film is electrically connected between said source-drain path of said second n-channel MISFET and said source-drain path of said second p-channel MISFET.

8. A semiconductor integrated circuit device according to claim 7, further comprising: contact holes each formed in said first and second insulating films; and conductive films filled in said contact holes, wherein said first conductive film is electrically connected to said source-drain path of said first n-channel MISFET, said source-drain path of said first p-channel MISFET, and said gate electrodes of both said second n-channel MISFET and said second p-channel MISFET through said contact holes, and wherein said second conductive film is electrically connected to said source-drain path of said second n-channel MISFET, said source-drain path of said second p-channel MISFET, and said gate electrodes of both said first n-channel MISFET and said first p-channel MISFET through said contact holes.

9. A semiconductor integrated circuit device comprising: a first n-channel MISFET and a second n-channel MISFET, each having a gate electrode formed over a principal surface of a semiconductor substrate, and each having a source region and a drain region formed in said substrate; a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed over said principal surface, and each having a source region and a drain region formed in said substrate; a first insulating film formed over said gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETs; a first conductive film formed over said first insulating film; a second insulating film formed over said first conductive film; and a second conductive film formed over said second insulating film, wherein said first conductive film is electrically connected to the drain region of said first n-channel MISFET, the drain region of said first p-channel MISFET, and said gate electrodes of both said second n-channel MISFET and said second p-channel MISFET, and wherein said second conductive film is electrically connected to the drain region of said second n-channel MISFET, the drain region of said second p-channel MISFET, and said gate electrodes of both said first n-channel MISFET and said first p-channel MISFET; the semiconductor integrated circuit device further including structure for applying a first potential to source regions of said first n-channel MISFET and said second n-channel MISFET, and structure for applying a second potential, greater than said first potential, to source regions of said first p-channel MISFET and said second p-channel MISFET.

10. A semiconductor integrated circuit device according to claim 9, further comprising: a capacitor element comprised of said first conductive film, said second conductive film, and said second insulating film formed between said first conductive film and said second conductive film.

11. A semiconductor integrated circuit device according to claim 9, further comprising: contact holes each formed in said first and second insulating films; and conductive films filled in said contact holes, wherein said first conductive film is electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, and said gate electrodes of both said second n-channel MISFET and said second p-channel MISFET through said contact holes, and wherein said second conductive film is electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, and said gate electrodes of both said first n-channel MISFET and said first p-channel MISFET through said contact holes.

12. A semiconductor integrated circuit device comprising: a first n-channel MISFET and a second n-channel MISFET, each having a gate electrode formed over a principal surface of a semiconductor substrate, and each having a source region and a drain region formed in said substrate to form a source-drain path; a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed over said principal surface, and each having a source region and a drain region formed in said substrate to form a source-drain path; a first insulating film formed over said gate electrodes of said first and second n-channel MISFETs and said first and second p-channel MISFETS; a first conductive film formed over said first insulating film; a second insulating film formed over said first conductive film; and a second conductive film formed over said second insulating film, wherein said first conductive film is electrically connected to said source-drain path of said first n-channel MISFET, said source-drain path of said first p-channel MISFET, and said gate electrodes of both said second n-channel MISFET and said second p-channel MISFET, and wherein said second conductive film is electrically connected to said source-drain path of said second n-channel MISFET, said source-drain path of said second p-channel MISFET, and said gate electrodes of both said first n-channel MISFET and said first p-channel MISFET.

13. A semiconductor integrated circuit device according to claim 12, further comprising: contact holes each formed in said first and second insulating films; and conductive films filled in said contact holes, wherein said first conductive film is electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, and said gate electrodes of both said second n-channel MISFET and said second p-channel MISFET through said contact holes, and wherein said second conductive film is electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, and said gate electrodes of both said first n-channel MISFET and said first p-channel MISFET through said contact holes.

14. A semiconductor integrated circuit device according to claim 12, further comprising: a capacitor element, formed from same level conductive layers from which said first conductive film and said second conductive film are formed, included in an input/output protective circuit of the semiconductor integrated circuit device.

15. A semiconductor integrated circuit device according to claim 12, further comprising: a memory cell of a dynamic random access memory, having a capacitor element formed from same level conductive layers from which said first conductive film and said second conductive film are formed, wherein said first and second n-channel MISFETs and said first and second p-channel MISFETs comprise a memory cell of a static random access memory of the semiconductor integrated circuit device.

16. A semiconductor integrated circuit device comprising: a memory cell including first and second n-channel MISFETs, first and second p-channel MISFETS, and first and second transfer MISFETs, wherein said first and second n-channel MISFETs are arranged, in a first direction, between said first and second transfer MISFETs and said first and second p-channel MISFETs, wherein said first n-channel MISFET is arranged, in a second direction perpendicular to said first direction, adjacent to said second n-channel MISFET, wherein gate electrodes of said first and second n-channel MISFETs, said first and second p-channel MISFETs and said first and second transfer MISFETs are formed over a principal surface of a semiconductor substrate, wherein source and drain regions of said first and second n-channel MISFETs, said first and second p-channel MISFETs and said first and second transfer MISFETs are formed in said semiconductor substrate, wherein the drain region of said first n-channel MISFET is electrically connected to the drain region of said first p-channel MISFET, one of the source and drain regions of said first transfer MISFET, and the gate electrodes of said second n-channel MISFET and said second p-channel MISFET, and wherein the drain region of said second n-channel MISFET is electrically connected to the drain region of said second p-channel MISFET, one of the source and drain regions of said second transfer MISFET, and the gate electrodes of said first n-channel MISFET and said first p-channel MISFET; a word line extending in said second direction over said principal surface and electrically connected to said gate electrodes of said first and second transfer MISFETs; a first insulating film over said word line, and over said gate electrodes of said first and second n-channel MISFETs, said first and second p-channel MISFETs and said first and second transfer MISFETs; and a capacitor element formed over said first insulating film, wherein said capacitor element is comprised of a first conductive film over said first insulating film, a second conductive film over said first conductive film, and a dielectric film between said first conductive film and said second conductive film, wherein said first conductive film is electrically connected to the drain region of said first n-channel MISFET, wherein said second conductive film is electrically connected to the drain region of said second n-channel MISFET, wherein said first conductive film and said second conductive film extend over a portion of said principal surface, in said first direction, between said first and second n-channel MISFETs and said first and second transfer MISFETs, and wherein said first conductive film and said second conductive film extend over a portion of said principal surface, in said first direction, between said first and second n-channel MISFETs and said first and second p-channel MISFETs.

17. A semiconductor integrated circuit device according to claim 16, wherein said first conductive film and said second conductive film extend over said word line.

18. A semiconductor integrated circuit device according to claim 16, wherein the first and second n-channel MISFETs are first and second driver MISFETS, respectively, and the first and second p-channel MISFETs are first and second load MISFETs, respectively, of the memory cell.

19. A semiconductor integrated circuit device according to claim 18, wherein the first and second transfer MISFETs are third and fourth n-channel MISFETs, respectively.

20. A semiconductor integrated circuit device comprising: a memory cell including first and second driver MISFETs, first and second load MISFETs, and first and second transfer MISFETs, wherein gate electrodes of said first and second driver MISFETs, said first and second load MISFETs and said first and second transfer MISFETs are formed over a principal surface of a semiconductor substrate, wherein source and drain regions of said driver MISFETs, said load MISFETs and said transfer MISFETs are formed in said semiconductor substrate, wherein said drain region of said first driver MISFET is electrically connected to said drain region of said first load MISFET, one of said source and drain regions of said first transfer MISFET, and said gate electrodes of said second driver MISFET and said second load MISFET, and wherein said drain region of said second driver MISFET is electrically connected to said drain region of said second load MISFET, one of said source and drain regions of said second transfer MISFET, and said gate electrodes of said first driver MISFET and said first load MISFET; a first insulating film formed over said gate electrodes of said driver MISFETs, said load MISFETs and said transfer MISFETs; and a capacitor element formed over said first insulating film, wherein said capacitor element is comprised of a first conductive film formed over said first insulating film, a second conductive film formed over said first conductive film, and a dielectric film formed between said first conductive film and said second conductive film, wherein said first conductive film is electrically connected to said drain region of said first driver MISFET, and wherein said second conductive film is electrically connected to said drain region of said second driver MISFET.

21. A semiconductor integrated circuit device according to claim 20, wherein the device further includes a peripheral circuit, and wherein a capacitor element, formed from same level conductive layers from which said first conductive film and said second conductive film are formed, is formed in the peripheral circuit.

22. A semiconductor integrated circuit device according to claim 20, wherein the device further includes a peripheral circuit, and wherein MISFETs constituting the peripheral circuit, and metal wiring lines formed over said second conductive film, are electrically connected through pad layers formed from same level conductive layers from which said first conductive film and said second conductive film are formed.

23. A semiconductor integrated circuit device according to claim 20, wherein said first and second driver MISFETs are arranged, in a first direction, between said transfer MISFETs and said load MISFETs, wherein said first driver MISFET is arranged, in a second direction perpendicular to said first direction, adjacent to said second driver MISFET, wherein said first conductive film and said second conductive film extend over a portion of said principal surface, in said first direction, between said driver MISFETs and said transfer MISFETs, and wherein said first conductive film and said second conductive film extend over a portion of said principal surface, in said first direction, between said driver MISFETs and said load MISFETs.

24. A semiconductor integrated circuit device according to claim 20, further comprising: a word line extending over said principal surface and electrically connected to said gate electrodes of said transfer MISFETs; wherein said first insulating film is formed over said word line, and wherein said first conductive film and said second conductive film extend over said word line.

25. A semiconductor integrated circuit device according to claim 20, wherein said first conductive film extends over said gate electrodes of said first driver MISFET and of said transfer MISFETs, and wherein said second conductive film extends over said gate electrodes of said second driver MISFET and of said transfer MISFETs.

26. A semiconductor integrated circuit device according to claim 25, wherein said driver MISFETs are arranged, in a first direction, between said transfer MISFETs and said load MISFETs, and wherein said first driver MISFET is arranged, in a second direction perpendicular to said first direction, adjacent to said second driver MISFET.

27. A semiconductor integrated circuit device comprising: a memory cell including a flip-flop circuit having a pair of driver MISFETs and a pair of load MISFETs electrically connected so as to provide the flip-flop circuit, and a pair of transfer MISFETs electrically connected to the flip-flop circuit so as to provide the memory cell, with two storage nodes being provided respectively by two input/output terminals of the flip-flop circuit, wherein gate electrodes of said driver MISFETs, said load MISFETs and said transfer MISFETs are formed over a principal surface of a semiconductor substrate; a first insulating film formed over said gate electrodes of said driver MISFETs, said load MISFETs and said transfer MISFETs; and a capacitor element formed over said first insulating film, wherein a pair of electrodes of said capacitor element is comprised of a first conductive film formed over said first insulating film and a second conductive film formed over said first conductive film, wherein a dielectric film of said capacitor element is formed between said first conductive film and said second conductive film, wherein one electrode of said capacitor element and one storage node of said flip-flop circuit are electrically connected to each other, and wherein the other electrode of said capacitor element and the other storage node of said flip-flop circuit are electrically connected to each other.

28. A semiconductor integrated circuit device according to claim 27, wherein the device further includes a peripheral circuit, and wherein a capacitor element, formed from same level conductive layers from which said first conductive film and said second conductive film are formed, is formed in the peripheral circuit.

29. A semiconductor integrated circuit device according to claim 27, wherein the device further includes a peripheral circuit, and wherein MISFETs constituting the peripheral circuit, and metal wiring lines formed over said second conductive film, are electrically connected through pad layers formed from same level conductive layers from which said first conductive film and said second conductive film are formed.

30. A semiconductor integrated circuit device according to claim 27, further comprising: a word line extending over said principal surface and electrically connected to said gate electrodes of said transfer MISFETs; wherein said first insulating film is formed over said word line, and wherein said first conductive film and said second conductive film extend over said word line.

31. A semiconductor integrated circuit device according to claim 21, wherein said first dielectric film is formed over the gate electrodes of said pair of driver MISFETs, the gate electrodes of said pair of transfer MISFETs and the gate electrodes of said pair of load MISFETs, and wherein said second conductive film is formed over said first dielectric film.

32. A semiconductor integrated circuit device according to claim 26, wherein a reference voltage line for feeding a reference voltage to source regions of said pair of driver MISFETs and a power voltage line for feeding a power voltage to source regions of said pair of load MISFETs are comprised of said first metal film.

33. A semiconductor integrated circuit device according to claim 27, wherein one of said pair of driver MISFETs is arranged, in a first direction, between one of said pair of transfer MISFETs and one of said pair of load MISFETs, wherein said pair of driver MISFETs are arranged, in a second direction perpendicular to said first direction, adjacent to each other, wherein said first conductive film and said second conductive film extend over a portion of said principal surface, in said first direction, between said pair of driver MISFETs and said pair of transfer MISFETs, and wherein said first conductive film and said second conductive film extend over a portion of said principal surface, in said first direction, between said pair of driver MISFETs and said pair of load MISFETs.

34. A semiconductor integrated circuit device according to claim 31, further comprising: a word line extending in said second direction over said principal surface and electrically connected to said gate electrodes of said transfer MISFETs; wherein said first insulating film is formed over said word line, and wherein said first conductive film and said second conductive film extend over said word line.

35. A semiconductor integrated circuit device according to claim 27, wherein said first conductive film is formed at least over said gate electrode of one of said driver MISFETs and over said gate electrodes of said transfer MISFETs, and wherein said second conductive film is formed at least over said gate electrode of the other of said driver MISFETs and over said gate electrodes of said transfer MISFETs.

36. A semiconductor integrated circuit device according to claim 31, wherein said driver MISFETs are formed between said transfer MISFETs and said load MISFETs in a first direction, when viewed from above, and wherein both said first and second conductive films are formed over a region of said principal surface between said driver MISFETs and said load MISFETs.

37. A semiconductor integrated circuit device according to claim 35, wherein both said first and second conductive films are formed over said load MISFETs.

38. A semiconductor integrated circuit device according to claim 35, wherein said first dielectric film is formed over the gate electrodes of said pair of driver MISFETs, the gate electrodes of said pair of transfer MISFETs and the gate electrodes of said pair of load MISFETs, and wherein said second conductive film is formed over said first dielectric film.