US 5,778,246 AGrant
Method and Apparatus for Efficient Propagation of Attribute Bits in an Instruction Decode Pipeline
Issue Date:1998-07-07
•15 Claims
•10 Drawing Sheets
Abstract
A method and apparatus for efficient propagation of attribute bits in an instruction decoding pipeline. Attribute bits associated with instructions are manipulated in a like manner to the instructions in an instruction decode pipeline. The pipeline has three pipe stages. Some of the attribute bits are generated in the first pipe stage but not used until the third pipe stage. A prefetch buffer stores prefetched instruction bytes. Attribute bits for each prefetched instruction byte are generated and stored in an attribute buffer in locations corresponding to the instruction bytes stored in the prefetch buffer. A code rotator selects two sequential instructions from the prefetch buffer and stores them in an instruction FIFO for later decoding and execution in the pipeline. In like manner and in parallel, an attribute rotator selects two sets of attribute bits corresponding to the selected instructions and stores them in the instruction FIFO. The attribute bits control certain operations in the decoding and execution of the selected instructions.
Metadata
Assignee
- Intel Corporation
Inventor
- Bob Brennan
Application Information
Application Number:US 579420&
Filing Date:1995-12-27
Priority Date:1995-12-27
Art Unit:232
Classifications
IPC:
G06F 1204
Field of Search:
395389;386;391;388;800.23;383;800.41;380
Patent Drawings (10 sheets)
Description
Related Applications
This patent application is related to the following patent application which is assigned to the assignee of the present invention and filed concurrently herewith: patent application Ser. No. 08/579,419, entitled Fast Decoding of 00H and 0FH Mapped Instructions.
Background of the Invention
1. Field of the Invention
The present invention relates generally to handling of attribute bits associated with instructions of a microprocessor, and more specifically to an efficient method for propagating status bits in an instruction decoder pipeline of a microprocessor.
2. Related Art
Microprocessors execute a defined set of instructions. Individual instructions are represented by a unique binary encoding called an opcode. The microprocessor fetches, decodes, and executes the instructions. The fetch, decode, and execute operations are often pipelined to increase the performance of the processor. Increasing the performance of a processor may require changing the microarchitecture to improve the balance of the pipeline.
For example, the instruction decode pipeline of today's commercially available Pentium.RTM. processors (available from Intel Corporation, Santa Clara, Calif.) is illustrated in block diagram form in FIG. 2. Pentium processors have a dual-pipeline superscalar architecture. To keep the dual execution pipelines optimally full, the instruction decoders must decode and issue two instructions per clock cycle. The prior instruction decode pipeline of FIG. 2 has prefetch and decode stages. In the prefetch stage, instruction bytes are prefetched from instruction cache 12. From the prefetched instruction bytes, two instructions are selected and aligned in the U and V pipelines based on the instruction pointer and an end bit indication of the first instruction. In the decode stage of the pipeline, U and V pipe instruction decoders 24 and 25 determine the length of the instructions and decode them to issue two macroinstruction vectors to the execution units of the processor.
If the time required to complete the tasks of each pipeline stage are not roughly equal, the entire pipeline is slowed down to the speed of the slowest pipeline stage. A pipeline is said to be unbalanced if some of the pipeline stages require significantly more time to complete their tasks than others. One way to improve the balance pipeline is to split very long pipeline stages into multiple stages. In this manner, the operational frequency of the processor can be increased to improve processor performance.
One way to increase the performance of Pentium processors would be to split the prefetch stage of the instruction decoder pipeline. For example, the prefetch stage could be split into prefetch and fetch stages.
Other optimizations of the pipeline could also be made. Attribute bits associated with the instructions may be generated in different pipeline stages. In general, attribute bits are used to control the flow of instructions through a processor's pipeline. Attribute bits can assist in various fetch, decode, and execute operations. Speeding up the handling and propagation of status bits in an instruction decode pipeline can improve the overall performance of the processor.
FIG. 1 illustrates the components of instructions used in Intel architecture processors. As shown in FIG. 1, an instruction may consist of several variable length fields. An instruction may include from zero to fifteen bytes of prefix information, one or two bytes of opcode information, zero or one byte of Mod R/M information (indicates which registers are to be used), zero or one byte of SIB (scaled index base) information, zero, one, two, or four bytes of displacement information, and zero, one, two, or four bytes of immediate information. Instructions of Intel architecture processors can vary from one to fifteen bytes in length. Further details of the instruction format of Intel architecture processors are found in chapter 25 of the publication entitled Pentium Processor User's Manual; Volume 3: Architecture and Programming Manual, Intel Corporation 1995, which is incorporated herein by reference. The variable length instructions of Intel architecture processors are furnished to the processor as a sequential stream of bytes in which no instruction is differentiated from any other.
Length decoding is an important part of decoding variable length instructions. For example, i486.TM. processors and earlier Intel architecture processors fetch an instruction based on an instruction pointer, decode the instruction for execution, and determine the length of the instruction. The instruction length is then added to the instruction pointer to point to the next instruction to be fetched and decoded. Thus, i486 processors and earlier Intel architecture processors fetch and decode instructions serially incrementing the instruction pointer by the last decoded instruction length to point to the next instruction.
Today's commercially available Pentium.RTM. processors have a dual-pipeline superscalar architecture. To optimally keep the dual execution pipelines busy the instruction decoder needs to decode and issue two instructions simultaneously per clock cycle. However, to select the correct starting point for a second (or next) instruction, the instruction decoder must know where the first instruction ends. In addition, in order to properly increment the instruction pointer, the instruction decoder must also know where the second instruction ends.
FIG. 2 illustrates a block diagram of a prior arrangement for indicating the length of instructions in the prefetch pipeline stage without decoding the length of the instructions until a later decode pipeline stage. This arrangement is described in detail in U.S. Pat. No. 5,450,605, entitled End Bit Markers For Instruction Decode, E. Grochowski et al, and assigned to the assignee of the present invention which is incorporated herein by reference. In the prior arrangement, instructions are decoded and executed in a pipeline that consists of prefetch, decode, and execute stages. The prefetch stage prefetches sequential instruction bytes from storage and aligns two sequential instructions for decoding based on the instruction pointer and an end bit indication of the end of the first instruction. In the next clock cycle the decode stage decodes the type and actual length (or end) of the two instructions.
End bit cache 14 stores an end bit corresponding to each byte of code stored in instruction cache 12. An end bit value of `1` indicates the end of an instruction. Since no determination of instruction length is made in the prefetch stage, new instruction bytes stored in instruction cache 12 are speculatively assigned a length of one byte. In other words, the corresponding end bits of all new instruction bytes loaded into instruction cache 12 are set to `1`.
In the prefetch stage rotators 15 and 20 select two sequential instructions for decoding based on the instruction pointer and the end bit of the first instruction. If later, in the decode stage, the U pipe instruction decoder 24 determines that the end bit indication for the first instruction was incorrect, the second instruction in the V pipe instruction decoder 25 is canceled because the starting pointer of the second instruction (based on the incorrect first instruction end bit indication) was incorrect. Incorrect end bits for instructions in the U pipe are later corrected by end bit update circuit 29 based on the instruction length decoding done in the decode stage of the pipeline. Thus, FIG. 2 shows an arrangement for indicating the length of instructions without the need to decode the instruction length before decoding the type of instruction. However, the arrangement incurs clock penalties in decoding instructions that are longer than one byte.
FIG. 3 is a block diagram of U pipe instruction decoder 24. U pipe instruction decoder 24 includes an instruction decoder that receives an instruction and determines the appropriate macroinstruction vector to be issued to the execution units. A 00H page length decoder is optimized to decode lengths of instructions mapped to the 00H opcode page and a selected few 0FH-mapped instructions in one clock cycle. 0FH length decoding logic decodes the length of 0FH-mapped instructions in two or more clock cycles, thereby introducing delays into the decoding pipeline for most 0FH-mapped instructions. For the purposes of this discussion, V pipe instruction decoder 25 is essentially the same as U pipe instruction decoder 24 (FIG. 2).
Thus, the prior instruction decoder of FIG. 2 incurs clock penalties in the prefetch stage when end bit indications are incorrect. This is always the case for new instructions that are more than one byte long, such as 0FH-mapped instructions. Additional clock penalties are incurred in the decode stage for most 0FH-mapped instructions because the 0FH length decoders of instruction decoders 24 and 25 take two or more clock cycles to decode 0F instructions.
As discussed above, the performance of the prior instruction decoder of FIG. 2 could be improved by splitting the prefetch pipe stage into prefetch and fetch stages so that the instruction decode pipeline has prefetch, fetch, and decode stages. Splitting the prefetch stage creates problems in handling attribute bits that are generated in the prefetch stage but not used until the decode stage. In addition, the propagation of attribute bits in the pipeline can be optimized to allow increased performance.
Therefore, a method and apparatus for efficient propagation of attribute bits in an instruction decoding pipeline is needed.
Summary of the Invention
In one embodiment, the present invention is implemented in an instruction decode pipeline. The pipeline decodes instructions which appear in an instruction stream without differentiation. Each instruction includes one or more instruction blocks. An instruction path of the pipeline extracts first and second instructions from a first plurality of instruction blocks. An attribute bit decoder generates a first plurality of attribute bits that correspond to the first plurality of instruction blocks. An attributes path selects first and second attribute bits that correspond to the first and second instructions. The first and second attribute bits control one or more operations in decoding the first and second instructions. In this manner, the present invention efficiently propagates attribute bits associated with instructions in the instruction decode pipeline of a processor.
Brief Description of the Drawings
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.
FIG. 1 illustrates the components of instructions used in Intel architecture processors.
FIG. 2 illustrates a block diagram of a prior arrangement for indicating the length of instructions in the prefetch pipeline stage without decoding the length of the instructions until a later decode pipeline stage.
FIG. 3 is a block diagram of U pipe instruction decoder 24 and V pipe instruction decoder 25 of FIG. 2.
FIG. 4 is a block diagram of one embodiment of the present invention having parallel sets 35 of 0FH detectors 36, 0FH shifters 38, and length decoders 40.
FIG. 5 is a detailed block diagram of one embodiment of prefetch buffer 32 and block 35 (the parallel 0FH detectors, 0FH shifters, and length decoders) of FIG. 4.
FIG. 6 is a block diagram showing, in one embodiment, a one-to-one correspondence between instruction bytes stored in prefetch buffer 32, length values stored in length buffer 44, 0F bits stored in 0FH buffer 46, and attribute bits stored in attribute buffer 62.
FIG. 7 is a block diagram of an embodiment of the present invention having parallel 00H/0FH PLAs 37 that incorporate 0FH detection, 0FH shifting, and length decoding in the PLAs.
FIG. 8 is a detailed block diagram of one embodiment of the parallel 00H/0FH PLAs 37 of FIG. 7.
FIG. 9 illustrates the instruction information stored in instruction FIFO 66 in one embodiment.
FIG. 10 illustrates an example operation of one embodiment of the instruction decoder of the present invention.
FIG. 11 is a flowchart of one embodiment of the present invention method for fast decoding of 00H and 0FH-mapped instructions.
Detailed Description of the Present Invention
A method and apparatus for efficient propagation of attribute bits in an instruction decoding pipeline is described. In the following description, numerous specific details such as instruction lengths in byte increments, numbers and arrangement of parallel decoders, bit formats, instruction formats, positions of opcode page pointer (0FH) bytes, length decoding schemes, and instruction rotation or selection schemes are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods and circuits are shown in block diagram form in order not to obscure the present invention.
Intel architecture instructions are variable length and appear in an instruction stream without differentiation. Each instruction is made up of one or more instruction bytes. However, the present invention may be applied to decoding instructions having other size instruction blocks. For purposes of this description, instructions are described as appearing in the instruction stream from most significant byte to least significant byte. However, the invention is not limited to this instruction ordering.
Length Decoding
FIG. 4 is a block diagram of one embodiment of the present invention instruction decoder having parallel sets 35 of 0FH detectors 36, 0FH shifters 38, and length decoders 40. The instruction pipeline has three stages that are important to an understanding of the present invention: prefetch, fetch, and decode. During the prefetch stage instruction bytes are prefetched from instruction cache 30 and stored in prefetch buffer 32. Attribute bits for the prefetched instruction bytes are generated and stored in corresponding locations in attribute buffer 62.
During the fetch stage, lengths of instructions embedded in the prefetched instruction bytes are determined and stored in corresponding locations in length buffer 44. 0FH detectors 36 generate bits indicating whether the prefetched instruction bytes are 0FH bytes and store the 0F bits in corresponding locations in 0FH buffer 46. Therefore, each instruction byte stored in prefetch buffer 32 has a corresponding length indication in length buffer 44, a corresponding 0F bit in 0FH buffer 46, and a corresponding set of attribute bits in attribute buffer 62. Finally, the code rotator 48 parses the instruction bytes in the prefetch buffer to Is provide up to two instructions per clock cycle to instruction FIFO 66. In a corresponding manner, length rotator 50, 0FH rotator 52, and attribute rotator 64 provide corresponding length values, 0F bits, and attribute bits for up to two instructions per clock cycle to the instruction FIFO 66. FIG. 9 shows the information stored for each instruction in the instruction FIFO 66 in one embodiment. Prefix information is decoded separately. An understanding of the decoding and handling of prefix information is not necessary to an understanding of the present invention.
In the decode stage, instruction FIFO 66 provides two instructions and associated length, 0F, and attribute information to instruction decoder 68. Instruction decoder 68 includes a U pipe instruction decoder and a V pipe instruction decoder that decode the instructions and issue the appropriate macroinstruction vectors to the execution units of the processor. Note that no length decoding occurs in the decode stage of the pipeline in contrast to the prior instruction decoder arrangement of FIG. 2.
Instruction cache 30 stores copies of instructions that are fetched from external memory for execution by the microprocessor. In one embodiment instruction cache 30 is 16K byte SRAM with a 32-byte line length. Instruction cache 30 provides sixteen instruction bytes per clock cycle to prefetch buffer 32 and block 35. Of course, other sizes or types of instruction cache can be used and other numbers of instruction bytes can be provided.
Prefetch buffer 32 stores instruction bytes that have been prefetched from instruction cache 30, or other storage locations. FIGS. 5 shows one embodiment of prefetch buffer 32. In this embodiment, prefetch buffer 32 has four lines A, B, C, and D, each having sixteen bytes of storage. Of course, other sizes or arrangements of prefetch buffers can be used. For purposes of describing the present invention, the order of storing instruction bytes from an instruction stream in prefetch buffer 32 is line A, positions A0 to A15, then line B, positions B0 to B15, then line C, positions C0 to C15, then line D, positions D0 to D15, and then returning to line A again.
Returning to FIG. 4, parallel 0FH detectors 36, parallel 0FH shifters 38, and parallel length decoders 40 provide fast length decoding of the instruction bytes received from instruction cache 30. In one embodiment, the length decoders 40, 0FH detectors 36, and 0FH shifters 38 are arranged so that each length decoder 40 has a corresponding detector 36 and shifter 38. Note that in the present invention instruction length decoding occurs before the instructions are decoded in the decode stage of the pipeline for later execution in the execution stage of the pipeline.
In one embodiment 0FH detectors 36 determine whether a set of instruction bytes are 0FH bytes. Recall that in the Intel architecture 0FH-mapped instructions have 0FH as their most significant opcode byte. The 0FH bytes is a pointer to the 0FH opcode page. 0FH detectors 36 generate a set of 0F signals (i.e., detector signals) that indicate whether the corresponding instruction bytes are 0FH (i.e., point to a secondary opcode page). In one embodiment, a 0F signal is set to `1` if the corresponding instruction byte is 0FH and to `0` for any other value. In other embodiments, the 0F signal can have other values. In one embodiment 0FH detectors 36 are comparators implemented with combinational logic. In other embodiments, other types of detectors could be used. In association with other instruction sets, other embodiments of the detectors would detect other types of pointers to various opcode pages. The pointers may also occur in other positions within an instruction. In yet another embodiment, other types of instruction blocks that contain no length information are detected.
The length of Intel architecture instructions can be determined by decoding the most significant nineteen bits of 00H page instructions and the first nineteen bits after the 0FH opcode byte of 0FH instructions. In other words, lengths of Intel architecture instructions can be determined by decoding nineteen sequential bits starting with the most significant byte of 00H page instructions or starting with the byte following the 0FH opcode byte for 0FH page instructions. Therefore, for Intel architecture instructions four sequential instruction bytes can be decoded to determine the length of any instruction if the most significant opcode byte is the most significant byte of the four bytes. For example, assume a four byte instruction window 3:0! where position0! is the most significant position. If byte0! is not 0FH, then bytes 2:0! are sufficient to decode the length of a 00H mapped instruction whose most significant opcode byte is in position0!. If byte0! is 0FH, then bytes 3:1! are sufficient to decode the length of a 0FH mapped instruction whose most significant opcode byte is in position0!.
In accordance with the above length decoding scheme, in one embodiment of the present invention each 0FH shifter 38 receives four sequential instruction bytes from instruction cache 30. In one embodiment, instruction cache 30 provides sixteen instruction bytes and there are sixteen corresponding 0FH shifters 38, each 0FH shifter 38 arranged to receive a corresponding instruction byte along with the next three instruction bytes (for example, see FIG. 5). The three sequential bytes including the most significant byte (i.e., bytes 2:0! of the four byte window) are selected if the corresponding 0FH detector 38 does not detect a 0FH byte in the most significant byte. The three sequential bytes not including the most significant byte (i.e., bytes 3:1 ! of the four byte window) are selected if the corresponding 0FH detector 38 detects a 0FH byte in the most significant byte. This ordering of 0FH detection and instruction byte selection is further illustrated in FIG. 5. 0FH shifters 38 can be implemented using a mux, a shifter, or other circuitry for performing a shifting function.
In association with other instruction sets or other length decoding schemes the detectors 36 and shifters 38 may be arranged in other ways. In any case, the operation of the detectors 36 and shifters 38 is to detect pointers to alternate opcode page(s) (or other types of instruction blocks that contain no instruction length information) and remove the pointer(s) (or other blocks) from the instruction blocks to achieve faster length decoding. Since opcode page pointer(s) contain no length information, removing opcode page pointers before length decoding allows the length decoder to be optimized. In other embodiments, the opcode pointers may be bit(s) or other values and may occur in other positions of the instruction encoding.
Each parallel length decoder 40 receives the instruction bytes selected by the corresponding 0FH shifter 38 and a 0F signal from the corresponding 0FH detector 36. If the selected instruction bytes correspond to an instruction length the length decoder 40 will determine the length of the instruction and store it in a corresponding location in length buffer 44. If no real instruction length is determined, length decoders 40 generate a length of 1 to 11 (based on the random arrangement of the bytes) which is eventually flushed by illegal instruction logic in the decode stage. In one embodiment, the length 40 are individual length decoder PLAs optimized to perform length decoding of 00H and 0FH-mapped instructions. In this embodiment, each length decoder PLA 40 is combined with a separate 0FH shifter 38 and a 0FH detector 36 to allow the length decoder PLAs to be optimized for size. Performing the 0FH detecting and 0FH shifting separately from the length decoder PLAs, as shown in FIGS. 4 and 5, advantageously reduces the size of the length decoder PLAs by about 50%. In other embodiments the length decoders 40 could be implemented using combinational logic, or a PLD (programmable logic device).
Referring to FIG. 5, a detailed block diagram of one embodiment of prefetch buffer 32 and block 35 of FIG. 4 is illustrated. Block 35 includes sixteen parallel sets of 0FH detectors, 0FH shifters, and length decoders. Prefetch buffer 32 is shown with each storage byte labeled to identify the correspondence between the bytes stored in prefetch buffer 32 and the bytes being detected, shifted, and length decoded by block 35. Block 35 is illustrated as operating on instruction bytes corresponding to lines B and C at a time when line C is being loaded from instruction cache 30. In like manner block 35 operates in turn on instruction bytes corresponding to lines C and D, lines D and A, and lines A and B when lines D, A, and B are loaded, respectively.
Refer to length decoder.sub.-- 0 of FIG. 5 and its associated 0FH detector and 0FH shifter logic. Detector/shifter/length decoder set.sub.-- 0 receives bytes3:0! of the currently prefetched line (line C is illustrated as the currently prefetched line so bytes C3:CO! are received). The 0FH detector determines whether byteC0! is 0FH and generates a detector signal 0F:0 accordingly. The mux (shifter) selects bytes C3:C1! if 0FH is detected, thereby shifting out the 0FH byte. The mux selects bytes C2:CO! if 0FH is not detected. The length decoder.sub.-- 0 decodes the three selected bytes to generate a length value L0.
Referring to FIG. 4, length decoders 40 store their length indications in length buffer 44 in locations that correspond to the locations of the corresponding instruction bytes in prefetch buffer 32. Likewise, 0F detectors 36 store their 0F bits or signals in corresponding locations in 0FH buffer 46.
FIG. 7 is a block diagram of an embodiment of the present invention having parallel 00H/0FH PLAs 37 that incorporate 0FH detection, 0FH shifting, and length decoding. In this embodiment the functions of 0FH detection, 0FH shifting, and length decoding are all included in the parallel PLAs 37. The overall operation of parallel PLAs 37 is identical to that of block 35 of FIG. 4. This embodiment allows the PLAs 37 to be optimized for speed to be faster than the embodiment of block 35 of FIG. 5. However, incorporating the additional functions makes the PLAs 37 about twice as big as the PLA length decoders that can be used with the embodiment of FIG. 5.
FIG. 8 is a detailed block diagram of one embodiment of the parallel 00H/0FH detect/shift/length decode PLAs 37 of FIG. 7. In accordance with the already-described length decoding scheme, each PLA receives four bytes of the currently prefetched line and performs 0FH detection, 0FH shifting, and length decoding as described above.
FIG. 11 is a flowchart of one embodiment of the present invention method for fast decoding of 00H and 0FH-mapped instructions. The method is explained in connection with the embodiment of FIG. 4. However, in general the method performs the steps of: 1) receiving a sufficient number of instruction bytes to decode the length of an instruction where some of the instruction bytes may contribute no instruction length information; 2) detecting and removing (shifting out) the bytes that contribute no length information; and 3) decoding the remaining instruction bytes to determine the length of instruction(s) embedded in the stream of instructions. FIG. 11 illustrates the case where the 0FH opcode bytes of the Intel architecture instruction set contribute no length information and are shifted out before length decoding. As explained above, this novel technique can be use to improve the speed and size of the length decoders.
At step 120 of FIG. 11, during a prefetch stage of the pipeline a line of sequential instruction bytes are prefetched from instruction cache 30 and stored in prefetch buffer 32.
At step 122, during a subsequent fetch stage of the pipeline the method detects instruction bytes that may contribute no length information (such as 0FH opcode bytes) are present in the prefetched line. A set of 0F bits are generated and stored in 0FH buffer 46. At step 124, still in the fetch stage, shifters 38 select either bytes 2:0! or bytes 3:1! of overlapping "windows" of four instruction bytes depending on the associated 0F bit indication for byteO! of each window. In this manner, the method removes 0FH opcode bytes that contribute no length decoding information. At step 126, still in the fetch stage, length decoders 40 perform length decoding on each of the selected three-byte sets. The associated 0F bits are used to speed up the length decoders. The length values are stored in length buffer 44.
At steps 128 and 130, still in the fetch pipeline stage, code rotator 48 selects a first and second instructions from the prefetched line of instruction bytes based on the prefetch instruction pointer and the first instruction length. If present, 0FH opcode bytes are shifted out of each instruction before the instruction bytes are stored in an instruction field in instruction FIFO 66. The corresponding 0F bits and length values are stored in 0F and length fields, respectively, in the instruction FIFO 66.
At step 132, the first and second instructions and associated 0F bits and length values are sent to instruction decoder 68. Instruction decoder 68 decodes the type of instructions and issues appropriate macroinstruction vectors to the execution units of the processor.
Attribute Path
Return to the prefetch stage of the instruction pipeline of FIG. 4. In one embodiment, for each instruction byte prefetched from instruction cache 30 four attribute bits are generated and stored in attribute buffer 62. In general, attribute bits control how the instructions flow down the instruction decode pipeline (i.e., control how the instructions are handled or executed in the pipeline). The attribute bits generated in this embodiment are defined in Table 1.
For branch instructions, branch target buffer 54 predicts if branches will be taken and what the offsets will be. Attribute bits decoder 58 receives this information and generates a predicted branch taken bit and a predicted bit for corresponding instruction bytes. In one embodiment, the predicted bit and predicted branch taken bit of the least significant instruction byte are used to tell other units in the pipeline that the branch target buffer has predicted a branch to be taken or not taken. For example the bits can control branch verification logic in the execution stage of the pipeline.
Paging unit 56 generates a paging violation signal for each sixteen byte line in instruction cache 30. Attribute bit decoder 58 receives the paging violation signal and generates a paging violation bit for each prefetched instruction byte of the currently prefetched line. For example, in one embodiment if a paging violation signal for a line is `1` the attribute bit corresponding to each instruction byte in the prefetched line is set to `1`. A paging valid bit set to `1` causes the pipeline to be flushed because the associated instruction code stream accesses a page not present in memory.
Instruction cache 30 generates two i-cache valid signals for each prefetched sixteen byte line, one for the high eight bytes 15:8! and one for the low eight bytes 7:0!. Attribute bit decoder 58 turns the high i-cache valid signal into eight valid bits 15:8! each having the same value as the high i-cache valid signal. Likewise the low i-cache valid signal is used to generate eight valid bits 7:0! having the same value as the low i-cache valid signal. Attribute bits decoder 58 stores the attribute bits in locations in the attribute buffer 62 corresponding to the currently prefetched line of prefetch buffer 32. In one embodiment, the valid bits of the fourth instruction byte and last instruction byte of an instruction determine whether the instruction code stream is valid. Based on the valid bits, invalid instructions in the pipeline are canceled.
Because some of the attribute bits are generated in the prefetch stage but not used until the decode stage, in one embodiment the present invention instruction decoder advantageously stores the attributes in attribute buffer 62 in locations corresponding to their associated instruction bytes in prefetch buffer 32. FIG. 6 is a block diagram showing, in one embodiment, the one-to-one correspondence between instruction bytes stored in prefetch buffer 32, length values stored in length buffer 44, 0F bits stored in 0FH buffer 46, and attribute bits stored in attribute buffer 62. The instruction bytes, length values, 0F bits, and attribute bits are manipulated in a corresponding manner by the instruction decode logic such that their one-to-one correspondence is maintained.
Returning now to the fetch stage, in one embodiment code rotator 48 parses instruction bytes in the prefetch buffer 32 in four rotation stages to provide up to two instructions per clock cycle to instruction FIFO 66. In the first rotation stage, code rotator 48 selects a thirty-two byte window based on the prefetch pointer from the previous clock cycle. In the second rotation stage, code rotator 48 selects fourteen bytes of the thirty-two bytes based on the prefetch pointer from the current clock cycle. In the third rotation stage, code rotator 14 selects either bytes 13:0! or bytes 13:1! of the fourteen bytes depending on the value of the 0F bit corresponding to byte 0!. Thus, the third stage shifts out the 0FH byte if the first instruction is a 0FH-mapped instruction. In the fourth rotation stage, the second instruction is selected based on the length of the first instruction. The fourth stage also shifts out the 0FH byte if the second instruction is a 0FH-mapped instruction (as indicated by the corresponding 0F bit).
Rotators for performing the first and second stage rotation are described in detail in U.S. patent application Ser. No. 08/276,089, entitled Two Stage Window Multiplexors For Deriving Variable Length Instructions From A Stream Of Instructions, E. Grochowski, and assigned to the assignee of the present invention, which is incorporated herein by reference. In one embodiment the third and fourth stages of rotation are implemented using multiplexors. In another embodiment shift registers are used.
In one embodiment, length rotator 50, 0FH rotator 52, and attribute rotator 64 each include first, second, and fourth rotation stages that operate on length buffer 44, 0F buffer 46, and attribute buffer 62, respectively, in a manner similar to the first, second, and fourth stages of code rotator 48. In this manner, length values, 0F bits, and attribute bits corresponding to the first and second instructions are selected and sent to instruction FIFO 66. However, length rotator 50, 0FH rotator 52, and attribute rotator 64 do not include the third rotation stage to shift out information corresponding to 0FH bytes of 0FH-mapped instructions. Nor do they shift out information corresponding to 0FH opcode bytes of the second instruction in the fourth rotation stage.
Example
FIG. 10 illustrates an example operation of the instruction decoder of the present invention. The processing of the following sequence of instructions by the present invention instruction decoder is illustrated.
The example of FIG. 10 is explained in conjunction with the embodiment of FIG. 4. At step 100, a line including the above sequence of instructions is prefetched from instruction cache 30 and stored in prefetch buffer 32 in locations B13 through C15. (The above sequence of instructions begin at location B14.) The same instruction bytes are also delivered to block 35.
At step 102, parallel 0FH detectors 36 detect 0FH bytes in positions B14, C1, C6, and C9 and generate 0F bits for bytes C12:B13!. The 0F bits are stored in corresponding locations in 0FH buffer 46. Parallel 0FH shifters 38 each select three bytes to send to their corresponding length decoders 40 based on the corresponding 0F signal. In this example, shifter.sub.-- 13 selects B15:B13!, shifter.sub.-- 14 selects C1:B15!, shifter.sub.-- 15 selects C1:B15!, shifter.sub.-- 0 selects C2:CO!, shifter.sub.-- 1 selects C4:C2!, shifter.sub.-- 2 selects C4:C2!, shifter.sub.-- 3 selects C5:C3!, shifter.sub.-- 4 selects C6:C4!, shifter.sub.-- 5 selects C7:C5!, shifter.sub.-- 6 selects C9:C7!, shifter.sub.-- 7 selects C9:C7!, shifter.sub.-- 8 selects C10:C8!, shifter.sub.-- 9 selects C12:C10!, shifter.sub.-- 10 selects C12:C10!, shifter.sub.-- 11 selects C13:C11!, and shifter.sub.-- 12 selects C14:C12!.
At step 104, parallel length decoders 40 length decode their corresponding selected instruction bytes. Length decoder.sub.-- 14 generates a length of 3(corresponding to instruction #1 above). Length decoder.sub.-- 1 generates a length of 5(corresponding to instruction #2 above). Length decoder.sub.-- 6 generates a length of 3(corresponding to instruction #3 above). Length decoder.sub.-- 9 generates a length of 5(corresponding to instruction #4 above). The other length decoders may also produce invalid length values, shown as X in FIG. 10 because they will later be discarded by invalid instruction logic in the decode stage. The length values are stored in corresponding locations in length buffer 44.
At step 106, attribute bits decoder 58 generates a set of attribute bits for each of the sixteen bytes in the prefetched line. In one embodiment, the attributes bits are those of Table 1 and appear in order from left to right as: 1) predicted branch taken bit, 2) predicted bit, 3) page violation bit, and 4) valid bit. Exemplary values for these bits are shown in FIG. 10. The attribute bits decoder 58 stores the attribute bits in corresponding locations in attribute buffer 62.
At step 108, the first and second stages of code rotator 48 select fourteen bytes based on the prefetch instruction pointer. In this example bytes C11:B14! are selected. The first and second stages of length rotator 50, 0FH rotator 52, and attribute rotator 64 perform corresponding operations to select the corresponding C11:B14! length values, 0F bits, and attribute bits, respectively. The values selected by the first and second stages of rotation are those underlined in step 108.
At step 110, the third stage of code rotator 48 selects, based on the B14! 0F bit, bytes C11:B15! to shift out the 0FH byte in position B14!. The selected bytes are underlined in step 110. The third stage selects either 13 of 14 or 14 of 14 of the fourteen selected instruction bytes depending on the 0F bit of the most significant byte in the fourteen-byte window (in this case bit B14!). Length rotator 50, 0FH rotator 52, and attribute rotator 64 do not perform the third stage of rotation.
At step 112, based on the length values and the 0F bits of the prefetched line the fourth stage of code rotator 48 selects the first and second instructions, shifts out a 0FH opcode byte in the second instruction if present, and stores the first and second instructions in instruction FIFO 66. Length rotator 50 and 0FH rotator 52 select and store the length values and 0F bits corresponding to the most significant bytes of the first and second instructions (in this example positions B14! and C1!, respectively) in instruction FIFO 66.
The fourth stage of attribute rotator 64 selects the attribute bits corresponding to the first and second instructions. In one embodiment, the attributes for each of the first and second instructions are selected as follows: #1) the predicted branch taken bit corresponding to the least significant instruction byte (LSB) is selected; #2) the predicted bit corresponding to the LSB is selected; #3) the page violation bit corresponding to the most significant instruction byte (MSB) is selected; #4) the valid bit corresponding to the LSB is selected; and #5) the valid bit corresponding to the fourth instruction byte, if present, is selected. The attribute bits selected in this example are underlined in step 112.
At step 114, the first and second instructions and their associated 0F bits, length values, and attribute bits selected by the rotators 48, 50, 52, and 64 are stored in instruction FIFO 66.
Thus, a method and apparatus for efficient propagation of attribute bits in an instruction decoding pipeline has been described. In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims
What is claimed is:
1. An instruction decode pipeline for decoding instructions which appear in an instruction stream without differentiation, each instruction including one or more instruction blocks, the instruction decode pipeline comprising: an instruction path for extracting a first and second instructions from a first plurality of instruction blocks; an attribute bit decoder coupled to the instruction path, wherein the attribute bit decoder generates a first plurality of attribute bits corresponding to the first plurality of instruction blocks; and an attributes path coupled to the instruction path, wherein the attribute path selects a first and second attribute bits corresponding to the first and second instructions, wherein the first and second attribute bits control one or more operations in decoding the first and second instructions.
2. The apparatus of claim 1 further comprising: a prefetch buffer coupled to the instruction path, the prefetch buffer having stored therein the plurality of instruction bytes; and an attribute buffer coupled to the attribute path, the attribute buffer having stored therein the plurality of attribute bits.
3. The apparatus of claim 2 wherein the first instruction is extracted based on an instruction pointer, the apparatus further comprising: a length decoder for determining the length of the first and second instructions; wherein the second instruction is extracted based on the instruction pointer and the length of the first instruction; and wherein the lengths of the first and second instruction are used to increment the instruction pointer.
4. The apparatus of claim 3 wherein the first and second attribute bits are branch prediction bits.
5. The apparatus of claim 3 wherein the first and second attribute bits are valid bits for indicating whether the first and second instructions are valid.
6. The apparatus of claim 3 wherein the first and second attribute bits are page violation bits for indicting whether the first and second instructions access a page not present in a memory.
7. An apparatus for handling instructions and attributes in an instruction decode pipeline, the apparatus comprising: an instruction buffer having stored therein a plurality of instruction blocks; an instruction selector coupled to the instruction buffer, wherein the instruction selector selects one or more of the instruction blocks; an attribute buffer coupled to the instruction buffer, the attribute buffer having stored therein a plurality of attribute blocks corresponding to the instruction blocks, each attribute block including one or more attribute bits; and an attribute selector coupled to the attribute buffer, wherein the attribute selector selects one or more attribute bits from the attribute blocks corresponding to the selected one or more instruction blocks, wherein the selected attribute bits control how the instruction decode pipeline operates on the selected one or more instruction blocks.
8. The apparatus of claim 7 wherein the instruction selector selects based on a prefetch instruction pointer, wherein the plurality of instruction blocks are equally corresponding to the plurality of attribute blocks.
9. The apparatus of claim 8 wherein the one or more attribute bits include one or more bits for branch prediction.
10. The apparatus of claim 9 wherein the one or more attribute bits include one or more valid bits for indicating whether the corresponding instruction block is valid.
11. The apparatus of claim 10 wherein the one or more attribute bits include one or more page violation bits for indicting whether instructions corresponding to the one or more selected instruction blocks access a page not present in a memory.
12. An instruction decode pipeline for decoding instructions which appear in an instruction stream without differentiation, each instruction including one or more instruction blocks, the instruction decode pipeline comprising: a prefetch buffer having stored therein a first plurality of instruction blocks; a length decoder coupled to the prefetch buffer, wherein the length decoder determines the length of the first and second instructions; a code rotator coupled to the prefetch buffer, wherein the code rotator selects a first and second instructions from the first plurality of instruction blocks based on a prefetch instruction pointer and the length of the first instruction; an attribute bit decoder coupled to the prefetch buffer, wherein the attribute bit decoder generates a first plurality of attribute bits corresponding to the first plurality of instruction blocks; an attribute buffer coupled to the instruction decoder, wherein the attribute buffer stores therein the first plurality of attribute bits in locations corresponding to the first plurality of instruction blocks stored in the prefetch buffer; an attribute rotator coupled to the attribute buffer, wherein the attribute path selects a first and second attribute bits corresponding to the first and second instructions, wherein the first and second attribute bits control one or more operations in further decoding the first and second instructions in the instruction decode pipeline.
13. The apparatus of claim 12 wherein the second instruction is extracted based on the instruction pointer and the length of the first instruction and the lengths of the first and second instruction are used to increment the instruction pointer.
14. An apparatus comprising: an instruction buffer having stored therein a first plurality of instructions; means, coupled to the instruction buffer, for selecting a first and second instructions from the first plurality of instructions; means, coupled to the instruction selecting means, for generating a first plurality of attribute bits corresponding to the first plurality of instructions; an attribute buffer, coupled to the attribute generating means, wherein the attribute generating means stores the first plurality of attribute bits in the attribute buffer; means, coupled to the attribute buffer, for selecting a first and second attribute bits corresponding to the first and second instructions.
15. A method for handling attribute bits in an instruction decode pipeline, the method comprising the steps of: storing a first plurality of instructions in an instruction buffer; selecting a first and second instructions from a first plurality of instructions stored in the instruction buffer; generating a first plurality of attribute bits corresponding to the first plurality of instructions; storing the first plurality of attribute bits in an attribute buffer; selecting a first and second attribute bits corresponding to the first and second instructions; and decoding the first and second instructions in the instruction decode pipeline, wherein the first and second attribute bits control one or more operations in the decoding step.