Manufacturing Method of Semiconductor Device

This application is based upon and claims the benefit of priority of the prior Japanese Patent applications No. 6-60693 filed on Mar. 30, 1994, No. 6-62448 filed on Mar. 31, 1994, No. 6-63220 filed on Mar. 31, 1994, No. 6-215769 filed on Sep. 9, 1994, and No. 6-324694 filed on Dec. 27, 1994, the contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention generally relates to a manufacturing method for a semiconductor device. More particularly, the present invention relates to a manufacturing method for a semiconductor device used as a power semiconductor device, i.e., a MOSFET (metal oxide semiconductor field effect transistor) and an IGBT (insulated gate bipolar transistor), and can suitably be employed for a MOSIC, etc. as a single unit or with the incorporation of a power semiconductor device.

2. Related Arts

Recently, a vertical type power MOSFET has been used in many industrial fields for various features thereof such as high frequency characteristics, fast switching speed and low power driving. The Nikkei Electronics (Nikkei-McGraw-Hills, Inc., May 19, 1986, pp. 165-188) says that the focus of the development of the power MOSFET has shifted to the low withstand voltage type and the high withstand voltage type, and that the ON-resistance of the power MOSFET having a withstand voltage of 100V or less has been lowered down to a level of 10 m.OMEGA. for the reason that channel width per unit area has been widened by using the microprocessing of LSI for the manufacture of the power MOSFET or by improving the shape of the power MOSFET. The description of this magazine centers around the prevailing vertical type power MOSFET using DMOS type (double diffusion type) cells, reasoning that the DMOS type has productional advantages of high yield and low cost owing to the use of the planar process featured by the use of a flat main surface of a silicon wafer for the channel part.

On the other hand, along with the spread of the vertical power MOSFET, there is an increasing demand for lower loss and lower cost, while the ON-resistance reduction by means of microprocessing and cell shape improvement has reached the limits. According to the Japanese Unexamined Patent Publication No. 63-266882, for example, the DMOS type has the minimal point from which the ON-resistance will not decrease however small the unit cell dimension is made by microprocessing, and it has been known that the major cause of the existence of the minimal point is an increase in the JFET (junction field effect transistor) resistance constituting a component of the ON-resistance. Furthermore, as disclosed in the Japanese Unexamined Patent Publication No. 2-86136, the unit cell dimension with which the ON-resistance takes the minimal point is approximately 15 .mu.m under the current microprocessing technology.

Various constructions have been proposed in an attempt to break through this limit. Common to these proposals is a construction in which a groove is formed on an element surface and a channel part is formed on a side surface of the groove, and this construction can substantially reduce the above JFET resistance. Furthermore, in a construction in which the channel part is formed on the side surface of the groove, even if the unit cell dimension is reduced, the consequent increase in the JFET resistance is negligible. Therefore, there is no limit wherein the ON-resistance takes a minimal point against the reduction in the unit cell dimension unlike the description in the Japanese Unexamined Patent Publication No. 63-266882, and thus the unit cell dimension can be further reduced to the limits of current microprocessing capabilities, i.e., below 15 .mu.m.

An example of the conventional manufacturing method with the above construction with the channel part on the side surface of the groove has been disclosed in the Japanese Unexamined Patent Publication No. 61-199666, for example, in which the groove is formed by means of RIE (reactive ion etching) and the channel part is formed on the side surface of the formed groove. Here, the RIE is a physical etching technique with a high process controllability. Specifically, in the RIE, electrodes are disposed on the top part and bottom part of a semiconductor device placed within the gas atmosphere; when a high frequency power is applied to between the electrodes, the gas is ionized into electrons and ions; and due to a large difference in the mobility of electrons and the ions between these electrodes, an cathode drop is caused to the top part of the semiconductor; this cathode drop causes an electric field, and the electric field accelerates the ions toward the semiconductor device and the ions physically collide against the surface to be etched, and the collision energy is used for etching the semiconductor device. For accelerating the ionized ions, a high frequency power is applied between the electrodes so as to cause a cathode drop of approximately 10 to 500V in absolute value. The RIE is featured by an excellent anisotropy and a consequent high resistance to side etch due to the acceleration of ionized gas in a constant direction. However, there is a problem with the RIE that, as the physically ionized gas is collided against the semiconductor device, a lattice defect is inevitably caused to the etched surface and subsequently a surface recombination occurs thereon, and as a result, the ON-resistance increases.

Some manufacturing methods have been disclosed which can control a lattice defect, for instance manufacturing methods using a wet etching technique such as in International Publication No. PCT WO93/03502 and the Japanese Unexamined Patent Publication No. 62-12167. FIGS. 25(a) and 25(b) are a plane view and cross-sectional view of a MOSFET respectively disclosed in the International Publication No. PCT WO93/03502, and FIGS. 26 through 37 are cross-sectional views of a MOSFET illustrating the manufacturing process therefor according to the same publication.

The above manufacturing process will now be briefly described.

First of all, as illustrated in FIG. 26, a wafer 21 is prepared with an n.sup.- -type epitaxial layer 2 developed on the main surface of a semiconductor substrate 1 made of n.sup.+ -type silicon. This semiconductor substrate 1 has an impurity concentration of approximately 10.sup.20 cm.sup.-3, while the n.sup.- type epitaxial layer 2 is developed to a thickness of approximately 7 .mu.m and an impurity concentration of approximately 10.sup.16 cm.sup.-3. A field oxide film 60 is formed to a thickness of approximately 60 nm by thermally oxidizing the main surface of the wafer 21, and then a resist film 61 is deposited and patterned by the publicly known photolithographic technique with the central part thereof open, the location of which being coincided with a location of cell formation. Then, boron ions (B.sup.+) are implanted through the field oxide film 60 by using the resist film 61 as a mask.

After removing the resist film 61, as illustrated in FIG. 27, a p-type diffusion layer 62 is formed to a junction depth of approximately 3 .mu.m. The p-type diffusion layer 62 ultimately becomes a part of a p-type base layer 16 (described herein later), and plays a role of improving the surge resistance by stably causing breakdown to the bottom part of the p-type diffusion layer 62 when a high voltage is applied to between a drain electrode and a source electrode.

Next, as illustrated in FIG. 27, a silicon nitride film 63 is deposited to a thickness of approximately 200 nm on the main surface of the wafer 21. The silicon nitride film 63 is patterned into a lattice-like open pattern with openings with a pitch (dimension of a unit cell 15) a. Incidentally, mask alignment is applied to the open pattern so that the p-type diffusion layer 62 can be positioned in the central part of the pitch.

Following the above, as illustrated in FIG. 28, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and then a groove 64 is formed by etching the n.sup.- -type epitaxial layer 2 to a depth of approximately 1.5 .mu.m.

As illustrated in FIG. 29, this time, the groove 64 is thermally oxidized by using the silicon nitride film 63 as a mask, which is a well known oxidizing technique as LOCOS (local oxidation of silicon). By this oxidation, a selective oxide film, i.e., a LOCOS oxide film 65 is formed, and concurrently a U-groove 50 is formed on the surface of the n.sup.- -type epitaxial layer 2 eroded by the LOCOS oxide film 65 and the shape of the groove 50 is fixed.

Then, as illustrated in FIG. 30, boron ions are implanted through a thin field oxide film 60 by using the LOCOS oxide film 65 as a mask to form the p-type base layer 16. In this process, the boundary surface between the LOCOS oxide film 65 and the field oxide film 60 is coincided with a self-alignment position, and accordingly a region into which boron ions are to be implanted can be defined exactly.

In the next process, as illustrated in FIG. 31, thermal diffusion is performed to obtain a junction depth of approximately 3 .mu.m. By this thermal diffusion, the p-type diffusion layer 62 previously formed in the process illustrated in FIG. 27 and the diffusion layer of the boron ions implanted in the process illustrated in FIG. 30 are integrated into the single p-type base layer 16, and both end surfaces of the p-type base layer 16 are self-alignedly defined in the position of the side walls of the U-groove 50.

Now, as illustrated in FIG. 32, phosphorous ions are implanted through the thin field oxide film 60 by using both a resist film 66 patterned by a pattern left on the central part of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 by a lattice-like pattern and the LOCOS oxide film 65 to form the n.sup.+ -type source layer 4. In this process as well, like the ion implantation performed with boron ions in the process illustrated in FIG. 30, the boundary part between the LOCOS oxide film 65 and the field oxide film 60 is coincided with a self-alignment position, and accordingly a region into which phosphorous ions are to be implanted can be defined exactly.

After the above, as illustrated in FIG. 33, the n.sup.+ -type source layer 4 is formed and concurrently the channel 5 is set up by thermal diffusion to a junction depth of 0.5 to 1 .mu.m. By this thermal diffusion, the end surface being in contact with the U-groove 50 in the region of the n.sup.+ -type source layer 4 is self-alignedly defined.

As a result of the processes illustrated in FIGS. 30 through 33, the junction depth and shape of the p-type base layer 16 can be fixed.

As illustrated in FIG. 34, now, the LOCOS oxide film 65 is removed by wet etching to expose an inside wall 51 of the U-groove 50, and then a gate oxide film 8 is formed to a thickness of approximately 60 nm by thermal oxidation.

Next, as illustrated in FIG. 35, a polysilicon film is deposited to a thickness of approximately 400 nm on the main surface of the water 21.

Following the above, as illustrated in FIG. 36, boron ions are implanted through the oxide film 67 by using the patterned resist film 68 as a mask in preparation for forming a p.sup.+ -type base contact layer 17.

Then, as illustrated in FIG. 37, the p.sup.+ -type base contact layer 17 is formed by the thermal diffusion to a junction depth of approximately 0.5 .mu.m.

Subsequently, as illustrated in FIG. 25(b), an interlayer insulating film 18 is formed with BPSG (boron phosphate silicate glass) on the main surface of the wafer 21, and contact holes are made in parts of the interlayer insulating film 18 to expose the p.sup.+ -type base contact layer 17 and the n.sup.+ -type source layer 4. Furthermore, a source electrode 19 is formed with an aluminum film to achieve an ohmic contact between the source electrode 19 and the p.sup.+ -type base contact layer 17 and n.sup.+ -type source layer 4 through the contact holes. In addition, a passivation film (not illustrated) for protecting the aluminum film is formed by the plasma CVD method or the like using silicon nitride. On the other hand, on the back surface of the wafer 21 is formed a drain electrode 20 with three layers of a Ti film, a Ni film and a Au film and ohmically contacted with the n.sup.+ -type semiconductor substrate 1.

However, according to the manufacturing methods disclosed in the above International Publication No. PCT WO93/03502 and the Japanese Unexamined Patent Publication No. 62-12167, there is a problem that as the wet etching technique which is isotropic etching technique is used, an excessive etching over a specified etching width (i.e., side etch) is caused, a uniform groove with a constant depth can not be formed on the wafer surface due to uneven etching liquid, and consequently the process controllability is low.

Another problem is that, as the groove shape within the wafer surface is not uniform, the unevenness in the electric characteristics of the FET is large. The cause of the uneven groove shape is presumed to be the unevenness in the groove shape within the wafer surface in the etching process prior to the LOCOS oxidation. It may be an idea to form the channel groove by the LOCOS oxidation alone. However, this would lengthen the LOCOS oxidation time period and the angle of the groove side surface would be as gentle as approximately 30.degree., and this would make it impossible to micronize cells and the reduction in the ON-resistance would not be promising. Furthermore, if the channel groove is formed by the LOCOS oxidation alone, as the volume of Si almost doubles due to oxidation by nature, the channel part might be strained by the increase in the Si volume. Therefore, the etching process prior to the LOCOS oxidation, i.e., the initial groove formation process, is necessary by all means.

From the above viewpoint, in order to manufacture a vertical type MOSFET at a low voltage with uniformity in the electric characteristics within the wafer surface being maintained, it is necessary to perform the LOCOS oxidation without introducing any defect or contaminant into the channel part after the formation of the initial groove and besides remove the LOCOS oxide film to make the groove shape uniform within the wafer surface.

However, the manufacturing methods disclosed in the above publications have a problem that reducing the channel defect and exactly controlling the channel groove shape together is impossible.

In view of the above problems, it is a primary object of the present invention to obtain a manufacturing method for a MOSFET having a channel part on the side surface which can reduce the channel part defect and exactly control the groove shape.

The manufacturing method according to the present invention aiming to achieve the above object comprises: a mask formation process for forming a mask having an opening part within a specified region on the main surface of a first conductivity type semiconductor layer disposed on a semiconductor substrate; a chemical dry etching process for forming a first groove having an inlet part wider than an opening part of the mask, a bottom surface roughly parallel to the main surface and a side surface connecting the inlet part and the bottom part by applying a chemical dry etching to the semiconductor layer through the opening of the mask; an oxidation process for forming an oxide film to a specified thickness on the surface of the first groove by oxidizing a region including the first groove; an impurity introduction process for forming a second conductivity type base layer within the semiconductor layer by introducing second conductivity type impurities from the main surface so as to include the surface of the semiconductor layer being adjacent to the oxide film, forming a first conductivity type source layer within the base layer by introducing first conductivity type impurities from the main surface, and forming a channel region on the side wall of the base layer concurrently with the formation of the source layer; an oxide film removal process for forming a second groove having a specified depth deeper than the first groove by removing the oxide film; and an electrode formation process for forming a gate electrode on the surface of the second groove between the source layer and the semiconductor layer through a gate insulating film, forming a source electrode which is to electrically contact the source layer and the base layer, and forming a drain electrode which is to electrically contact the semiconductor substrate.

Incidentally, the chemical dry etching process may preferably be an isotropic etching process, and if a gas system including carbon tetrafluoride and oxygen is used for etching, high reproducibility can be achieved by controlling the ratio of the carbon tetrafluoride to the oxygen.

In addition, the chemical dry etching process may be an etching process using a gas system which includes one or more than one of CCl.sub.4, Cl.sub.2, SF.sub.6, CFCl.sub.3, CF.sub.2 Cl.sub.2, CF.sub.3 Cl, CHF.sub.3, C.sub.2 ClF.sub.5, F.sub.2, NF.sub.3 and BCl.sub.3, and the efficiency of this etching process is high.

Furthermore, the chemical etching may preferably be performed within the ionized gas atmosphere with substantially no cathode drop (self bias) at the upper part of the semiconductor layer, and if any, the cathode drop at the upper part of the semiconductor layer may preferably be less than 10V in absolute value.

Moreover, the oxidation process according to the present invention may preferably comprise a selective oxidation process for forming a selective oxide film to a specified thickness on the surface of the first groove and between the mask and the semiconductor substrate by selectively oxidizing a region including the first groove; the impurity introduction process may preferably comprise a process for forming the base layer of the second conductivity type by introducing the second conductivity type impurities from the side of the main surface so as to include the surface of the semiconductor layer being adjacent to the selective oxide film and a process for forming the source layer of the first conductivity type by introducing the first conductivity type impurities from the side of the main surface into the base layer; and the oxide film removal process may preferably comprise a selective oxide film removal process for forming the second groove having a specified depth deeper than the first groove by removing the selective oxide film.

Here, the selective oxide process may use the mask formed in the mask forming process for selective oxidation. Therefore, there is no need to form a new mask or to perform mask alignment.

Also, the oxide film removal process according to the present invention may preferably be a process for forming a second groove by removing the oxide film while the surface of the oxide film is terminated with hydrogen within an aqueous solution, and then forming an oxide film for protecting the second groove by oxidizing the surface of the second groove applied with the termination with hydrogen within gas including oxygen. Here, the oxide film removal process is featured by the removal of the oxide film by terminating with hydrogen a dangling bond generated on the surface of the oxide film within an aqueous solution including hydrofluoric acid. As a result of this process, the highly reactive dangling bond reacts to the hydrogen before reacting to the contaminant into a stable state, whereby the reaction of the contaminant to the semiconductor layer can be prevented. Subsequently, when the dangling bond is exposed to the oxygen, a more stable oxide film can be formed, whereby the surface of the second groove can be protected and the following contamination of the channel region can be prevented. In short, a high channel mobility can be obtained, and a low ON-state voltage can be realized.

Furthermore, the oxide film removal process according to the present invention is featured by a process in which the oxide film is removed with at least the surface of the oxide film being shaded from light. Therefore, there is no light irradiated onto the semiconductor layer to be a channel region. Accordingly, the electric potential of the source layer is almost equal to the electric potential of the base layer both in the neighborhood of the channel region, the development of etching from a limited part can be prevented, and a uniform etching is possible. As a result, a flat channel region can be obtained, and a high mobility can be realized.

According to the present invention constructed as described above, a specified region of the surface of the semiconductor layer having a low impurity concentration is removed by the chemical dry etching method prior to the selective oxidation. The chemical dry etching method which is one of the dry etching methods is high in process controllability, uniform in etching within the wafer surface, and high in reproducibility. The chemical dry etching gives comparatively less damage to the etching surface compared with other dry etching methods. After this chemical dry etching, the surface of the first groove is oxidized. In this oxidation process, according to the surface condition of the first groove from which the oxidation is started, the condition of the boundary surface with the oxide film of the resultant semiconductor layer varies. That is, even if the surface etched by a physical etching technique such as RIE is oxidized, the oxidation advances without removing lattice defects, and the lattice defects remain on the surface of the resultant semiconductor layer. However, in the present invention, by applying the chemical dry etching to the surface of the first groove, the first groove with a few lattice defects can be formed, and oxidation of the surface of the resultant first groove can be uniform from the start of the oxidation, and therefore the surface of the second groove can have a few lattice defects. Furthermore, as the surface of this second groove is used for the channel region, a low ON-resistance can be obtained. Moreover, as two processes of the chemical dry etching and the oxidation are applied to the formation of the second groove for the channel region, when the second groove is desired to be formed to a specified width, only what is required is to control the width to be oxidized. Therefore, the shape of the second groove can exactly be controlled.

Here, if the chemical dry etching process is isotropic, the first groove has no corner part, and consequently the second groove formed by oxidation has no corner part, whereby the withstand voltage between the drain layer and the source layer can be improved.

In addition to the above, if there is no substantial cathode drop (less than 10V in absolute value) during the chemical dry etching process, there is no possibility that the ionized gas collides against the surface of the semiconductor layer at such a speed that the collision gives defects to the surface of the semiconductor. Accordingly, the surface of the formed first groove has a few defects.

Furthermore, by removing the oxide film within an aqueous solution including hydrofluoric acid, the selection ratio of the oxide film to be removed and the semiconductor layer not to be removed can be set to be a very large, and the oxide film can be removed without damaging the surface of the semiconductor layer.

Still furthermore, if the index of plane of the side surface of the second groove formed by removing the selective oxide film is (110) or (100), the side surface can be flat in terms of atomic order of silicon, whereby a high channel mobility can be obtained.

On the other hand, if the index of plane of the side surface of the second groove formed by removing the selective oxide film is (111), the silicon atoms of the side surface of the second groove is terminated with a single piece of hydrogen, and the side surface can be flat in terms of atomic order, whereby a high channel mobility can be obtained. Here, if the oxide film removal process is performed within an aqueous solution of pH4 or more, the possibility of terminating the silicon atoms of the side surface of the second groove with a single piece of hydrogen becomes higher, and the (111) surface flat in terms of atomic order can be obtained, whereby a high channel mobility can be obtained.

These and other objects, features and characteristics of the present invention will be appreciated from a study of the following detailed description, the appended claims, and drawings, all of which form a part of this application. In the drawings:

FIG. 1(a) is a plane view illustrating a part of the vertical type power MOSFET of the first embodiment according to the present invention, and FIG. 1(b) is a cross-sectional view taken along line A--A of FIG. 1(a);

FIG. 2 is a view illustrating the manufacturing process of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 3 is a cross-sectional view illustrating the manufacturing process of an important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 4 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 5 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 6 is a plane view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 7 is a view illustrating the manufacturing process of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 8 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 9 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 10 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 11 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 12 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 13 is a view illustrating the manufacturing process of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 14 is a view illustrating the manufacturing process of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 15 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 16 is a view illustrating the manufacturing process of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 17 is a view illustrating the manufacturing process of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 18 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 19 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 20 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 21 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 22 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the first embodiment according to the present invention;

FIG. 23 is a cross-sectional view illustrating the manufacturing process of the important part of the vertical type power MOSFET of another embodiment according to the present invention;

FIG. 24 is a plane view illustrating the manufacturing process of the important part of the vertical type power MOSFET of the second embodiment according to the present invention;

FIG. 25(a) is a plane view illustrating a part of a conventional power MOSFET, and FIG. 25(b) is a cross-sectional view taken along line A--A of FIG. 25(a);

FIG. 26 is a cross-sectional view illustrating the manufacturing process of an important part of the conventional vertical type power MOSFET;

FIG. 27 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 28 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 29 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 30 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 31 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 32 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 33 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 34 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 35 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET;

FIG. 36 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET; and

FIG. 37 is a cross-sectional view illustrating the manufacturing process of the important part of the conventional vertical type power MOSFET.

An embodiment according to the present invention will now be described with reference to the appended drawings.

FIG. 1(a) is a plan view of a vertical type power MOSFET composed of a numerosity of square unit cells according to the first embodiment of the present invention, and FIG. 1(b) is a cross-sectional view taken along line A--A of FIG. 1(a). FIGS. 2 through 22 are descriptive views of the respective stages of the manufacturing method for a vertical type power MOSFET according to the first embodiment, wherein FIG. 4 is a cross-sectional view of a wafer into which boron ions have been implanted to form a central part of a p-type base layer; FIG. 5 is a cross-sectional view of the wafer whose silicon nitride film has been patterned at a pitch which is equal to the dimension of a unit cell a for the LOCOS (localized oxidation of silicon); FIG. 8 is a cross-sectional view of the wafer on which the LOCOS oxide film has been formed; FIG. 9 is a cross-sectional view of the wafer into which boron ions have been implanted to form a p-type base layer by using the LOCOS oxide film as a mask; FIG. 10 is a cross-sectional view of the wafer on which a p-type base layer has been formed by means of thermal diffusion; FIG. 11 is a cross-sectional view of the wafer into which phosphorous ions have been implanted to form an n.sup.+ -type source layer by using the LOCOS oxide film as a mask; FIG. 18 is a cross-sectional view of the wafer on which the n.sup.+ -type source layer has been formed by means of thermal diffusion; FIG. 20 is a cross-sectional view of the wafer on which a gate oxide film has been formed by means of thermal oxidation since the removal of the LOCOS oxide film; FIG. 19 is a cross-sectional view of the wafer with a gate electrode formed on the gate oxide film; FIG. 21 is a cross-sectional view of the wafer into which boron ions have been implanted to form a p.sup.+ -type base contact layer; FIG. 22 is a cross-sectional view of the wafer on which the p.sup.+ -type base contact layer has been formed by means of thermal diffusion; and FIG. 1(b) is the cross-sectional view of the completed wafer on which an interlayer insulating film, a source electrode and a drain electrode have been formed.

The main part (unit cell part) of the vertical type power MOSFET according to this embodiment is so constructed as illustrated in FIGS. 1(a) and 1(b) in which a numerosity of unit cells 15 are laid out lengthwise and breadthwise with ordination at a pitch (unit cell dimension) of a.

In FIGS. 1(a) and 1(b), a wafer 21 is composed of a semiconductor substrate 1 comprising an n.sup.+ -type silicon having an impurity density of 10.sup.20 cm.sup.-3 and a thickness of 100 to 300 .mu.m, an n.sup.- -type epitaxial layer 2 having an impurity density of approximately 10.sup.16 cm.sup.-3 and a thickness of approximately 7 .mu.m formed on the semiconductor substrate 1 and a unit cell 15 formed on the main surface of the wafer 21. On the main surface of the wafer 21 is formed a LOCOS oxide film to a thickness of approximately 3 .mu.m to form a U-groove 50 at a pitch of the unit cell dimension a (=approximately 12 .mu.m) and by using this oxide film are formed a p-type base layer 16 to a junction depth of approximately 3 .mu.m and an n.sup.+ -type source layer 4 to a junction depth of approximately 1 .mu.m, whereby a channel 5 is set on the side wall part 51 of the U-groove 50. Incidentally, the p-type base layer 16 is set to a junction depth which does not permit the p-type layer 16 to be fractured due to breakdown at an edge part 12 on the bottom of the U-groove 50. Furthermore, boron ions have been implanted into the central part of the p-type base layer 16 beforehand to deepen the junction depth in the central part of the p-type layer 16 down from the circumference, so that a breakdown can be caused when a high voltage is applied to between the drain electrode and the source electrode. After the double diffusion, the diffusion mask and the LOCOS oxide film used for forming the U-groove 50 are removed, a gate oxide film 8 is formed to a thickness of approximately 60 nm on the inner wall of the U-groove 50 and on the gate oxide film 8 are formed a gate electrode 9 with a polysilicon to a thickness of approximately 400 nm and an interlayer insulating film 18 with a BPSG to a thickness of approximately 1 .mu.m. Furthermore, a p.sup.+ -type base contact layer 17 is formed to a junction depth of approximately 0.5 .mu.m in the central part surface of the p-type base layer 16 and ohmic contact is made between a source electrode 19 formed on the interlayer insulating film 18 and the n.sup.+ -type source layer 4 and p.sup.+ -type base contact layer 17 through contact holes. On the other hand, a drain electrode 20 is formed on the back surface of the semiconductor substrate 1 to make ohmic contact therewith.

An example of the manufacturing method according to this embodiment will now be described.

A wafer 21 is prepared in which, as illustrated in FIGS. 2 and 3, an n.sup.- -type epitaxial layer 2 is formed by means of epitaxial growth on the main surface of the semiconductor substrate 1 having the index of plane of (100). The impurity concentration of this semiconductor substrate 1 (equivalent to a semiconductor substrate) is approximately 10.sup.20 cm.sup.-3 and the thickness of the epitaxial layer 2 (equivalent to a semiconductor layer) is approximately 7 .mu.m and the impurity concentration thereof is approximately 10.sup.16 cm.sup.-3. Then, as illustrate in FIG. 4, a field oxide film 60 is formed to a thickness of approximately 60 nm by thermally oxidizing the main surface of the wafer 21 and subsequently a resist film 61 is deposited on the field oxide film 60 and the resist film is patterned to form a pattern opened in the central part of a region where a cell is to be formed by means of the publicly known photolithographic technique. Then, boron (B.sup.+) ions are implanted into the field oxide film 60 by using the resist film 61 as a mask.

As illustrated in FIG. 5, after removing the resist, a p-type diffusion layer 62 is formed to a junction depth of approximately 3 .mu.m by means of thermal diffusion. This p-type diffusion layer 62 ultimately constitutes a part of the p-type base layer 16 (described herein later) and plays a role of improving the surge resistance of the device by stably causing a breakdown at the bottom part of the p-type diffusion area when a high voltage is applied to between the drain electrode and the source electrode.

Furthermore, as illustrated in FIG. 5, a silicon nitride film 63 is deposited to a thickness of approximately 200 nm on the main surface of the wafer 21. Then, as illustrated in FIG. 6, the silicon nitride film 63 (equivalent to a mask) is patterned to be vertical and parallel to an orientation of <011> to form a lattice-like open pattern opening at a pitch of a (dimension of unit cell 15) (equivalent to a mask formation process). This open pattern is mask-aligned so that the above p-type diffusion layer 62 can be positioned in the central part of the pitch.

The field oxide film 60 is etched by using the silicon nitride film 63 as a mask. Following this, as illustrated in FIG. 7, a chemically active species is made by generating plasma within a discharge chamber 702 containing a carbon tetrafluoride and oxygen gas and the active species is transported into a reaction chamber 703 and a groove 64 is formed by isogonally applying chemical dry etching to the n.sup.- -type epitaxial layer 2 within the reaction chamber 703 (equivalent to a chemical dry etching process).

Next, as illustrated in FIG. 8, the part of the groove 64 is thermally oxidized by using the silicon nitride film 63 (equivalent to an oxidation process and a selective oxidation process). This is an oxidation method well known as the LOCOS (local oxidation of silicon) method. By this oxidation, a LOCOS oxide film 65 (equivalent to an oxide film and a selective oxide film) is formed and concurrently a U-groove 50 (equivalent to a second groove) is formed on the surface of the n.sup.- -type epitaxial layer 2 eroded by the LOCOS oxide film 65 and the shape of the U-groove is fixed.

In the above process, the conditions of the chemical dry etching and LOCOS oxidation are selected by controlling an angle .theta. of the side surface of the U-groove to the surface of the semiconductor substrate 1 (FIG. 8) so that the index of plane of the channel forming part on the side surface of the U-groove 50 can be approximates to (111).

The inside wall surface 51 of the U-groove 50 formed by the LOCOS oxidation as described above has a high flatness and a few defects and the surface condition thereof is as good as the main surface of the wafer 21 in the initial stage illustrated in FIG. 2.

Now, as illustrated in FIG. 9, boron ions are implanted through the thin field oxide film 60 by using the LOCOS oxide film 65 as a mask to form the p-type base layer 16. As a result, the boundary part between the LOCOS oxide film 65 and the field oxide film 60 constitutes a self-alignment position to exactly define a region into which boron ions are implanted.

Then, as illustrated in FIG. 10, thermal diffusion is applied to the field oxide film 60 to a junction depth of approximately 3 .mu.m. As the result of this thermal diffusion, the p-type diffusion layer 62 previously formed in the process illustrated in FIG. 5 and the boron diffusion region into which boron ions have been implanted in the process illustrated in FIG. 9 are integrated into the p-type base layer 16 (equivalent to a base layer), both ends of which are self-aligned and defined by the positions of the side walls of the U-groove 50.

Subsequently, as illustrated in FIG. 11, phosphorous ions are implanted through the thin field oxide film 60 by using a resist film 66 patterned according to the pattern left on the central part of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 according to the lattice-like pattern and the LOCOS oxide film 65 as masks to form the n.sup.+ -type source layer 4 (equivalent to a source layer). In this process, like the process illustrated in FIG. 9 in which boron ions have been implanted, the boundary part between the LOCOS oxide film 65 and the field oxide film 60 constitutes a self-alignment position, whereby the ion implantation region can exactly be defined.

The next process is, as illustrated in FIG. 12, to apply thermal diffusion to a junction depth of 0.5 to 1 .mu.m to form the n.sup.+ -type source layer 4 and set the channel 5 (equivalent to a channel region) as well. The end surface being in contact with the U-groove 50 in the region of the n.sup.+ -type source layer 4 is self-aligned and defined in the position of the side wall of the U-groove 50 (equivalent to an impurity introduction process).

The processes illustrated in FIGS. 9 to 12 fix the junction depth and shape of the n-type base layer 16. Here, a point is that the shape of the p-type base layer 16 is perfectly symmetric with respect to the U-groove 50 due to the self-alignment and thermal diffusion.

Next, as illustrated in FIG. 13, an inside wall 51 of the U-groove 50 is exposed by removing the LOCOS oxide film 65 by way of terminating the silicon surface with hydrogen within an aqueous solution containing hydrofluoric acid and adjusted to an acidity/alkalinity of around pH5 with ammonium fluoride. This process may be performed by applying an shading cloth 704 over the wafer 21 to shade the surface with the selective oxide film from light (equivalent to an oxide film removal process and a selective oxide film removal process).

After the completion of the above process, the wafer 1 is taken out of the aqueous solution and dries in a clean air.

Then, as illustrated in FIG. 15, an oxide film is formed on a side surface of the U-groove 50 of the p-type base layer 16 on which the channel 5 is to be formed until the (111) plane is formed. By this thermal oxidation process, the flatness of the surface on which the channel 5 is to be formed is improved in terms of atomic order. As illustrated in FIG. 14, this thermal oxidation process is performed by slowly inserting the wafer 21 into an oxidation furnace 601 which is maintained within the oxygen atmosphere at a temperature of approximately 1000.degree. C. In this thermal oxidation process, as the initial stage of the oxidation is performed at a comparatively low temperature, the scattering of impurities within the p-type base layer region 16 and n.sup.+ -type source region 4 to the outside of the wafer 21 during the thermal oxidation process can be controlled. Then, an oxide film 600 thus formed is removed as illustrated in FIG. 16. The removal of the oxide film 600 is also performed by way of terminating the exposed silicon surface with hydrogen within an aqueous solution containing hydrofluoric acid and adjusted to an acidity/alkalinity of around pH5 with ammonium fluoride. The inside wall surface 51 of the U-groove 50 formed by this method is a good silicon surface with a high flatness and a few defects.

As illustrated in FIG. 18 this time, a gate oxide film 8 is formed to a thickness of approximately 60 nm on the side surface and bottom surface of the U-groove 50 by thermal oxidation. This thermal oxidation process is, as described above and as illustrated in FIG. 17, performed by slowly lowering the wafer 21 into an oxidation furnace 601 which is maintained within the oxygen atmosphere at a temperature of approximately 1000.degree. C. In this thermal oxidation process, as the initial stage of the oxidation is performed at a comparatively low temperature, the scattering of impurities within the p-type base layer region 16 and n.sup.+ -type source region 4 to the outside of the wafer 21 during the thermal oxidation process can be controlled. The film quality and thickness uniformity of the gate oxide film 8, the interface interfacial sequence density of the interface of the channel 5 and the carrier mobility are as high as those of the conventional DMOS.

Now, as illustrated in FIG. 19, the gate electrode 9 is formed by depositing a polysilicon film on the main surface of the wafer 21 to a thickness of approximately 400 nm and patterning the polysilicon film so as to be separated by a distance of c which is shorter by 2.beta. than the distance b between the two U-grooves 50 adjacent to each other. Then, the gate oxide film 8 is further oxidized (a thick film part is formed) so as to be thicker at the end part of the gate electrode 9. Here, when the length of a part where the gate oxide film 8 is thickened is x as illustrated in FIG. 20, .beta. is set to be longer than x (.beta.>x).

In this manner, the gate oxide film 8 is arranged to be a part .lambda. which is uniform in thickness and thin (a thin film part) in the neighborhood of the semiconductor region 4 and on a surface part 501 of the semiconductor region 4 where the impurity concentration is lower than the impurity concentration of the flat part surface of the semiconductor region 4. In other words, the gate oxide film 8 is composed of the thin film part .lambda. uniformly and thinly formed on the side of the U-groove 50 and the thick film part thickly formed in comparison with the thin film part and the gate electrode 9 formed on the gate oxide film 8 from the bottom part of the U-groove 50 to the top of the thick film part.

The processes illustrated in FIGS. 9 through 19 are the most important stages of the manufacturing process according to this embodiment, in which the n-type base layer 16, the n.sup.+ -type source layer 4 and the channel 5 are formed by using the LOCOS oxide film 65 as a mask for self-alignment type double diffusion, then the LOCOS oxide film 65 is removed and then the gate oxide film 8 (equivalent to a gate insulating film) and the gate electrode 9 (equivalent to a gate electrode) are formed (equivalent to a gate electrode formation process).

Next, as illustrated in FIG. 21, boron ions are implanted through an oxide film 67 by using a patterned resist film 68 as a mask to form the p.sup.+ -type base contact layer 17.

Following the above, as illustrated in FIG. 22, the p.sup.+ -type base contact layer 17 is formed to a thickness of approximately 0.5 .mu.m by thermal diffusion.

Then, as illustrated in FIG. 1(b), the interlayer insulating film 18 is formed with a BPSG on the main surface of the wafer 21 and contact holes are made in parts of the interlayer insulating film 18 to expose the p.sup.+ -type base contact layer 17 and the n.sup.+ -type source layer 4. Furthermore, the source electrode 19 is formed with an aluminum film and ohmic contact is made between the source electrode 19 (equivalent to a source electrode) and the p.sup.+ -type base contact layer 17 and n.sup.+ -type source layer 4 through the contact hole. Subsequently, a passivation film (not illustrated) is formed with silicon nitride, etc. for protecting the aluminum film by the CVD (chemical vapor deposition) technique or the like. On the back surface of the wafer 21 is formed the drain electrode 20 (Equivalent to a drain electrode) with three layers of a Ti film, a Ni film and a Au film, an ohmic contact is made between the drain electrode 20 and the n.sup.+ -type semiconductor substrate 1 (equivalent to a source and drain electrode formation process and an electrode formation process).

According to this embodiment of the present invention constructed as described above, a specified region of the surface of the semiconductor layer having a low impurity concentration is removed by the chemical dry etching method prior to the selective oxidation. The chemical dry etching method which is one of the dry etching methods is high in process controllability, uniform in etching within the wafer surface and high in reproducibility. The chemical dry etching gives comparatively less damage to the etching surface compared with other dry etching methods. After this chemical dry etching, the surface of the groove 64 (the first groove) is oxidized. In this oxidation process, according to the surface condition of the groove 64 from which the oxidation is started, the condition of the boundary surface with the oxide film of the resultant n.sup.- -type epitaxial layer 2 (the semiconductor layer) varies. That is, even if the surface etched by a physical etching technique such as RIE is oxidized, the oxidation advances without removing lattice defects and the lattice defects remain on the surface of the resultant n.sup.- -type epitaxial layer 2 (the semiconductor layer). However, in the present invention, by applying the chemical dry etching to the surface of the groove 64, the groove 64 with a few lattice defects can be formed and oxidation of the surface of the resultant first groove can be uniform from the start of the oxidation and therefore the surface of the U-groove 50 can have a few lattice defects. Furthermore, as the surface of this U-groove 50 is used for the channel region, a low ON-resistance can be obtained. Moreover, as two processes of the chemical dry etching and the oxidation are applied to the formation of the U-groove 50 for the channel region, when the U-groove 50 is desired to be formed to a specified width, all that is required is to control the width to be oxidized. Therefore, the shape of the second groove can exactly be controlled.

Furthermore, according to this embodiment, as the chemical dry etching process is isotropic according to the present invention, the groove 64 has no corner part and consequently the U-groove 50 formed by oxidation has no corner part, whereby the withstand voltage between the drain layer and the source layer can be improved. Moreover, an angle in the neighborhood of the surface of the n.sup.- -type epitaxial layer 2 of the groove 64 is nearly 90.degree. and the angle of inclination of the side surface of the U-groove 50 formed after the selective oxidation can be made sharp, whereby the cell size can be reduced and a low ON-state voltage can be obtained.

On the other hand, as the chemical dry etching uses gas containing carbon tetrafluoride and oxygen, the process can exactly be performed with a high reproducibility by controlling the ratio of the carbon tetrafluoride to the oxygen.

In addition to the above, according to this embodiment, as there is no substantial cathode drop on the upper part of the semiconductor substrate 1 or the n.sup.- -type epitaxial layer 2 during the chemical dry etching process, there is no possibility that the ionized gas collides against the surface of the semiconductor layer at such a speed that the collision gives defects to the surface of the semiconductor. Accordingly, the surface of the formed groove 64 has a few defects.

Besides the above, according to this embodiment, as the oxidation process is a selective oxidation process for selectively oxidizing the groove 64, the depth of the groove 64 can be increased. Also, as the mask used in the chemical dry etching process can be used as it is in the selective oxidation process, there is no need to form a new mask or perform a mask alignment.

Furthermore, the process for exposing the channel region by removing the oxide film after the oxidation process is performed while terminating the dangling bond on the surface of the n.sup.- -type epitaxial layer 2 with hydrogen within an aqueous solution. As a result of this process, the highly reactive dangling bond reacts to the hydrogen before reacting to the contaminant into a stable state, whereby the reaction of the contaminant to the n.sup.- -type epitaxial layer 2 can be prevented. Subsequently, when the dangling bond is exposed to the oxygen, a more stable oxide film can be formed, whereby the surface of the U-groove 50 can be protected and the following contamination of the channel region can be prevented, whereby a high channel mobility can be obtained and a low ON-state voltage can be realized.

Furthermore, the removal of the oxide film is performed within an aqueous solution including hydrofluoric acid, the selection ratio of the oxide film to be removed and the n.sup.- -type epitaxial layer 2 not to be removed can be set to be a very large and the oxide film can be removed without damaging the surface of the n.sup.- -type epitaxial layer 2.

Still furthermore, as the base layer and the source layer are formed in self-alignment with the selective oxide film, there is no alignment, whereby the base layer and the source layer can be formed in an exact position and consequently the area of the semiconductor device can be reduced.

Moreover, because light is not irradiated onto the surface of the oxide film during the oxide film removal process, there is no light irradiated onto the semiconductor layer to be a channel region through the oxide film. Accordingly, as the electric potential of the n.sup.- -type source layer 4 is almost equal to the electric potential of the p-type base layer 16 both in the neighborhood of the channel region, the development of etching from a limited part can be prevented and a uniform etching is possible. As a result, a flat channel region can be obtained and a high mobility can be realized.

On the other hand, as the index of plane of the side surface of the U-groove 50 formed by removing the selective oxide film is (111), the silicon atoms of the side surface of the second groove can be terminated with a single piece of hydrogen and the side surface can be flat in terms of atomic order, whereby a high channel mobility can be obtained. Furthermore, as the oxide film removal process is performed within an aqueous solution of pH4 or more, the possibility of terminating the silicon atoms of the side surface of the U-groove 50 with a single piece of hydrogen can become higher and the (111) surface flat in terms of atomic order can be obtained, whereby a high channel mobility can be obtained.

In short, in the above embodiment, the surface of the silicon substrate 1 with an index of plane of (100) is used, the conditions of etching and selective oxidation are selected by using an oxidation resistant mask patterned at a roughly right angle or in roughly parallel to an direction of <011> on the surface of the silicon substrate 1, an angle of the side surface of the U-groove 50 to the surface of the substrate 1 is exactly be controlled and thereby the side surface of the U-groove 50 is made to be an equivalent crystal surface with an index of plane of (ABB). As a result, the side surface of the U-groove 50 can be made to be crystal surface, the channel mobility can be made high and the ON-resistance can be reduced. Here, when the angle .theta. of the side surface of the U-groove 50 to the surface of the substrate 1 is controlled to be 54.7.degree., a crystal surface with a high mobility and an index of plane of (111) as per this embodiment can be obtained, whereby the ON-resistance can be reduced.

Also in this embodiment, as illustrated in FIG. 20, the gate oxide film 8 is the thin film part .lambda. with a uniform in thickness and thin film at the part 501 in the neighborhood of the semiconductor region 4 with a low surface impurity concentration. Therefore, when a voltage is applied to between the gate electrode 9 and the source electrode 19, as the electric field is not mitigated, electrons are accumulated on the surface thereof, the surface electron density increases and the resistance of the source layer 4 decreases, whereby the ON-resistance can be reduced.

As the gate electrode end part is the thick film part x of the gate oxide film 8, the electric field is mitigated and the life time of the gate oxide film 8 can be elongated.

In the above description, only the case where the gate oxide film 8 is uniform in thickness and thin at the part 501 where the surface impurity concentration is low is treated. Also in a care where the film thickness of the gate oxide film 8 is not uniform, as the gate electrode 9 is formed through the gate oxide film 8, electrons are accumulated on the surface thereof and the surface electron density increases, whereby the ON-resistance can be reduced.

Furthermore, as illustrated in FIG. 23, it may be so constructed that the gate electrode 9 is lengthened by .beta. on the gate oxide film on the surface part 501 of the semiconductor region 4 in the neighborhood of the U-groove 50 of the semiconductor region 21 where the impurity concentration is higher compared with the impurity concentration of the surface of the flat part of the semiconductor region 4.

Now, the effect of the above arrangement as illustrated in FIG. 23 will be described.

When a voltage is applied to between the gate electrode 9 and the source electrode 19, electrons are accumulated on the part 501 in the neighborhood of the U-groove 50 on the flat part of the surface of the semiconductor region 4 by the gate electrode 9 formed with an elongation of .beta. on the upper part of this low impurity concentration part and the surface electron density increases. As a result, the resistance of the source layer 4 decreases and the ON-resistance can be reduced.

As described above, it has been considered that by performing the LOCOS oxidation after the physical etching such as RIE or the wet etching, the lattice defects introduced in the initial groove (the first groove, i.e., the groove 64) formation process could be removed by performing the LOCOS oxidation and removing the LOCOS oxide film. However, as a result of actual experiments by the inventors, it was confirmed that the lattice defects introduced in the initial groove formation process could not be removed and remain on the surface of the channel region and this resulted in the cause of the leak current between the drain electrode and the source electrode and findings that the initial groove formation process had to be free from lattice defects. However, the chemical dry etching known as a process without defect as in wet etching is slower in etching speed than the wet etching and is isotropic the wet etching but causes side etch and therefore is not suitable to micronization. Accordingly, from the viewpoint of the current technique of reducing the channel resistance and the ON-resistance by shortening the channel length by micronization, the chemical dry etching has been considered to be not suitable to the groove formation process. However, in the initial groove (the first groove, i.e., the groove 64) formation process by performing the LOCOS oxidation after etching, although there is a little difference in the time required for the etching between the chemical wet etching and the chemical dry etching, the lattice defects on the surface of the channel region which is ultimately obtained are a few and the plane of any index can be formed exactly.

Although only one embodiment of the present invention has been described herein, it may be apparent that the present invention may be embodied in many other forms without departing from the spirit or the scope of the invention. For example, in the above embodiment, the silicon surface is protected by applying a natural oxide film by means of natural oxidation after removing the LOCOS oxide film within the aqueous solution containing hydrofluoric acid. This process, however, may be performed at a high temperature such as 900.degree. C. A resist mask may be used for the formation of the n-type source layer and the p-type source layer after removing the LOCOS oxide film. Furthermore, the plane orientation of the silicon substrate and the patterning shape may be selected so that the index of plane of side surface of the U-groove can be (110) or (100).

Now, a manufacturing method for a semiconductor device which makes the plane orientation of the side surface of the groove to be a (110) plane will be described only as to those parts which are different from the first embodiment.

In the silicon nitride film patterning process illustrated in FIG. 6, the silicon nitride film 63 is patterned to be perpendicular and parallel to an orientation of <001> and an open pattern is formed with opening at a pitch a as illustrated in FIG. 24.

By using this silicon nitride film 63 as a mask, the chemical dry etching and the LOCOS oxidation are performed. In this process, the conditions of the chemical dry etching and LOCOS oxidation are selected by controlling an angle .theta. which is an angle of the side surface of the U-groove 50 to the surface of the substrate 1 illustrated in 8 so that the index of plane of the channel formation part on the side surface of the U-groove 50 can be approximated to (110).

In the oxidation process illustrated in FIG. 15, it is advisable to perform the above process by forming the oxide film on the surface side 5 of the U-groove 50 of the p-type base layer 16 on which a channel is to be formed until the (110) plane can be formed.

The effect of the second embodiment will be described. By making the side surface of the U-groove 50 to be a crystal surface with the (110) plane having a high channel mobility, the channel mobility can be increased and thereby the ON-resistance can be reduced.

Although description has been given only to a case where the side surface of the U-groove 50 is made to be a crystal surface with the (110) plane, it is acceptable that the side surface of the U-groove 50 is made to be a crystal surface with the (AB0), wherein A and B are integers, to increase the channel mobility and decrease the ON-resistance.

That is, when the silicon substrate 1 with an index of plane of (100) is used, the conditions of the etching and selective oxidation is selected by using an oxidation resistant mask patterned at a roughly right angle or roughly parallel to an orientation of <001> of the surface of the silicon substrate 1 and an angle .theta. of the side surface of the U-groove 50 to the surface of the silicon substrate 1 is controlled, the side surface of the U-groove 50 can be made to be an equivalent crystal surface having the index of plane of (AB0), wherein A and B are integers. As a result, the side surface can be made to be a crystal surface and the channel mobility can be increased, whereby the ON-resistance can be reduced. Particularly, in the second embodiment, by controlling an angle .theta. of the side surface of the U-groove 50 to the surface of the silicon substrate 1 to be 45.0.degree., the side surface of the U-groove 50 can be made to be an equivalent crystal surface with an index of plane of (110), whereby the ON-resistance can be reduced.

In the above description, the silicon substrate 1 with an index of plane of (100) is used and the oxide resistant mask patterned at a right angle and parallel to an orientation <011> or <001> of the surface of the silicon substrate 1. However, even if this condition is deviated from the above, as long as the channel mobility on the four planes of the side surface of the U-groove 50 can be improved and the an interfacial level can be formed with a high symmetry, this case can be included in the present invention.

Also, in the above embodiment, the lattice-like pattern is used for patterning at a right angle and parallel to an orientation of <011> or <001>. The present invention, however, should not be limited to the lattice-like pattern but a stripe-like pattern may also be used and the patterning may be at either a right angle or parallel to an orientation of <011> or <001>.

In the various embodiments, only the application of the present invention to a vertical type power MOSFET has been described. The present invention, however, may also be applied to a power MOSIC with an incorporation of a vertical type power MOSFET. Furthermore, in the present embodiments, description has been given to a vertical type power MOSFET using an n.sup.+ -type semiconductor substrate as a semiconductor substrate, but the present invention may also be applied to a gate construction of an IGBT (insulating gate type bipolar transistor) using a p.sup.+ -type semiconductor substrate.

In addition, the chemical dry etching process may be performed with a gas system which include one or more than one of CCl.sub.4, Cl.sub.2, SF.sub.6, CFCl.sub.3, CF.sub.2 Cl.sub.2, CF.sub.3 Cl, CHF.sub.3, C.sub.2 ClF.sub.5, F.sub.2, NF.sub.3 and BCl.sub.3, whereby the efficiency of this etching process can be increased.

Moreover, in the current embodiments, the chemical dry etching is performed without applying a voltage to the semiconductor substrate, but the chemical dry etching may also be performed within the ionized gas atmosphere with a cathode drop on the upper part of the semiconductor layer of less than 10V in absolute value. As a result of this chemical dry etching, it is not possible that the ionized gas collides at a speed that may cause defects to the surface of the semiconductor layer and the surface of the formed groove 64 can be a surface with a few defects.

Furthermore, in the current embodiments, description has been given only to the n channel type, it is needless to say that the p-channel type can have the same effect as the n channel type.

While the present invention has been shown and described with reference to the foregoing preferred embodiments, it will be apparent to those skilled in the art that changes in form and detail may be made therein without departing from the scope of the invention as defined in the appended claims.