Management of Memory Modules

The present invention concerns the management of memory modules within a computing system.

Computing systems generally use various types of technology to store data. For long term storage of data, disk drives are typically used. Disk drives provide for the permanent storage of large amounts of data. However, the access of data from disk drives is relatively slow as compared to other technologies. Memory that is accessed by a processor during runtime is generally stored in some form of random access memory (RAM) or read-only memory (ROM). RAM provides for relatively fast access of data. However, generally RAM is not utilized for the permanent storage of data because of the high relative cost and because of the volatility of many types of RAM. That is, when power is removed from many types of RAM, data stored in the RAM is lost.

In many computing system, random access memory (RAM) capacity is added using memory modules. For example, computer mother boards often have slots which will receive single in line memory modules (SIMMs) or dual in line memory modules (DIMMs). DIMMs typically have double the data width of a SIMM.

As there is an increase in the amount of data stored increases, so does the potential value of a DIMM. This raises the importance of accurately tracking the use of DIMMs, for example for the purpose of properly determining warranties, detecting counterfeits and so on. Currently, such tracking is not performed or is done rather primitively, for example, by stamping a serial number on the module. It is desirable, therefore, to provide more comprehensive management of memory modules.

In accordance with the preferred embodiment of the present invention, a system is presented for managing a memory module within a computing system. Within the memory module, a management memory is provided. The management memory provides permanent storage for management information. For example, an error log is stored within the management memory. The error log indicates a time stamp for errors which occur in operation of the memory module. The error log consists of, for example, two lists. A first list indicates a time stamp for each (soft) correctable error which occurs in operation of the memory module. A second list indicates a time stamp for each (hard) non-correctable error which occurs in operation of the memory module.

When the first list is full, the first list wraps by overwriting entries in the first list when new correctable errors occur in operation of the memory module. Likewise, when the second list is full, the second list wraps by overwriting entries in the second list when new un-correctable errors occur in operation of the memory module. A first wrap count which indicates a number of times the first list wraps around and a second wrap count which indicates a number of times the second list wraps around are stored in the management memory. When the first wrap count or the second wrap count reaches a maximum value, the pertinent wrap count is frozen at the maximum value.

In the preferred embodiment of the present invention, other historical information about the memory module is stored in the management memory. For example, a time stamp is stored which indicates when the memory module was first placed in service. Also, in the preferred embodiment, a cyclic redundancy checksum is stored in the management memory as a security check for information stored in the management memory. For additional security, the cyclic redundancy checksum is calculated using a string of bytes within a program area of a microprocessor which accesses the management memory.

In the preferred embodiment of the present invention, the management memory is used within a management system within a computing system. The management system manages the memory modules within the computing system. The management system also includes indicating lights and a management controller. The management controller accesses the management information within the management memory and causes the indicating lights to indicate information about the memory modules. For example, each memory module slot has an associated indicating light. When the indicating light is off, this indicates there is no memory module within the memory module slot. When the indicating light flashes at a first rate, this indicates that the memory module within the memory module slot is not operating properly within the computing system. When the indicating light blinks at a second rate, this indicates that the memory module within the memory module slot is not from a particular entity. When the indicating light is on steadily, this indicates that the memory module within the memory module slot is from the particular entity. In the preferred embodiment of the present invention, the indicating lights are additionally used to indicate status of a central processing unit for the computing system.

The present invention provides an efficient way to manage memory modules within a computing system.

FIG. 1 is a simplified block diagram of a processor board which includes DIMMs which are implemented, for example, using dynamic random access memory (DRAM) in accordance with a preferred embodiment of the present invention.

FIG. 2 is a simplified block diagram showing a management system for the processor board shown in FIG. 1 in accordance with a preferred embodiment of the present invention.

FIG. 3 illustrates the calculation of a value to be placed within a linear feedback shift register in accordance with a preferred embodiment of the present invention.

FIG. 4 shows status patterns displayed by LED indicators for CPU errors in accordance with a preferred embodiment of the present invention.

FIG. 1 is a simplified block diagram of a processor board 10 used in a computing system which functions, for example, as a network server.

A processor 11 and a processor 12 are connected to a processor bus 10. For example, processor 11 and processor 12 are Pentium Pro processors available from Intel Corporation, having a business address of 2200 Mission College Boulevard, Santa Clara, Calif. Processor bus 10 is, for example, a P6 processor bus. A clock generator 13 generates clock signals for entities on processor board 10.

Also connected to processor bus 10 is an input/output (I/O) bridge and memory controller 14. I/O bridge and memory controller 14 serves as a bridge between processor bus 10 and an I/O bus 17. I/O bus 17 is for example, a Peripheral Component Interconnect (PCI) bus. I/O bridge and memory controller 14 also controls accesses to DIMMs 16. DIMMs 16 are composed of, for example, dynamic random access memory (DRAM). A data bus accelerator 15 accelerates access to DIMMs 16 from processor bus 10. A baseboard interface 18 provides connectivity between processor board 10 and other entities in the computing system. A memory management controller 31 and a system management controller 33 are part of a management system further described below.

FIG. 2 is a simplified block diagram showing the management system for processor board 10 shown in FIG. 1. DIMMs 16, shown in FIG. 1, are represented in FIG. 2 as a DIMM 34, a DIMM 35, a DIMM 36 and a DIMM 37. Each of DIMMs 34 through 37 include a non-volatile management memory. For example, DIMM 34 includes an electrically erasable programmable read-only memory (EEPROM) 38, DIMM 35 includes an EEPROM 39, DIMM 36 includes an EEPROM 40 and DIMM 37 includes an EEPROM 41. Within each EEPROM is stored management information about the DIMM, as is further described below. Processor board 10 also has non-volatile memory, for example EEPROM 42, in which is stored management information about processor board 10. EEPROMs 38 through 42 are accessed via a memory management bus 48. Memory management bus 48 is, for example, a two-wire secondary I.sup.2 C bus. Memory management controller 31 controls memory management bus 48. Memory management controller 31 is, for example, an 8xC751 I.sup.2 C controller available from Philips Semiconductors, having a business address of 811 E. Arques Avenue, Sunnyvale, Calif. Memory management controller 31 includes output ports on which is connected a light emitting diode (LED) indicator 51, an LED indicator 52, an LED indicator 53 and an LED indicator 54. Also status input ports of management controller provide access of management controller for the purpose of determining status.

When no CPU error condition exists, LED indicator 51 through 54 indicate the status of DIMMs 34 through 37 respectively. When an LED indicator is off, this indicates that no DIMM is installed in the associated DIMM slot or that the installed DIMM has no EEPROM. When an LED indicator flashes at 1 hertz (Hz) 50% off and 50% on, this indicates that there is an uncorrectable error or an inappropriate DIMM in the associated DIMM slot. For inappropriate DIMMs, main processor 11 or 12 compares management information at power-up with the DIMM parameters supported by the system and tells memory management controller 31 to flash the appropriate LED if the DIMM is not supported. The parameters checked for support at start-up include, for example, memory type, data width of memory, RAS access time, CAS access time, interface levels, and so on. When an LED indicator blinks at 1 hertz (Hz) 90% on and 10% off, this indicates that there is a DIMM in the associated DIMM slot which is not from Hewlett-Packard Company. When an LED indicator is on, this indicates that there is a DIMM in the associated DIMM slot which is from Hewlett-Packard Company.

When a CPU error condition exists, LED indicator 51 through 54 alternate between the patterns shown in FIG. 4 at a rate of 1 Hz rate. The CPU patterns shown in FIG. 4 indicate the following five error conditions: (1) the primary CPU core voltage is bad; (2) the secondary CPU core voltage is bad; (3) over temperature; (4) the GTL voltage is bad; and, (5) the primary CPU is not installed.

Memory management controller 31 detects the third error conditions (over temperature) by an interrupt from CPU socket 55 or CPU socket 56 onto an interrupt line 57, shown in FIG. 2, or by an interrupt from processor 11 or processor 12 onto an interrupt line 58, shown in FIG. 2. Memory management controller 31 detects the first and second error conditions (CPU core voltage is bad), the fourth error condition (GTL voltage is bad) and the fifth error condition (primary CPU not installed) by inputs on other I/O ports 59, shown in FIG. 2.

Memory management controller 31 is connected to baseboard interface 18 through a system management bus 46. System management bus 46 is, for example, a two-wire I.sup.2 C NetServer system management bus available from Hewlett-Packard Company, having a business address of 3000 Hanover Street, Palo Alto, Calif. Baseboard interface 18 connects system management bus 46 through to entities off processor board 10. System management controller 33 controls system management bus 46. Management controller 33 is, for example, a PCF 8584 I.sup.2 C controller available from Philips Semiconductors.

System management controller 33 interfaces to the system central processing unit (i.e., processor 11 and processor 12), through the I/O bus system of the computing system. For example, system management controller 33 is connected to a bridge 32 through an I/O bus 44. For example, I/O bus 44 is a baseboard Industry Standard Architecture (ISA) bus. Bridge 32 is a PCI/Extended Industry Standard Architecture (EISA) bus bridge. Bridge 32 is connected to baseboard interface 18 through an I/O bus 45. I/O bus 45 is, for example, a PCI bus. Baseboard interface 18 connects I/O bus 45 to I/O bus 17, shown in FIG. 1.

In the preferred embodiment of the present invention, EEPROMs 38 through 41 each have a storage capacity of 256 bytes. In each of EEPROMs 38 through 41, 128 bytes of storage is reserved as an industry standard data area. See for example, The Preliminary Specification for "8 Byte Unbuffered Product Overview" Industry Standard, SA14-4619-00 Revised 10/95 available from IBM Corporation. See also the JEDEC Standard No 21-C. Table 1 below sets out the currently proposed use of the 128 bytes reserved as an industry standard data area.

The remaining 128 bytes of EEPROMs 38 through 41 are used to implement various features in accordance with preferred embodiments of the present invention. Table 2 below sets out the use of the 128 bytes in accordance with a preferred embodiment of the present invention.

Table 3 below gives an explanation for symbols used in Tables 1 and 2, above.

As shown in Table 2, management data stored within the 128 bytes of EEPROMs 38 through 41 are used to store information identifying information about the DIMM. Bytes 0 through 21 gives information such as the manufacturer's name, product or accessory number, part number, Company Division, and Revision letters. The management data and the error log stays with the DIMM even when the DIMM is removed from one computing system and added to another computing system. The accessory number allows a service representative, without physically looking at the DIMM, to determine whether the DIMM was from a particular company. For example, this information is available by observing LEDs 51 through 54 or by accessing management information in the EEPROMs electronically.

For example, the EEPROMs are accessed electronically via I/O bus 17 using one of processors 11 or 12, or through an I/O card which is connected to I/O bus 17. For example, the I/O card is a Remote Assistant I/O card available from Hewlett-Packard Company. The EEPROMs are accessed via processor 11 or 12 using management software. For example, the management software is NetServer Assistant (NSA) management software available from Hewlett-Packard Company. Access to the EEPROMs through I/O bus 17 is through bridge 32, through system management controller 33 through management bus 46 and through memory management controller 31.

Bytes 28 through 30 contain the number of writes made to the EEPROM. Bytes 31 through 47 give additional information about the DIMM. For example, bytes 42 and 43 contain a two-byte time stamp which indicate the date the DIMM was turned on. Bytes 48 through 49 gives additional manufacturing data

Bytes 126 and 127 is two unsigned bytes of data which are used to implement a Cyclic Redundancy Checksum (CRC) security system. The CRC is generated as a pseudo-random number using a linear feedback shift register (LFSR) implemented in firmware.

FIG. 3 is a schematic of an implementation of the system which generates the CRC. An LFSR includes an LFSR byte 73 and an LFSR byte 74. At the start of the sequence, the LFSR is initialized to a known value (usually non-zero). Data is read from the EEPROM a byte at a time and loaded into a data shift register 71. Data shift register 71 and the LFSR bytes 73 and 74 are then shifted 8 times. The bit shifted out of the most significant bit of data shift register 71 is XOR'd by XOR gate 72 with the bit shifted out of the most significant bit of LFSR byte 74. The result is shifted into the least significant bit of LFSR byte 73.

After all eight bits of data register have been shifted out, a new byte is read and the process repeated. After all of the bytes of data have been processed, the Cyclic Redundancy Checksum (CRC) is unloaded from the LFSR byte 73 and LFSR byte 74 and stored in bytes 126 and 127 of the EEPROM as shown in Table 2.

To verify data integrity in the EEPROM, the same process is used to generate a CRC which is then checked against the value stored in bytes 126 and 127. If they match then the data can be assumed to be correct.

Since this is a fairly simple algorithm, in the preferred embodiment, security has been added by two means. First,the value in LFSR byte 73 and LFSR byte 74 is initialized to one of 2.sup.16 possible values. Second, there is a string of bytes within the program area of the memory management controller 31 which are included into the CRC generation. Since the program area of the memory management controller 31 can be read protected, determining either of these values would either be impossible or too difficult to be worth doing by an unauthorized user.

Bytes 22 through 27, and 50 through 125, shown in Table 2, are used to perform error logging. In the preferred embodiment of the present invention, there are two types of errors logged: correctable errors and noncorrectable errors. Whenever I/O bridge and memory controller 14 detects an error, an interrupt to main processor 11 or 12 will be generated which will cause the system to log an error. A two byte timestamp consisting of the day, month, year, and 3 hour period of the day is generated by processor 11 or 12 executing firmware. The processor then sends an I.sup.2 C message through baseboard interface 18 (shown in FIG. 2) to system management controller 33 which forwards the I.sup.2 C message back through baseboard interface 18 to memory management controller 31. Memory management controller 31 logs the error message within the correct EEPROM.

Memory management controller 31 reads values stored in byte 22 or byte 25 (shown in Table 2) of the EEPROM on the DIMM to determine the location of the next available memory location in the EEPROM memory to save the error information. Two error logs are implemented as circular buffers. The correctable error log contains 32 (two byte) memory locations (bytes 54 through 117) and the non-correctable error log contains four memory locations (bytes 118 through 125). For the preferred embodiment the number of memory locations for each type of error were selected out of a compromise of space in the EEPROM and the relative frequency that the errors were expected. Each error log entry is a two-byte time stamp.

When either error log is full, the full error log will wrap to its beginning and start overwriting older entries. A count of how many times the buffer has wrapped is kept to allow calculation of how many errors were logged. For the correctable errors, this count is in byte 24 of Table 2. For the un-correctable errors, this count is in byte 27 of Table 2. Each wrap count is locked when it reaches 255.

Table 4 below is a code listing for firmware or software which generates time stamps for errors and performs CRC checking.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art,the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.