Control of a Power Amplifier Stage of a Portable Transceiver

This invention relates to portable radio transceivers, such as portable telephones.

A major problem with portable telephones is providing sufficient battery capacity for long periods of use and to that end the circuits employed have been developed to operate on quite low voltages, such as 6 volts. Also, in the interests of economy of consumption the circuits of such telephones are predominantly in the form of integrated circuits using transistors of very small size, but such integrated circuits have limited power handling ability. That limitation is not a problem in the transmitter itself because the output power amplifier is usually a discrete device, such as a gallium arsenide transistor. However, there is a need to switch the power supply to the transmitter on and off and that operation is normally done by a conventional silicon MOS transistor. It would be desirable to integrate that transistor with the control and signal processing circuitry, but the power switching requirements of that transistor can mean that its size is incompatible with that of the other transistors so that the integration is undesirably complicated.

It is an object of the present invention to alleviate the problem just described.

According to the present invention there is provided a portable radio transceiver having a gallium arsenide depletion mode n-channel field-effect transistor as a transmitter power amplifier, means for providing a negative voltage supply that is connected to the gate of that transistor and a PMOS enhancement mode transistor that is switched by voltage applied to its gate to pass or to block a positive voltage supply to the gallium arsenide transistor to enable or disable transmission by the transmitter, in which the negative voltage supply is also used to augment the gate voltage applied to the PMOS transistor when conducting so as to reduce its resistance.

The reduction of the resistance of the PMOS transistor when it is conducting has the advantage that it enables a smaller transistor to be used than would be needed if the gate of the transistor were to be connected to ground (0 v). Ideally, the size of the transistor should be such that its geometry is compatible with that of transistors of an integrated circuit used to perform at least some of the functions of a portable telephone so that all the transistors can readily be formed in the same integrated circuit. The switching speed of the PMOS transistor may also be increased as a result of the reduction in size and the use of a larger swing in the gate driving voltage.

The invention will be described in its application to a portable telephone but it is also applicable to other apparatus such as portable radio transceivers for military and civil personal communications.

FIG. 1 is a diagram showing a power supply circuit for a portable radio transmitter.

In order that the invention may be fully understood and readily implemented, a power supply circuit for a portable radio transmitter will now be described with reference to the single figure of the accompanying drawing.

The single figure of the drawing shows a radio transmitter 1 connected to an antenna 2 and having power supply input conductors 3 and 4. The conductor 3 is connected through a PMOS transistor 5 to a terminal 6 for connection to the positive terminal of a battery (not shown). The conductor 4 is connected to chassis ground and to a terminal 7 for connection to the negative terminal of the battery. A charge pump 8 is also connected to the terminals 6 and 7 and serves to generate a negative supply voltage, relative to the conductor 4, on a conductor 9, which voltage is stored on a capacitor 10. As indicated, in the transmitter 1 the power amplifier is an n-channel gallium arsenide MESFET 11 which requires a negative bias on its gate for its operation driving a resonant tank circuit, for example, as a class C amplifier. The resonant tank circuit and the drive circuitry for the power amplifier are not shown because they may be of any suitable conventional form. The negative bias for the gate of the transistor 11 is derived from the conductor 9 by circuitry represented by the rectangle 12. The conductor 9 is also connected to the gate of the transistor 5 through a TRANSMIT switch 13 and a level shifter 14. The switch 13 is shown as a mechanical switch although in a practical circuit it is likely to be an electronic switch in the same integrated circuit as the transistor 5 and the level shifter 14.

Typically the battery voltage is between 4.5 and 7.5 volts and the negative voltage generated by the charge pump 8 and stored on the capacitor 10 lies between 3 and 6 volts.

The gallium arsenide transistor 11 is an n-channel depletion mode device and requires a negative bias on is gate to set it to its working point for operation so that it does not draw undue current and become overheated.

The circuit makes use of the negative supply needed by the gallium arsenide power amplifier transistor to enable a large voltage swing to be applied to the gate of the transistor 5. The transistor 5 is an enhancement-mode p-channel MOS device which is normally non-conducting and responds to a relatively large negative voltage, say -10 volts, on its gate relative to the source to become conducting very rapidly and to have a very low resistance. Whilst the transistor 5 could be switched to be conducting by a smaller negative voltage say -5 volts, which could be derived from the conductor 4 (at 0 volt). When operated under such conditions the transistor 5 would have a larger forward conduction resistance so that it would consume such an amount of power that dissipating the heat generated could be a problem in an integrated circuit. Moreover, the power consumed by the transistor 5 would detract from the power that could be generated by the power amplifier transistor 11. Whilst those difficulties could be overcome by making the transistor 5 a larger device, that would make it much harder to integrate with the other transistors used in the transceiver, as mentioned above.

It is desirable to arrange that should the negative supply fail for any reason then the transistor 5 would remain non-conducting so that no positive supply would be applied to the power transistor 11. The failure of the negative supply would mean that the negative bias is not applied to the gate of the power transistor 11, in which case if the positive supply were to be maintained the transistor would pass a large current which could damage or even destroy the transistor. Since the transistor 5 is a PMOS enhancement mode device its channel is non-conducting unless a suitable bias is applied to its gate, therefore what is required to ensure its non-conductive state if the negative supply were to fail is that either no voltage is applied to its gate or the gate voltage is non-negative. This precaution has the additional advantage that in normal operation the positive supply cannot be applied to the power transistor 11 before its negative bias, even if the negative supply is slow to build up.

The charge pump 8 used to generate the negative supply could be replaced by a suitable battery.