Memory Row Redrive

This invention relates to information processing computer systems and more particularly to computer systems in which the main memory is implemented with dynamic random access modules (DRAMs).

Memory controllers which multiplex the row and column addresses onto a single bus and which generate the critical row and column address strobes (RAS and CAS) sequences required by main memories (hereinafter referred to as Basic Storage Modules or BSMs) exist today. A typical memory controller to BSM interface sequence is shown in FIG. 2. The prior art hardware which generates such interface sequences is shown in FIG. 1.

Referring to FIGS. 1 and 2, there is illustrated the hardware and the operational timing waveforms for a particular prior art system. Processor fetch and store requests are prioritized by the priority logic 11 in the memory controller (PMC) 10. When a given operation has been selected, the priority logic 11 provides an active status on the array start line. This array start active signal is applied to select gate 15 to select the row and then the column addresses to be gated into the row/column address latch 17. The row address in this particular system is selected in the first cycle of the array operation (or access) and then the column address is selected just prior to the fifth cycle of the access. Also the array start activates an array timer 19 which is a counter. On receiving active array start status the array timer 19 is initialized to a count of one. A clock 19a is inputted into the array timer 19 to increment the counter every cycle. The output of the array timer 19 is applied to timing logic 18, which immediately provides an address valid for the first cycle of the access, and when there is a count of four to eleven cycles, provides an active row address strobe (RAS) signal (low level) to the RAS latch 23 on the BSM card 20. Also at about a count of six cycles, the CAS signal (column address strobe) is provided to the CAS latch 22 on the memory card 20. The memory card control logic 20a includes a row/column address latch 21, CAS latch 22 and RAS latch 23. Also the timing logic 18 provides an address valid when the counter reaches a value of five cycles. The address valid signal from logic 18 gates the latch 21 in memory card 20 to latch the row and column address applied through the interface at the card row/column address latch 21. The row/column address at latch 21 which is part of the memory card control logic 20a is sent on to address the DRAMs along with the RAS signal from DRAM control latch 23 and the CAS signal from DRAM control latch 22. The DRAMs are a plurality of memory chips on the memory card 20 which receive the addresses and the RAS strobe and CAS strobe signals which are sequenced as shown in FIG. 2 during memory read and write operations.

One method of speeding up the access has been the static column mode system or page mode system as discussed for example in U.S. Pat. No. 4,803,621, U.S. Pat. No. 4,807,622, U.S. Pat. No. 4,839,796, U.S. Pat. No. 4,823,324, U.S. Pat. No. 4,623,986. In this mode the RAS strobe remains active or low in the waveform of FIG. 2 until a change in the row address of sequential accesses is detected. In this mode of operation the data access time is reduced when sequential accesses are to the same row. However, when sequential accesses are to different rows a substantial penalty in access time (or latency) is observed. This increased latency under this page or static column mode operation is incurred in deactivating RAS, observing a RAS precharge time and re-activating RAS for the new row address. Thus the benefits of page or static column mode operation are dictated by the memory referencing patterns of the processing system. The subject invention, like page or static column mode operation, exploits the locality of memory references but without the increased latency problem just described.

In accordance with one embodiment of the present invention an improved memory access system is provided by a memory for storing data wherein the memory includes a plurality of storage locations, each of the locations specified by one of a plurality of first addresses followed by one of a plurality of second addresses. A controller for accessing the data at specified locations is provided by a first address and a first strobe signal followed by a second address and a second strobe signal. The first strobe signal goes inactive before the beginning of the next access. The memory, when the first strobe signal goes inactive, automatically switches from the second address back to the previous first address. A controller further includes a device for storing the first address and on each access, comparing the next first address with the previous first address and if there is a match, immediately activating the first strobe signal to the memory to permit the previous first address to access the memory, and if there is not a match, accessing said memory by the new first address and the first strobe signal.

FIG. 1 is a prior art hardware which generates the interface sequence as shown in FIG. 2.

FIG. 2 is a timing diagram for a prior art memory controller.

FIG. 3 is a memory row redrive according to one embodiment of the present invention.

FIG. 4 illustrates the waveforms for the operation of the system in accordance with FIG. 3.

Referring to FIG. 3 there is illustrated the memory row redrive system in accordance with the present invention wherein in addition to the hardware described in connection with FIG. 1, there is in the memory controller 10, a previous row address latch 50, an AND gate 53, a selector 55 and compare circuit 51. Selector 55 normally provides a count of "one" to array timer 19. The row address compare circuit 51 is coupled to receive the current row address and a previous row address from register 50. Latch 50 receives the current row address and latches this address when the array start is active. The output from the previous row latch 50 is provided to the compare circuit 51 for comparing the current row address with the previous row address. The output of the compare circuit 51 is ANDed with the array start signal at gate 53 for selecting or preloading a count value greater than one from selector 55 into the array timer 19 to skip memory access cycles. In the embodiment described herein when there is a compare at circuit 51 and the array start becomes active the AND gate 53 output causes the count of four to be loaded into the array timer 19 from select 55, allowing immediate generation of the RAS signal from the timing logic 18.

To the memory card control logic 20a is added select gate 25, Previous Row Address Register 27, RAS Edge Detect Logic 29 and flip-flop device 31. The output from the row/column address latch 21 is sent to the "0" input of select gate 25 which normally gates the output from the row/column address latch 21 to the DRAMs. The row output from the row/column latch 21 address is also applied to the Previous Row Address Register 27 which latches the previous row address when gated by the RAS falling edge (low level is active state). The BSM further includes a RAS edge detect logic 29 which detects the RAS falling edge and provides the enable gate to latch the row address at register 27. The detect logic 29 also detects the RAS rising edge and provides a set signal to flip-flop 31. The set state of flip-flop 31 provides a switch control signal to Select gate 25 to drive the previous row address from Previous Row Address Register 27 to the DRAMS via the "1" input of selector 25. Note in FIG. 4 how upon the deactivation of RAS the previous row address is immediately sent to the DRAMs. The timing logic 18 provides an address valid both to the row/column address latch 21 and to flip-flop 31 to reset it. When the RAS edge detect logic detects a rising edge it sets flip-flop 31 and the previous row address is gated.

The timing sequence of the system shown in FIG. 3 is explained using the timing diagrams in FIG. 4. When the logic priority 11 detects a fetch or a store request, it provides an array start signal to select gate 15 to cause the initial row address to be gated into the row/column address latch 17 of the controller 10. That row address is also gated into the Previous Row Address latch 50. When the RAS detect logic 29 detects the RAS falling edge at a count of four, it provides a gating signal to the previous Row Address Register 27 to load the row address present at latch 21 in the Previous Row Address register 27. The initial row address is followed by the column address that is also gated via select 15 to the row/column address latch 17. Since there was no previous row there is not a compare at compare circuit 51 and as discussed previously, the normal count of one is selected at selector gate 55 and provided to the array timer 19. The timing logic 18 then provides the active RAS signal (low level) to the BSM logic 20 to latch 23 as discussed previously to provide the RAS to the DRAMs. The address valid applied from the timing logic gates the row address to latch 21 and resets flip-flop 31, which then gates the selector 25 to the position which normally couples the address at "0" input to the DRAMs. The address valid then inactivates for several cycles. As discussed previously, just prior to a count of five the column address is selected and latched in the row/column address latch 17 of the controller 10 via the select 15 and at the count of five latched in the BSM logic at latch 21 with the activation of address valid. Following the column address and at timing count of eleven the RAS strobe from the timing logic 18 goes high or inactive. This is detected by the RAS Edge Detect Logic 29 providing a set signal to flip-flop 31 to gate the previous row address from register 27 to the DRAMs. The row address associated with the next access is then compared to the Previous Row Address Register latch 50 and if there is a match at compare circuitry 51 and the array start is active, AND gate 53 provides a control signal to the selector 55 to "advance" the counter of array timer 19 a count of four rather than a count of one. Thereafter, as long as the rows match, the strobe is activated immediately since the previous row address is already stable at the inputs to the DRAMs. When the next address valid signal occurs in each access the flip-flop 31 is reset and places the select switch back to coupling from the "0" input position to receive the column address latched at gate 21. When there is not a compare at compare circuit 51 and the array start is active, the normal count of one is loaded in the array timer 19. The system operates in the original manner to not advance the count and to gate the current row address to the BSM. The timer logic 18 provides the RAS strobe between clock cycles of four to eleven, the CAS strobe at about the count of six and the address valid pulses at counts one and five.

While the invention has been described and illustrated at what is present to be considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof, without departing from the true scope of the invention.