Low Input Bias Current Circuit

1. Field of the Invention

The present invention relates to low input bias current circuits.

2. Description of the Related Art

Low input bias current circuits, such as amplifiers, are often used in applications with high source impedances to reduce the contribution of the amplifier noise and associated offset. Such low input bias current amplifiers are also used to perform very sensitive measurements, such as leakages, by taking advantage of the amplifier's low input bias current in integrator circuitry.

One problem with present low bias current amplifiers is that, when providing for ESD protection, it is often difficult to maintain low input bias currents, because the ESD circuitry itself draws some leakage or bias current from the external source circuitry supplying the input signal. Referring now to FIG. 1, there is shown a prior art circuit 100 for providing ESD protection for an input device such as operational amplifier ("op amp") 101. Op amp 101 requires ESD protection to protect it from an voltage spike appearing at terminal 102 (caused, for example, by ESD), which can damage op amp 101. Therefore, in the prior art two ESD protection diodes 110 and 111 may be connected as illustrated to input terminal 102 and to positive and negative voltage supplies 120, 121, as illustrated, in order to protect op amp 101 from ESD appearing at terminal 102. In circuit 100, ESD currents are thus shunted to the power supply terminals. Depending on the polarity of a voltage spike, such ESD current will flow to a power supply terminal by forward biasing either diode 110 or 111.

As will be understood, leakage currents I.sub.130 and I.sub.131 will flow through diodes 110 and 111, respectively, during the operation of circuit 100. Leakage currents I.sub.130 and I.sub.131, will typically differ, causing a bias, or leakage, current I.sub.132 to flow from or to the external user circuitry source supplying V.sub.140. As will be appreciated, such a current is referred to herein as a bias current, whether actually caused by a biasing current flowing into a device or whether caused by leakage currents such as referred to above. When the input voltage V.sub.140 applied to input terminal 102 varies above the midpoint of the positive and negative supply voltages, currents I.sub.130 and I.sub.131 may differ by an even greater amount, thereby causing an even greater bias current I.sub.132. Leakage currents I.sub.130 and I.sub.131 may also differ by a greater amount as temperature rises. A bias current I.sub.132 flowing from or to the external user circuitry supplying the input voltage signal V.sub.140 is often an undesirable effect of providing ESD protection in this manner because such bias current can produce damaging effects for some external source circuitry such as sensors, or can produce voltage offset errors and noise errors as the input bias current interacts with the source resistance of the source device.

Referring now to FIG. 2, there is shown another prior art circuit 200 for providing ESD protection for an input device. A circuit similar in operation to circuit 200 is described in U.S. Pat. No. 4,630,162, issued Dec. 16, 1986 to Bell et al., the entirety of which is incorporated by reference herein. As illustrated in FIG. 2, prior art circuit 200 employs pnp transistor 210 to reduce the bias current I.sub.240 by isolating the leakage current of ESD breakdown structure 220 from the input terminal 202. However, currents I.sub.241, and I.sub.242 can be present, so that bias current I.sub.240 is not negligible. Thus, both circuits 100 and 200 are characterized by input bias currents, which also increase with ambient temperature and that vary along with changes in the input voltage within its input common mode voltage range.

Additionally, some input devices themselves draw a bias current from the external user device that supplies an input voltage signal to the input device, independent of any leakage currents in the ESD protection circuitry.

Therefore, there is a need for circuits which reduce the input bias current drawn by input devices or by ESD circuitry.

There is provided herein a circuit and method for reducing an input bias current flowing from an external signal source coupled to an input terminal of the circuit, the circuit being coupled to an input device having a device leakage current related to a device voltage. According to a preferred embodiment of the invention, a replica voltage source provides a replica voltage equal to the device voltage. A cancellation device is coupled to the replica voltage source so that the replica voltage is applied to the cancellation device. The cancellation device is further coupled to the input terminal for providing a cancellation current equal to the device leakage current, wherein the input bias current is equal to the difference between the device leakage current and the cancellation current.

In another embodiment of the present invention, there is provided a circuit and method for protecting an input device coupled to an input terminal of the circuit from ESD appearing at the input terminal and for reducing an input bias current flowing from an external input voltage source coupled to an input terminal of the circuit. According to this preferred embodiment of the invention, a buffer means coupled to the input device provides an output voltage at an output terminal equal to the input voltage at the input terminal. An ESD protection means is coupled between the output terminal and the input terminal for protecting the input device from ESD events, whereby there is no voltage drop across the ESD protection means.

These and other features, aspects, and advantages of the present invention will become more fully apparent from the following description, appended claims, and accompanying drawings in which:

FIG. 1 shows a prior art circuit for providing electrostatic discharge ("ESD") protection for an input device;

FIG. 2 shows another prior art circuit for providing ESD protection for an input device;

FIG. 3 is a diagram of a circuit in accordance with a preferred embodiment of the present invention;

FIG. 4 is a diagram showing further details of a preferred embodiment of the circuit of FIG. 3; and

FIG. 5 is a diagram of another circuit in accordance with another preferred embodiment of the present invention.

The present invention, in a preferred embodiment, provides a circuit that has a low input bias current and that also provides ESD protection of an input device. In a preferred embodiment, a replica bias is employed which tracks the input voltage so as to provide another bias point which cancels the input device's leakage current. The present invention is described in further detail hereinbelow.

Referring now to FIG. 3, there is shown a circuit 300 in accordance with a preferred embodiment of the present invention. As illustrated, an input voltage V.sub.INPUT is applied to input terminal 351, typically by external user circuitry (not shown). Input device 301 is, in the illustrated embodiment, a junction field-effect transistor (JFET) 301. As will be understood by those skilled in the art, JFET 301 is an input device that receives an input signal V.sub.INPUT and provides an output signal V.sub.OUT (at output terminal 352) to further circuit elements (not shown). As explained hereinabove, there is a need to protect JFET 301 from ESD appearing at input terminal 351. There is also a need to reduce any bias current I.sub.INPUT that would flow from the external input source (not shown) that supplies V.sub.INPUT to input terminal 351.

Cascode 303 is coupled as illustrated between the source and drain terminals of JFET 301 and the negative supply voltage terminal 332. Cascode 303, as will be understood, maintains a constant voltage V.sub.GD across the gate to drain junction of JFET 301. In alternative preferred embodiments, as will be appreciated, a cascode may be coupled in another manner to maintain a constant voltage V.sub.GD, for example to the positive supply instead of to the negative supply. JFET 301 is biased by circuit 300 so that there is no voltage across the gate to source junction of JFET 301. Therefore, as will be appreciated, the gate to source junction of JFET 301 will not produce a leakage current flowing across the gate to source junction. However, the gate to drain junction provides a leakage current I.sub.GD proportional to V.sub.GD. Unless canceled, this leakage current I.sub.GD would otherwise cause an input bias current I.sub.INPUT of the same magnitude to flow. As will be appreciated, leakage current I.sub.GD will in general be related to the characteristics of the junction of the input device through which the leakage current flows, and to the voltage existing across this junction.

To cancel this leakage current, which would otherwise flow from input terminal 351, a replica bias voltage V.sub.REPLICA is applied by voltage source 310 between cancellation device 302 and output terminal 352 (which is also coupled to the source terminal of JFET 301), as illustrated in FIG. 3. Cancellation device 302 is designed with characteristics (e.g., a junction) similar to that of the input device that give rise to its own leakage current, so that when a matching voltage is applied thereacross a cancellation leakage current will be generated, having the same or nearly the same magnitude of the leakage current of the input device. This cancellation current reduces or eliminates the input bias current I.sub.INPUT. V.sub.REPLICA is the same magnitude as V.sub.GD, as will be understood, because there is no voltage drop across the gate to source junction of JFET 301. Thus, in circuit 300 a leakage current I.sub.CANCEL is provided that cancels leakage current I.sub.GD.

As discussed hereinabove, V.sub.GD may vary slightly with temperature, which may affect the canceling effect discussed herein. As will be appreciated by those skilled in the art, cascode 303 and replica bias voltage V.sub.REPLICA may be configured so that temperature variations are taken into account so that V.sub.REPLICA tracks the temperature-caused variations in V.sub.GD so as to minimize undesirable affects caused by variations in temperature. Thus, in the present invention, even when temperatures rise the input bias current I.sub.INPUT is greatly reduced in comparison to prior art circuits and techniques. Additionally, in circuit 300 I.sub.INPUT remains very small and relatively constant over the entire input common mode voltage range (i.e., as V.sub.INPUT varies within its permissible range).

Referring now to FIG. 4, there is shown a diagram showing further details of a preferred embodiment of circuit 300 of FIG. 3 which also provides for ESD protection while still reducing input bias current I.sub.INPUT. As illustrated in FIG. 4, circuit 300 shunts away positive ESD events to the positive supply at terminal 331 through cancellation device 302, here implemented by diode 302, and through diode 360. Similarly, negative ESD events are shunted through diode 361 and the forward biased gate to drain junction of the input device (JFET 301). Unlike prior art ESD protection circuits, the present invention provides for ESD protection while also providing for extremely low input bias current I.sub.INPUT.

FIG. 5 is a diagram of another circuit 500 in accordance with another preferred embodiment of the present invention. In circuit 500, input device 501 requires ESD protection and also has an effectively zero input bias current I.sub.DEVICE. For example, input device 501 may be a CMOS device that requires little or no input current I.sub.DEVICE. In prior art circuits ESD protection circuitry added to protect the input device would tend to have leakage currents, which would give rise to an input bias current. These problems are alleviated by the present invention. In circuit 500, ESD protection is provided by diodes 520-523. As will be appreciated, positive ESD events are shunted to the positive supply coupled to terminal 511 through diodes 522 and 520. Negative ESD events are shunted to the negative supply coupled to terminal 510 through diodes 521 and 523. Thus, the present circuit 500 provides for ESD protection for input device 501. As will be appreciated, the positive supply is positive relative to the operating voltage range of V.sub.INPUT, and the negative supply is negative relative to the operating voltage range of V.sub.INPUT.

Typically the voltage output V.sub.550 by input device 501 may be equal to V.sub.INPUT. Alternatively, V.sub.550 may be a function of V.sub.INPUT, such as V.sub.INPUT minus or plus a small voltage. Low output impedance buffer 502 takes as its input V.sub.550 and outputs V.sub.OUT, which is identical in magnitude to V.sub.INPUT. Thus, if V.sub.550 is equal to V.sub.INPUT, then buffer 502 is a unity gain buffer. If V.sub.550 is instead some function of V.sub.INPUT, then buffer 502 may be configured so that V.sub.OUT equals V.sub.INPUT. Because V.sub.OUT equals V.sub.INPUT, no current flows across the parallel-coupled diodes 522 and 523. Therefore, I.sub.ESD is zero, so that I.sub.INPUT =I.sub.DEVICE, which is very small. Therefore, the input bias current I.sub.INPUT is maintained at an extremely small magnitude (in typical embodiments, in the femto amp range) even while providing for ESD protection. Thus, the present invention as embodied in circuit 500 of FIG. 5 provides for ESD protection of an input device while also minimizing input bias current.

It will be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated above in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as recited in the following claims.