US 5,757,694 AGrant
Balanced Resistance Load Type SRAM Cell
Issue Date:1998-05-26
•3 Claims
•16 Drawing Sheets
Abstract
In a static semiconductor memory device including first and second power supply lines for a first voltage, a third power supply line for a second voltage, first and second nodes, and first and second drive transistors connected between the first and second nodes and the third power supply line, a first load resistor is connected between the first power supply line and the first node, and a second load resistor is connected between the second power supply line and the second node.
Metadata
Assignee
- NEC Corporation
Inventor
- Hitoshi Mitani
Application Information
Application Number:US 6207898
Filing Date:1996-03-28
Priority Date:1995-03-30
Art Unit:251
Classifications
IPC:
G11C 1100
Field of Search:
365257154;156;174903
Patent Drawings (16 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a resistance load type static random access memory (SRAM) device.
2. Description of the Related Art
A prior art SRAM cell is constructed by a flip-flop formed by cross-coupled first and second inverters and transfer gates connected to first and second nodes of the flip-flop. That is, the first inverter is formed by a first resistance element between a high power supply line and the first node and a first drive MOS transistor between the first node and a ground line. Similarly, the second inverter is formed by a second resistance element between the high power supply line and the second node and a second drive MOS transistor between the second node and the ground line.
Also, the first node is connected directly to a gate electrode of the second drive transistor, so that the second drive transistor is driven directly by the voltage at the first node. Similarly, the second node is connected directly to a gate electrode of the first drive transistor, so that the first drive transistor is driven directly by the voltage at the second node.
In the above-described prior art SRAM cell, however, the first and second resistance elements are made of the same conductive layer which is connected at a point of the high power supply line. Therefore, the resistance values of the first and second resistance elements are unbalanced, so that data retention characteristics are deteriorated. Further, the prior art SRAM cell is subject to soft errors caused by .alpha. rays. That is, the first and second nodes are constructed by impurity diffusion regions in a semiconductor substrate. Therefore, when .alpha. rays penetrate into the first and second nodes or neighboring regions, the voltages at the first and second nodes fluctuate. If the resistance values of the first and second resistance elements are unbalanced, the voltages at the first and second nodes fluctuate further. As a result, operation states of the first and second drive transistors may be reversed.
The prior art SAM cell will be explained later in detail.
Summary of the Invention
It is an object of the present invention to improve the data retention soft error resistance characteristics of a resistance load type static semiconductor memory device.
According to the present invention, in a static semiconductor memory device including first and second power supply lines for a first voltage, a third power supply line for a second voltage, first and second nodes, and first and second drive transistors connected between the first and second nodes and the third power supply line, a first load resistor is connected between the first power supply line and the first node, and a second load resistor is connected between the second power supply line and the second node.
Since the first and second load resistors are connected separately to the first and second power supply lines, the resistance values of the first and second load resistors can be balanced.
Brief Description of the Drawings
The present invention will be more clearly understood form the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:
FIG. 1 is an equivalent circuit diagram illustrating a prior art SRAM cell;
FIGS. 2A, 3A and 4A are plan views for explaining a method for manufacturing the SRAM cell of FIG. 1;
FIGS. 2B and 2C are cross-sectional views of the transfer transistor and the drive transistor of FIG. 2A;
FIG. 3B is a cross-sectional view of the transfer transistor and the drive transistor of FIG. 3A;
FIGS. 4B and 4C are cross-sectional views of the transfer transistor and the drive transistor of FIG. 4A;
FIG. 5 is an equivalent circuit diagram illustrating an SEAM cell to which embodiments of the present invention are applied;
FIGS. 6A, 7A and 8A are plan views for explaining a method for manufacturing a first embodiment of the SRAM cell according to the present invention;
FIGS. 6B and 6C are cross-sectional views of the transfer transistor and the drive transistor of FIGS. 6A;
FIG. 7B is a cross-sectional view of the transfer transistor and the drive transistor of FIG. 7A;
FIGS. 8B and 8C are cross-sectional views of the transfer transistor and the drive transistor of FIG. 8A;,
FIG. 9A is a plan view for explaining a method for manufacturing a second embodiment of the SRAM cell according to the present invention; and
FIG. 9B is a cross-sectional view of the transfer transistor and the drive transistor of FIG. 9A.
Description of the Preferred Embodiments
Before presenting the description of the preferred embodiments of the present invention a prior art SRAM cell will be explained with reference to FIGS. 1, 2A, 2B, 2C, 3A, 3B, 4A, 4B and 4C.
In FIG. 1, which is an equivalent circuit diagram illustrating the prior art SRAM cell, one SRAM cell is provided at each intersection between a word line WL.sub.1 and two complementary data lines DL.sub.1 and DL.sub.2. This memory cell is constructed by a flip-flop formed by two cross-coupled inverters and transfer N-channel MOS transistors Q.sub.t.spsb.1 and Q.sub.t.spsb.2 connected between nodes N.sub.1 and N.sub.2 of the flip-flop and the data lines DL.sub.1 and DL.sub.2.
The transfer transistors Q.sub.t.spsb.1 and Q.sub.t.spsb.2 are controlled by the voltage at the word line WL.sub.1.
Each of the inverters includes a load resistor R.sub.1 (R.sub.2) and a drive N-channel MOS transistor Q.sub.d.spsb.1 (Q.sub.d.spsb.2) between a high power supply line V.sub.DD and a low power supply (ground) line V.sub.SS. Node N.sub.1 is connected to a gate of the drive transistor Q.sub.d.spsb.2, so that the drive transistor Q.sub.d.spsb.2 is driven by the voltage at node N.sub.1. Also, node N.sub.2 is connected to a gate of the drive transistor Q.sub.d.spsb.1, so that the drive transistor Q.sub.d.spsb.1 is driven by the voltage at node N.sub.2.
Generally, transistors Q.sub.t.spsb.1, Q.sub.t.spsb.2, Q.sub.d.spsb.1 and Q.sub.d.spsb.2 are formed on a principal surface of a semiconductor substrate, and the load resistors R.sub.1 and R.sub.2 are made of polycrystalline silicon or semi-insulated polycrystalline silicon (SIPOS).
As SRAM cells become more refined, load resistors R.sub.1 and R.sub.2 have to be more highly stable.
The structure of the SRAM cell of FIG. 1 is explained next with reference to FIGS. 2A, 2B, 2C, 3A, 3B, 4A, 4B and 4C which show manufacturing steps thereof. Note that FIGS. 2A, 3A and 4A are plan views of four-bit SRAM cells; FIGS. 2B and 2C are cross-sectional views of the transfer transistor Q.sub.t.spsb.2 and the drive transistor Q.sub.d.spsb.1 of FIG. 2A; FIG. 3B is a cross-sectional view of the transfer transistor Q.sub.t.spsb.2 and the drive transistor Q.sub.d.spsb.1 of FIG. 3A; and FIGS. 4B and 4C are cross-sectional views of the transfer transistor Q.sub.t.spsb.2 and the drive transistor Q.sub.d.spsb.1 of FIG. 4A.
First, referring to FIGS. 2A and 2B, a p.sup.- -type monocrystalline silicon substrate 1 is thermally oxidized to form a field silicon oxide layer 2 by using a local oxidation of silicon (LOCOS) process. Thereafter, a gate silicon oxide layer 3 is formed by thermally oxidizing the substrate 1. Then, a gate electrode 4, including a polycrystalline silicon layer 41 and a tungsten layer 42, is formed on the gate silicon oxide layer 3 and the field silicon oxide layer 2. Then, phosphorous ions are implanted into the substrate 1 using the gate electrode 4 as a mask to form N.sup.- -type impurity diffusion regions 5 of a lightly-doped drain (LDD) configuration.
Next, referring to FIGS. 2A and 2C, a silicon oxide layer is formed on the entire surface, and an isotropic etching operation is performed upon the silicon oxide layer to form sidewall silicon oxide layers 6. Then, arsenic ions are implanted into the substrate 1 using the sidewall silicon oxide layers 6 as a mask to form N.sup.+ -type impurity diffusion regions 7 of the LDD configurations Then, a silicon oxide layer 8 is formed on the entire surface by using a chemical vapor deposition (CVD) process.
In FIG. 2A, only word lines such as WL.sub.1 and conductive layers such as G.sub.1 and G.sub.2 formed by the gate electrode 4, and the N-type impurity diffusion regions 5 and 7 of FIGS. 2B and 2C are illustrated; the other portions are omitted. Note that word line WL.sub.1 serves as gate electrodes of transfer transistors Q.sub.t.spsb.1 and Q.sub.t.spsb.2, conductive layer G.sub.1 serves as a gate of drive transistor Q.sub.d.spsb.1, and conductive layer G.sub.2 serves as a gate of drive transistor Q.sub.d.spsb.2.
Next, referring to FIGS. 3A and 3B, a tungsten layer 9 is formed and is patterned to form high power supply line V.sub.DD and low power supply line V.sub.SS. In this case, low power supply line V.sub.SS is connected via contact holes CONT1 to sources (the N.sup.+ -type impurity regions 7) of drive transistors Q.sub.d.spsb.1 and Q.sub.d.spsb.2. Then, a silicon oxide layer 10 is formed on the entire surface by using a CVD process.
Next, referring to FIGS. 4A and 4B, contact holes CONT2, CONT3 and CONT4 are perforated in the silicon oxide layer 10 and the like. Then, an SIPOS layer 11 is formed and is patterned. As a result, at node N.sub.1 i.e., contact hole CONT2, the SIPOS layer 11 is connected to the gate of the drive transistor Q.sub.d.spsb.2 and the source of transfer transistor Q.sub.t.spsb.1. Also, at the node N.sub.2 i.e., the contact hole CONT3R the SIPOS layer 11 is connected to the gate of the drive transistor Q.sub.d.spsb.1 and the source of the transfer transistor Q.sub.t.spsb.2. Further, at contact hole CONT4, the SIPOS layer 11 is connected to the high power supply line V.sub.DD. Thus, the SIPOS layer 11 serves as the load resistors R.sub.1 and R.sub.2.
Finally, referring to FIGS. 4A and 4C, a silicon oxide layer 13 is formed on the entire surface, and is flattened. Then, contact holes CONT5 and CONT6 are perforated in the silicon oxide layer 13 and the like. Then, an aluminum layer 14 is formed and is patterned to form the data lines DL.sub.1 and DL.sub.2. In this case, data line DL.sub.1 is connected via contact hole CONT5 to the drain of the transfer transistor Q.sub.t.spsb.1, and the data line DL.sub.2 is connected via contact hole CONT6 to the drain of the transfer transistor Q.sub.t.spsb.2.
Regarding the above-described prior art SRAM cell, reference is made to JP-A-63-29573, JP-A-1-227469 and JP-A-4-17366.
In the above-described prior art SRAM cell, however, load resistor R.sub.1 is not equivalent to load resistor R.sub.2. That is, as illustrated in FIG. 4A, there is a large difference in length between load resistor R.sub.1 (from CONT2 to CONT4) and the load resistor R.sub.2 (from CONT3 to CONT4). For example, load resistor R.sub.1 is longer, by about 10 percent, than load resistor R.sub.2. As a result, the loads of the inverters of the flip-flop are unbalanced, which deteriorates data retention characteristics, soft error resistance (SER) characteristics and the like.
Note that reduction size of the memory cells decreases capacitance of the nodes, which thereby deteriorates soft error resistance characteristics. In the resistance load type SRAM cell, it is possible to improve soft error resistance characteristics by reducing resistance values of the loads; in this case, resistance values of the loads are greatly unbalanced as stated above, so that soft error resistance characteristics can be improved only to some extent.
In FIG. 5, which is an equivalent circuit diagram illustrating a SRAM cell to which embodiments of the present invention are applied, a word line WL.sub.2 is added to the elements of FIG. 1. That is, the gate of the transfer transistor Q.sub.t.spsb.1 is controlled by the voltage at word line WL.sub.1, and the gate of the transfer transistor Q.sub.t.spsb.2 is controlled by the voltage at word line WL.sub.2. In this case, note that the voltage at word line WL.sub.1 is same as that at the word line WL.sub.2. Also, two high power supply lines V.sub.DD.spsb.1 and V.sub.DD.spsb.2 are provided instead of the high power supply line V.sub.DD of FIG. 1. The high power supply lines V.sub.DD.spsb.1 and V.sub.DD.spsb.2 are connected to load resistors R.sub.1 and R.sub.2, respectively. In this case, note that voltage at the high power supply line V.sub.DD.spsb.1 is the same as that at high power supply line V.sub.DD.spsb.2.
A first embodiment of the present invention is explained next with reference to FIGS. 6A, 6B, 6C, 7A, 7B, 8A and 8B which show manufacturing steps thereof. Note that FIGS. 6A, 7A and 8A are plan views of four-bit SRAM cells; FIGS. 6B and 6C are cross-sectional views of the transfer transistor Q.sub.t.spsb.2 and the drive transistor Q.sub.d.spsb.1 of FIG. 6A; FIG. 7B is a cross-sectional view of the transfer transistor Q.sub.t.spsb.2 and drive transistor Q.sub.d.spsb.1 of FIG. 7A; and FIGS. 8B and 8C are cross-sectional views of the transfer transistor Q.sub.t.spsb.2 and drive transistor Q.sub.d.spsb.1 of FIG. 8A.
First, referring to FIG. 6A and 6B, in a similar way to that shown in FIGS. 2A and 2B, a p.sup.- -type monocrystalline silicon substrate 1 is thermally oxidized to form LOCOS a field silicon oxide layer 2 by using a LOCOS process. Thereafter, a gate silicon oxide layer 3 is formed by thermally oxidizing the substrate 1. Then, a gate electrode 4, including an about 100 nm thick polycrystalline silicon layer 41 and an about 100 nm thick tungsten layer 42, is formed on the gate silicon oxide layer 3 and the field silicon oxide layer 2. Then, phosphorous ions are implanted into the substrate 1 using the gate electrode 4 as a mask to form N.sup.- -type impurity diffusion regions 5 of an LDD configuration.
Next, referring to FIG. 6A and 6C, in the same way as shown in FIGS. 2A and 2C, a silicon oxide layer is formed on the entire surface, and an isotropic etching operation is performed upon the silicon oxide layer to form sidewall silicon oxide layers 6. Then, arsenic ions are implanted into the substrate 1 using the sidewall silicon oxide layers 6 as a mask to form N.sup.+ -type impurity diffusion regions 7 of the LDD configuration. Then, a silicon oxide layer 8 is formed on the entire surface by using a CVD process.
In FIG. 6A, only word lines such as WL.sub.1 and WL.sub.2 and conductive layers such as G.sub.1 ' and G.sub.2 ' formed by the gate electrode 4, and the N-type impurity diffusion regions 5 and 7 of FIGS. 6B and 6C are illustrated; the other portions are omitted. Note that word lines WL.sub.1 and WL.sub.2 serve as gate electrodes of the transfer transistors Q.sub.t.spsb.1 and Q.sub.t.spsb.2, respectively. Also, conductive layer G.sub.1 ' serves as a gate of the drive transistor Q.sub.d.spsb.1, and conductive layer G.sub.2 ' serves as a gate of the drive transistor Q.sub.d.spsb.2.
In FIG. 6A, the N-type impurity diffusion regions 5 and 7, word lines WL.sub.1 and WL.sub.2, and conductive layers G.sub.1 ' and G.sub.2 ' are symmetrical with respect to a center location thereof as indicated by Z.
Next, referring to FIGS. 7A and 7B, in a similar way to that shown in FIGS. 3A and 3B, a tungsten layer 9 is formed and is patterned to form the high power supply lines V.sub.DD.spsb.1 and V.sub.DD.spsb.2 and the low power supply line V.sub.SS. In this case, the low power supply line V.sub.SS is connected via contact holes CONT1 to sources (N.sup.+ -type impurity regions 7) of the drive transistors Q.sub.d.spsb.1 and Q.sub.d.spsb.2. Then, a silicon oxide layer 10 is formed on the entire surface by using a CVD process.
In FIG. 7A, the high power supply lines V.sub.DD.spsb.1 and V.sub.DD.spsb.2 and the low power supply line V.sub.SS are symmetrical with respect to the center location thereof as indicated by Z.
Next, referring to FIGS. 6A and 8B, in a similar way to that shown in FIGS. 4A and 4B, contact holes CONT2, CONT3, CONT4-1 and CONT4-2 are perforated in the silicon oxide layer 10 and the like. Then, a SIPOS layer 11 is formed and is patterned. As a result, at node N.sub.1 i.e., contact hole CONT2, SIPOS layer 11 is connected to gate of drive transistor Q.sub.d.spsb.2 and the source of transfer transistor Q.sub.t.spsb.1. Also, at node N.sub.2, i.e., the contact hole CONT3, the SIPOS layer 11 is connected to the gate of the drive transistor Q.sub.d.spsb.1 and the source of the transfer transistor Q.sub.t.spsb.2. Further, SIPOS layer 11 is connected to the high power supply line V.sub.DD.spsb.1 at the contact hole CONT4-1, and SIPOS layer 11 is connected to the high power supply line V.sub.DD.spsb.2 at contact hole CONT4-2. Thus, SIPOS layer 11 serves as load resistors R.sub.1 and R.sub.2.
Finally, referring to FIGS. 8A and 8C, in a similar way to that shown in FIGS. 4A and 4C, a silicon oxide layer 13 is formed on the entire surface, and is flattened. Then, contact holes CONT5 and CONT6 are perforated in the silicon oxide layer 13 and the like. Then, an aluminum layer 14 is formed and is patterned to form data lines DL.sub.1 and DL.sub.2. In this case, data line DL.sub.1 is connected via contact hole CONT5 to the drain of the transfer transistor Q.sub.t.spsb.1, and data line DL2 is connected via contact hole CONT6 to the drain of the transfer transistor Q.sub.t.spsb.2.
In FIG. 8A, load resistors R.sub.1 and R.sub.2 are symmetrical with respect to the center location thereof as indicated by Z.
In the first embodiment, since the high power supply lines V.sub.DD.spsb.1 and V.sub.DD.spsb.2 are provided for load resistors R.sub.1 and R.sub.2, respectively, the resistance values of load resistors R.sub.1 and R.sub.2 can be easily adjusted. Therefore, the load resistors R.sub.1 and R.sub.2 maybe so balanced that there maybe substantially no difference in resistance between them.
A second embodiment of the present invention is explained next with reference to FIGS. 9A and 9B which correspond to FIGS. 7A and 7B, respectively. In FIGS. 9A and 9B, contact holes CONT7 and CONT8 are perforated in silicon oxide layer 8 and the like, and a SIPOS layer 11' is formed only within the contact holes CONT7 and CONT8. In this case, tungsten layer 9(V.sub.DD.spsb.1) covers the contact hole CONT7 and is in direct contact with SIPOS layer 11' within the contact hole CONT7. Also, tungsten layer 9 (V.sub.DD.spsb.2) covers contact hole CONT8 and is in direct contact with SIPOS layer 11' within contact hole CONT8. Thus, SIPOS layer 11' serves as load resistors R.sub.1 and R.sub.2.
In the second embodiment, since resistance values of load resistors R.sub.1 and R.sub.2 are determined by the sizes of the contact holes CONT7 and CONT8, resistance values of load resistors R.sub.1 and R.sub.2 can be easily adjusted. Therefore, load resistors R.sub.1 and R.sub.2 maybe so balanced that there maybe substantially no difference in resistance between them.
As explained hereinbefore, according to the present invention, since the imbalance of the load resistors of a SRAM cell can be substantially eliminated, data retention and soft error resistance characteristics can be improved.
Claims
I claim:
1. A static memory cell formed in cell region, said static memory cell comprising: a first power supply line for a first power voltage; a second power supply line for said first power voltage; a third power supply line for a second power voltage; a first load resistor connected between said first power supply line and a first node; a second load resistor connected between said second power supply line and a second node; a first drive transistor connected between said first node and said third power supply line and having a gate connected to said second node; a second drive transistor connected between said second node and said third power supply line and having a gate connected to said first node; a first transfer transistor connected between said first node and a third node and having a gate connected to a first word line; and a second transfer transistor connected between said second node and a fourth node and having a gate connected to a second word line, said first and second word lines being at the same voltage level, said third power supply line crossing over said cell region to divide said cell region into a first area on a first side of said third power supply line and a second area on a second side of said third power supply line, said first power supply line and said second word line being formed over said first area, said second power supply line and said first word line being formed over said second area; wherein said first and second power supply lines, respectively, and said third power supply line are symmetrically disposed with respect to a center of said cell region.
2. The device as set forth in claim 1, wherein said first and second load resistors, respectively, said first and second drive transistors, respectively, and said first and second transistors, respectively, are symmetrically disposed with respect to said center of said cell region.
3. The device as set forth in claim 1, wherein each of said first and second load resistors comprises a high resistance element filled in a contact hole area formed in said first and second nodes, respectively.