Method of Making EEPROM Cell With Improved Coupling Ratio

The present invention generally relates to electronic memory structures and, more particularly, to electrically erasable programmable read only memories (EEPROMs) formed at high integration density.

Electrically Programmable Read-Only Memories (EPROMs) and Electrically Erasable Programmable Read-Only Memories (EEPROMs) are well known in the art. More particularly, in recent years, EEPROMs, known as flash memories, have a provision for erasing and rewriting individual sections or partitions, independently, while stored data is maintained in other sections.

EEPROMs in general have many applications ranging from personalization of communications devices or storage of bar codes. Flash memories are touted as a possible replacement for system fixed disks, particularly in laptop, notebook or smaller personal computers.

FIG. 1 is a cross sectional representation through an array area of a prior art EEPROM cell. On the substrate 10, cells are identified by a floating gate 12 between two isolation diffusions 14. There is a gate oxide layer 16 between the substrate 10 and the floating gates 12. The floating gates 12 are isolated from each other by thick oxide 18. A composite silicon Oxide-silicon Nitride-silicon Oxide (ONO) dielectric layer 20 separates the floating gates 12 from an overlying control gate 22.

Data is stored in EEPROM cells in a manner that is similar to a Dynamic Random Access Memory (DRAM), i.e., storing a charge on (or discharging) an isolated node. In a DRAM cell, the isolated node is a capacitor plate. In an EEPROM cell, the isolated node is a floating gate 12, which is an electrically isolated (floating) gate of a Field Effect Transistor (FET). Carriers, electrons or holes, are injected onto the floating gate 12 through gate oxide 16 or an insulating layer 20. These carriers effectively shift the FET's threshold voltage (V.sub.T) by some voltage, .delta., to V.sub.T.delta. =V.sub.T +.delta..

The control gate 22, passing over, or under, some part of the floating gate 12, is capacitively coupled to the floating gate 12. The control gate 22 voltage (V.sub.CX) is divided between the control gate 22 to floating gate 12 capacitance C.sub.CF and the floating gate 12 to channel capacitance C.sub.FX and V.sub.CX .dbd.V.sub.CF +V.sub.FX. When the control gate 22 is driven high, the floating gate is pulled high through the capacitive coupling.

In order to read correctly, V.sub.CX must be high enough that V.sub.T <V.sub.FX <V.sub.T.delta.. Thus, when the control gate is driven high, i.e., the cell is selected, in an unprogrammed (or erased) cell, V.sub.FX >V.sub.T, and the floating gate FET turns on; in a programmed cell, V.sub.FX <V.sub.T +.delta., and the floating gate FET remains off. Ideally, during a read V.sub.FX .dbd.V.sub.CX and during a write V.sub.CF .dbd.V.sub.CX. However, practically, neither of these conditions is possible.

Writing the cell of FIG. 1, i.e., causing charge movement into the floating gate 12, is achieved by increasing voltage on the control gate 22 above the read voltage. Writing requires a minimum Write voltage V.sub.W across the injection oxide, C.sub.CF. Thus, the minimum for V.sub.CX to develop V.sub.CF.dbd.V.sub.W depends, in large part, on the capacitive coupling ratio (or, simply, "coupling ratio" ) of C.sub.CF and C.sub.FX. In the prior art cell of FIG. 1, C.sub.FX includes a significant overlap capacitance where the floating gate 12 overlaps diffusions 14, both in the thick oxide isolation regions 18 and in the thinner oxide regions immediately adjacent channels. The larger C.sub.FX, the higher V.sub.CX must be in order to write, or C.sub.CF must be increased to maintain the coupling ratio. Further, the higher the coupling ratios, the easier it is to write.

Typically, EEPROM cells are designed to prevent inadvertent writing or erasure during a normal read. So, by design, during a read, V.sub.CF is always less than V.sub.W and, is as close to zero as possible. Consequently, during a write, V.sub.CX is normally boosted to a much higher voltage than during a read to raise V.sub.CF above V.sub.W. However, how much V.sub.CX may be boosted is limited by technology. Geometric factors limit C.sub.CF and, therefore, V.sub.CF. One such factor limiting C.sub.CF is cell area, which is a primary concern for a stacked type of EEPROM cell. Another factor limiting C.sub.CF is the capacitor area, i.e., the area between the intersection of the control gate 22 and the floating gate 12. Because of these limitations, C.sub.CF is normally much smaller than desired. Since C.sub.CF is directly proportional to area, increasing capacitor area increases C.sub.CF. However, increasing capacitor area increases cell size, which is contrary to the objective of increasing the number of EEPROM cells per unit area, i.e., increasing chip density. ways are needed to increase C.sub.CF without increasing cell size.

It is a purpose of the invention to increase the control gate to floating gate coupling ratio in an EEPROM cell.

It is another purpose of the present invention to increase EEPROM cell density.

It is yet another purpose of the present invention to improve EEPROM cell density while increasing the cell control gate to floating gate coupling ratio.

The present invention is a method of forming EEPROM cells. The method includes forming a tunnel oxide layer on a wafer and forming floating gates on the tunnel oxide layer with the floating gate having sidewalls. Isolation regions may be formed adjacent the sidewalls. Then, a conformal layer of dielectric is formed on the floating gate and sidewalls. The conformal dielectric may be ONO deposited using Chemical Vapor Deposition. Next, a selective etch material layer is deposited on the wafer over the conformal dielectric layer. A polish stop layer is deposited on the wafer over the selective etch material layer to define an upper polishing surface above the floating gate. The polish stop layer and the selective etch material layer are selectively removed to re-expose the conformal dielectric layer along the floating gates and sidewalls. The exposed polish stop layer and underlying etch material are removed by first depositing an oxide layer on the polish stop layer and then polishing the deposited layer coplanar with the polish stop layer such that the exposed polish stop layer is an upper polishing surface above the floating gates. Exposed portions of the polish stop layer are removed to expose the selective etch layer above the floating gates and above sidewall regions adjacent the sidewalls. Then, the exposed selective etch layer is removed, exposing the conformal dielectric layer. Finally, a control gate is formed over the conformal dielectric layer. The control gate may be formed by depositing a control gate layer above the floating gate and within the sidewall region and patterning the control gate layer. The patterned control gates extend over the floating gate and along the floating gate sidewalls. The area of the floating gate-control gate capacitor includes the area of the sidewalls.

FIG. 1 is a cross sectional representation of a prior art EEPROM cell.

FIGS. 2A-2E represent the steps in forming an EEPROM cell according to the preferred embodiment of the present invention.

FIGS. 2A-E are cross sectional representations of a preferred EEPROM cell through the steps of forming the EEPROM cell. The preferred EEPROM cell has improved floating gate coupling capacitance. The cross section is taken in a direction perpendicular to cell current flow, i.e., perpendicular to the floating gate FET's channel and between its source and drain.

First, in preparation of a wafer, in FIG. 2A, a thin, 70 .ANG. tunnel oxide layer 10r is formed on the surface 102 of a silicon wafer. A layer of n.sup.+ doped polysilicon is deposited on the tunnel oxide layer 10r using Chemical Vapor Deposition (CVD). Floating gates 100 are formed from the polysilicon layer using a suitable photolithographic process such as are known in the art. Isolation regions 108 are formed adjacent to floating gates 100 by a p isolation implant. After the isolation implant, the floating gate photo resist pattern is removed from the polysilicon. A tunnel oxide layer 110, which is a conventional conformal ONO layer 110, is formed on the wafer covering the floating gates 100 and regions therebetween 106. The effective thickness of the conformal ONO layer is, preferably, 150 .ANG..

Next, in FIG. 2B, a layer 112 of selective etch material is deposited on ONO layer 110. Preferably, the selective etch material is 1500 .ANG. thick and is boron nitride or aluminum oxide. The selective etch layer 112 is capped with a polish stop layer 114. Preferably, the polish stop layer 114 is a 1000 .ANG. thick layer of Silicon Nitride. A layer of oxide is formed on the polish stop layer 114. Preferably, Chemical Vapor Deposition (CVD) is used to form the oxide layer 106.

In FIG. 2C, the CVD oxide layer 106 is polished, using a typical Chemical-Mechanical Polishing (CMP) process, until the polish stop layer 114 (which forms an upper polishing surface over the floating gates 100 in areas 120) is removed. Thus, pockets of CVD oxide 118 remain only between floating gates 100 or in areas where there are no floating gates 100, i.e., outside of the array.

In FIG. 2D, the exposed polish stop layer 114 in areas 120 is removed by a wet or dry etch to expose the etch selective material therebeneath. Then, the exposed selective etch material is removed in areas 120 to expose ONO layer 110 on floating gates 100 and, in areas 122, along the floating gates' sidewalls 124.

Finally in FIG. 2E, a layer 126 of n.sup.+ doped poly is deposited using a well known CVD process. The deposited poly layer 126 is patterned, photolithographically, and etched to form control gates. After control gates 126 are patterned, n.sup.+ regions are implanted to form sources and drains of the cells (not shown on the drawing) on either side of the control gates 126. As noted above, the cross section of FIGS. 2A-2E is taken through the cell, perpendicular to the direction of READ current flow. Thus, the source to drain (READ) current flow is perpendicular to control gates 126. Having thus completed the EEPROM cells according to the present invention, the EEPROM chip structure is completed using manufacturing steps well known in the art for such a structure.

Thus preferred EEPROM cells formed according to the steps of the present invention have a control gate to floating gate coupling ratio of at least 0.55 for a 0.3 .mu.m thick floating gate 100. The control gate (layer 126) contacts the floating gate dielectric (ONO layer 110) vertically along the gate's sidewalls 124 as well as horizontally over the gate 100. Therefore, the EEPROM cell of the present invention has an increased coupling ratio without a corresponding decrease in cell density.

While the present invention is described in terms of preferred embodiments, it is understood that numerous variations and modifications will occur to a person skilled in the art without departing in spirit from the claimed invention. It is intended that the scope of the claims include those modifications and variations that fall within the spirit of the invention.