Digital Signal Processor Architecture

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1. Field of the Invention

The invention relates to digital signal processor architectures and, more particularly, to cyclical machines for performing digital signal processor functions.

2. Description of Related Art

In a typical digital signal processing system, a varying analog signal is sampled at some periodic rate and converted to a digital value. The sequence of digital values is then processed according to a signal processing algorithm which may represent, for example, a low-pass filter, a high-pass filter, a band-pass filter, or any of a number of other functions. Typically the calculations to be performed are the same for each sample in the input sequence. The result is another sequence of digital values which can then be reconverted to analog form.

The signal processing algorithm may be performed "off-line" meaning the input sequence of values is stored, the processing takes place on all of the input values, and the resulting values are then reconverted to analog form. Off-line digital signal processing is useful if the processing hardware is slow and/or a large number of calculations need to take place. It cannot be used for real time applications, however, in which the output is expected substantially simultaneously, or at least in a pipelined manner, with the input. It also cannot be used if the input stream will be continuous and there is not enough memory to store all the input values while the processing takes place.

Real time digital signal processing requires fast, powerful hardware to perform the number of calculations required between each sample of the input signal. For many algorithms the calculations involve repetitions of a multiply-and-add-to-accumulator function. The number of these calculations that can be performed by the hardware between "cycles" (input samples) directly limits the signal processing work which can be accomplished by the device. For example, if it is desired that the device perform a multi-pole low-pass filtering function, the number of multiply-add calculations that the device can perform per sample sets a hard limit on the number of poles which the filter can have. Viewed another way, the higher the desired filtering quality, the lower the sampling frequency will have to be in order to permit the required number of calculations between cycles. A lower sampling frequency reduces the maximum frequency component which the system can handle in the analog input signal without causing aliasing.

In compact disc (CD) audio applications, input data samples always arrive at a fixed standard rate such as 4:4.1 kHz for a stereo pair. In some systems and for some purposes, the fixed rate is 176.4 KHz. Live CD signals must be processed in real time. The performance of a given hardware architecture with respect to these signals, therefore, can be measured by the number of calculations which the hardware can perform between samples occurring at a constant, predefined sampling frequency.

In order to maximize performance, many digital signal processors use a pipelined architecture and/or incorporate extensive auxiliary hardware. Additional hardware is expensive, however, and could not be readily used in lower-priced consumer directed equipment. In the consumer market, the key is to identify and include only those hardware features which yield a performance improvement worth more than the costs required to implement them.

Accordingly, it is an object of the present invention to provide a digital signal processing architecture which overcomes some or all of the above disadvantages.

It is another object of the present invention to provide a digital signal processing architecture which is optimized for audio or fixed-input-sample-frequency applications.

According to the invention, roughly speaking, a digital signal processing architecture is provided which is inherently cyclical in nature. A timer is provided which can be programmed to reset the processor and return to the first instruction periodically, typically once each sample of the input stream.

In another aspect of the invention, pipeline operation is enhanced through the use of a double buffering system in which operands are latched into the first stage of a double buffer as soon as they are ready, but they are transferred to the second stage only when the last-ready operand is available and the computation unit is ready to receive the operands. The computation unit receives the operands in the second stage of the buffers.

In another aspect of the invention, a processor communicates with an external unit via a random access memory and a plurality of FIFOs. Each FIFO is associated with a respective location in the random access memory. Whenever the processor retrieves a value from one of these locations in the random access memory, control means automatically refills that location from the corresponding FIFO. Similarly, whenever the processor writes data to one of the locations corresponding to an output FIFO, control means automatically recognizes that and copies the data into the corresponding output FIFO. Output FIFO writes may be emulated by an address latch and a data latch in a path to the FIFOs.

In another aspect of the invention, a processor is provided for which certain operands can include a "write-back" bit, which causes the result of an operation automatically to be written back to a corresponding one of the operands.

In another aspect of the invention, a novel register addressing mode is supported in a processor.

In another aspect of the invention, a processor is provided in which an instruction following a branch instruction in memory may mandate another branch from the target instruction stream after a predetermined number of instructions.

In another aspect of the invention, apparatus is provided for moving data in response to one instruction, without affecting the progress of a computation which is taking place simultaneously in response to another instruction.

In another aspect of the invention, an operand mask register is provided which permits doing many instructions using one re-used constant.

The invention will be described with respect to particular embodiments thereof, and reference will be made to the drawings, in which:

FIG. 1 is a simplified block diagram of digital signal processing apparatus according to the invention;

FIG. 2 is a block diagram of the instruction/operand fetch subsystem shown in FIG. 1;

FIG. 3 is a block diagram of the buffer/computation subsystem as shown in FIG. 1;

FIG. 4 is a block diagram of one of the double buffers shown in FIG. 3;

FIG. 5 is a block diagram of the RAM/IO subsystem shown in FIG. 1;

FIG. 6 is a symbolic diagram of the control unit shown in FIG. 1;

FIG. 7 illustrates the instruction and operand formats for the processor of FIG. 1;

FIG. 8 illustrates the instruction pipeline of the processor of FIG. 1;

FIG. 9 is a block diagram of the register logic shown in FIG. 2; and FIG. 10 defines the operation of twiddle logic of FIG. 9.

FIG. 1 is a simplified block diagram of computer system which may incorporate the present invention. It includes, among other things, a digital signal processor (DSP) 10, and a dual port program memory unit 12. The DSP 10 is provided together with the program memory 12 on a single chip and may be designed as a single unit. Instructions are provided in 16-bit words from the read port of program memory 12 to the processor 10 over an NBUS bus 14, from program memory addresses specified by the processor 10 over a 10-bit PC bus 16. The system may include other elements as well, for example, a host CPU for writing digital signal processor program instructions into program memory 12, and for occasionally providing or reading parameters of a program running in the DSP 10. When an external source such as a microprocessor writes program instructions to program memory 12, it does so via the write port address lines NADDR›9:0! and data lines NDATA›15:0!.

The digital signal processor 10 includes three main subsystems: an instruction/operand fetch subsystem 20, a buffer/computation subsystem 22, and a RAM/IO subsystem 24. The instruction/operand fetch subsystem 20 generally performs instruction sequencing, branching, immediate justification and register address decoding. The buffer/computation subsystem generally performs operand synchronization functions, and arithmetic and logic functions on the incoming data stream. The RAM/IO subsystem generally performs scratch pad memory functions for the buffer/computation subsystem 22, as well as data stream input and output functions. The three main subsystems of digital signal processor 10 are controlled by a control unit 26.

Only certain major bus connections between the three main subsystems are shown in FIG. 1, and they include a 16-bit operand (OP) bus 134 from the instruction/operand fetch subsystem 20 to the buffer/computation subsystem 22, a 13-bit instruction register NRC bus from the instruction/operand fetch subsystem 20 to the buffer/computation subsystem 22, a 10-bit accumulator ACC bus from the buffer/computation subsystem 22 to the instruction/operand fetch subsystem 20, a 10-bit read address RDADDR bus from the instruction/operand fetch subsystem 20 to the RAM/IO subsystem 24, a 16-bit write data WRDATA bus from the buffer/computation subsystem 22 to RAM/IO subsystem 24, and a 16-bit read data RDDATA bus from the RAM/IO subsystem 24 to the instruction operand fetch subsystem 20. The RAM/IO subsystem 24 additionally communicates externally to the processor 10 over lines 28.

FIG. 2 is a block diagram of the instruction/operand subsystem 20 of FIG. 1. As shown in FIG. 2, the 16-bit NBUS bus 14 from program memory 12 is connected to the input of a 16-bit NRC register 110, the output of which forms a 16-bit NRC bus 112. The low-order 10 bits NRC bus 112, NRC(9:0), are connected to a first input port of a 3-input, 10-bit wide multiplexer 114, the 10-bit output of which is connected the input of a PC register 116. The PC register 116 has a PC increment input connected to receive a PCI signal 118, and generates a 10-bit output which forms the PC bus 16. In addition to being connected to the program memory unit 12 (FIG. 1), the PC bus is also connected to the input of 10-bit SUBR register 120, the 10-bit output of which is connected to a third one of the input ports of multiplexer 114. The second input port of multiplexer 114 is connected to receive ACC(13:4) from the buffer/computation subsystem 22. Both PC register 116 and NRC register 110 are readable directly by an external CPU by means not shown.

The low-order 10 bits NRC(9:0) of NRC bus 16 are also connected to a first input port of a 3-input, 10-bit wide, multiplexer 122, the output of which forms the 10-bit RDADDR bus 124. Three 4-bit fields of NRC bus 112 are also provided to respective first, second and third input ports of a 3-input, 4-bit wide multiplexer 126. The three fields are NRC(13:10), NRC(8:5) and NRC(3:0). The 4-bit output of multiplexer 126 is provided as an input to register logic 128, which provides a 10-bit output to a second input port of multiplexer 122. The details of register logic 128 are explained hereinafter.

The low-order 13 bits of NRC bus 112 are also connected to an input port of immediate justification logic unit 130, which provides a 16-bit output to a first input port of a 2-input, 16-bit wide multiplexer 332. Bit NRC(13) of the NRC bus 112 is also provided as a control input to immediate justification logic 130. The second input port of multiplexer 132 is connected to receive the RDDATA bus from RAM/IO subsystem 24 (FIG. 1), and the 16-bit output of multiplexer 132 is provided to the buffer/computation subsystem 22 (FIG. 1) over the OP bus 134. The low-order 10 bits of RDDATA are also provided as an input to an indirect register 136, the 10-bit output of which is connected to the third input of multiplexer 122.

The low-order 5 bits of NRC bus 112 are also provided to an OP.sub.-- MASK register 138, the purpose for which is described below. Similarly, the low-order 6 bits are provided to an RBASE register 140, and the low-order 3 bits are provided to an RMAP register 142, both of which are described below.

FIG. 3 is a block diagram of the buffer/computation subsystem 22 (FIG. 1). As shown in FIG. 3, the 16-bit operand bus 134 from the instruction/operand fetch subsystem 20 is provided as a 16-bit input to an M2 double buffer 210. A double buffer, also referred to herein as a double latch, is a two-stage register in which input values are usually loaded into the first stage only, upon receipt of a clock signal while an enable signal from control unit 26 is asserted. Registers in the DSP 10 always receive a clock signal, but are enabled for latching only when an enable signal for the register stands asserted when a clock pulse arrives. The output of the first stage of a double latch is connected to the input of the second stage of the double latch, the output of which is connected to one of the input ports of the computation engine in buffer/computation subsystem 22. As will be seen, the control unit 26 loads values into the first stage of all the appropriate double latches in the buffer/computation subsystem 22 and, only when the last value is ready and the computation engine is also ready, are the values transferred to the second stage of all of the double latches. If the computation engine is ready when the last value is to be loaded into one of the double latches, the control logic loads the last value directly into the second stage of the double latch, bypassing the first stage. This saves operand load time.

FIG. 4 is a detail of the double latch 210 of FIG. 3. As can be seen, it includes a 16-bit register 212 and a 16-bit register 214. Each is a master/slave register, but other types of registers, or carefully controlled transparent latches, may be used instead. The 16-bit operand bus OP(15:0) is provided as a data input to the first-stage register 212, the 16-bit output of which is connected to one input port of a multiplexer 213. The other input port of multiplexer 213 is connected to receive OP(15:0) directly, and the output is connected to the data input of register 214. The 16-bit output of register 214 is provided as the output value 216 of the double latch 210. Each of the registers 212 and 214 also has a respective clock enable input 218 and 220, driven by control unit 26 (FIG. 1).

Returning to FIG. 3, in addition to being connected as an input value to M2 double buffer 210, the operand bus OP(15:0) 134 is also connected to provide input values to a 16-bit M1 double buffer 230, a 16-bit A1 double buffer 232, a 16-bit A2 double buffer 234, and a 16-bit MOVE register 236. The MOVE register 236 facilitates moves of data which do not require or affect the operation of the computation engine. The buffer/computation subsystem 22 also includes a 1-bit MSEL double buffer 238, the data input of which is connected to receive NRC(12) from the instruction/operand fetch subsystem 20. It also includes a 4-bit AMX double latch 240, the input of which is connected to receive NRC(11:8), and a 4-bit ASEL double latch 242, the input of which is connected to receive NRC(7:4). A 2-input, 1-bit wide multiplexer 244 is also provided, which receives OP(4) on its first input and NRC(7) on its second input. The output of multiplexer 244 is provided as an input value to a 1-bit BT double buffer 246. Similarly, a 2-input, 4-bit wide multiplexer 248 is connected to receive OP(3:0) at its first input port and NRC(3:0) at its second input port. The output of multiplexer 248 is connected to the data input of a 4-bit BSEL double latch 250.

The computation engine of buffer/computation subsystem 22 is basically constructed from a 16.times.16 bit multiplier 252, a 20-bit ALU 254, a status register 255, a 20-bit barrel shifter 256, and a 20-bit accumulator 258. These elements are connected to operate as a "fractional" or "rational math" machine, meaning all values are interpreted to be between -1 and 1 (including -1 but excluding 1). These individual elements are essentially conventional in design, and may, for example, be made up of macros defined in the custom integrated circuit design tools available from AT&T Microelectronics, Allentown, Pa., incorporated herein by reference. The computation engine is entirely combinational except for the status register 255 and the accumulator 258, but a particular computation may require one, two or more clock cycles ("ticks") to propagate through. Control unit 26 determines from the particular instruction being executed how many clock ticks to wait before clocking a result into status register 255 and accumulator 258.

In the computation engine, a 2-input, 16-bit wide multiplexer 260 is provided which has a `0` input port connected to receive the high-order 16 bits ACC(19:4) of the accumulator 258. The `1` input port of multiplexer 260 is connected to receive a 16-bit value made up of a carry bit C followed by 15 zeroes. C is generated by the ALU 254 on a previous computation and latched into the status register 255 as explained hereinafter. The select input for multiplexer 260 is connected to receive an ACSBU signal, the source of which is explained below. Basically, the ACSBU signal indicates that an add-carry (ADDC) or subtract-borrow (SUBB) instruction is being executed.

The 16-bit output of multiplexer 260 is connected to the `0` input port of a 2-input, 16-bit wide multiplexer 262, the `1` input port of which is connected to the second stage output of double latch 210. The select input of multiplexer 262 is connected to receive the second stage output of M2SEL double latch 238. The 16-bit output of multiplexer 262 is connected to one input port of multiplier 252. The other input port of multiplier 252 is connected to receive the second stage output of M1 double latch 230. Accordingly, whereas one input to the multiplier 252 is always an operand (M1), the other input is either another operand (M2), the accumulator value, or a carry bit, all selectably in response to M2SEL and ACSBU.

The result of a multiply in multiplier 252 is a 32-bit number including a replicated sign bit (in bits 31 and 30). Bit 31 is discarded and the remaining high order 20 bits, bits 30:11, form the 20-bit output of multiplier 252. The output of multiplier 252 is connected to the `3` input port of a dual multiplexer 264. The dual multiplexer 264 contains two independent 4-input, 20-bit wide multiplexers. The 4-bit select input to the dual multiplexer 264, which is connected to receive the second stage output of double latch 240, contains two bits which control the first multiplexer and two bits which control the second multiplexer. The `0` input port of dual multiplexer 264 is connected to receive the 20-bit ACC(19:0) value from accumulator 258, and the `1` input port is connected to receive the second stage output of A1 double latch 232. The `2` input port of dual multiplexer 264 is connected to receive the second stage output of A2 double latch 234. The A1 and A2 double latches 232 and 234 are each only 16 bits wide, and since the computation engine is a fractional machine, these are each extended to 20 bits by adding four low-order 0 bits before the dual multiplexer 264.

One of the 20-bit outputs of dual multiplexer 264 is connected to a 20-bit A input of the ALU 254. The other 20-bit output of dual multiplexer 264 is connected to the `0` input of a 2-input, 20-bit wide multiplexer 266, the `1` input of which is connected to receive a 20-bit value made up of all zeroes except for the carry bit C in bit 4. The multiplexer 266 allows 16-bit multiple precision math. The 20-bit output of multiplexer 266 is connected to the B input port of ALU 254, and the select input of multiplexer 266 is connected to receive the same ACSBU signal which is provided to the select input of multiplexer 260.

The ALU 254 has an 8-bit function select input which is provided by an FNX function translation unit 268. Four function bits are provided to FNX unit 268 from the second stage output of double latch 242, and translated by FNX unit 268 to the 8 bits required by ALU 254. FNX unit 268 also generates the ACSBU signal which controls multiplexers 260 and 266.

The ALU 254, after translation by FNX unit 268, supports 8 arithmetic and 8 logical operations. They are:

Operations ASEL =0000 and ASEL =1000 are handled identically by the ALU 254. Both are available since the high order bit of ASEL also specifies the type of shift, arithmetic or logical, which the barrel shifter 256 will perform. Note also that other operations might be supported in a different embodiment of the ALU, such as 16-bit increment and decrement operations.

The 20-bit output of ALU 254 is provided as an input to barrel shifter 256, the 20-bit output of which is connected to the input of accumulator 258. Barrel shifter 256 has a 4-bit N input to specify a shifting function, and a T input to specify whether the shift is to be arithmetic or logical. The T input is connected to receive the second stage output of BT double latch 246, and the N input is coupled to receive the second stage output of BSEL double latch 250. The functions performed by barrel shifter 256 are as follows:

For all BSELs except 1000, the shift type (arithmetic or logical) is determined by NRC(7), which is the same as the high order bit of ASEL. Basically, if the ALU function is arithmetic, so will the shift be arithmetic. If the ALU function is logical, so will the shift be logical. If BSEL=1000, then an operand is loaded which specifies both the shift type and a new BSEL explicitly. If the newly loaded operand is itself 1000, then the barrel shifter 256 performs a 1-bit left rotate of bits 19:4 with bit 19 being rotated into the carry bit.

The "clip on overflow" function of barrel shifter 256 essentially prevents the ALU 254 from exceeding the largest positive or negative number which can be represented in 20 bits. In this function, if the overflow (V) output of ALU 254 is set, the barrel shifter will output the largest positive number if the sign bit from the ALU 254 is negative, or the largest negative number if the sign bit from ALU 254 is positive. Clip on overflow is useful especially in digital filter applications.

As previously mentioned, the operand bus OP(15:0) is connected as an input to a 16-bit MOVE register 236. The output of the MOVE register 236 is connected to a first input port of a 2-input, 16-bit wide multiplexer 270. The second input port of multiplexer 270 is connected to receive the high-order 16 bits ACC(19:4) from accumulator 258, and the output of multiplexer 270 forms the WRDATA(15:0) bus provided to RAM/IO subsystem 24 (FIG. 1). Ten bits from accumulator 20, specifically ACC(13:4), are also provided to the instruction/operand fetch subsystem 20 as shown in FIG. 1.

FIG. 5 is a block diagram of RAM/IO subsystem 24 (FIG. 1). The major components of the RAM/IO subsystem 24 are an internal RAM (IRAM) 310, an external input RAM (EIRAM) 312, an external input FIFO (EIFIFO) 314, and an external output FIFO (EOFIFO) 316. The IRAM 310 and El-RAM 312 are each dual-ported, 16-bit wide register files, and are mapped into a 1 k word address space as follows:

Of these addresses, many do not actually contain memory and some are assigned special purposes. The special register locations are as follows:

Addresses 000h-0FFh are read only, as seen from outside the RAM/IO subsystem 24, and addresses 300h-3FFh are write only. Addresses 100h-2FFh are read/write, and may be accessed by the digital signal processor 10. Additionally, locations 100h-1FFh are equivalent to 200h-2FFh, and locations 000h-07Fh are equivalent to locations 080h-0FFh.

The semaphore words permit controlled communication between the DSP 10 and an external CPU. The semaphore data word can be either read or written by either the CPU or the DSP 10. The semaphore status word can only be read by either the CPU or the DSP 10. The semaphore status word contains four bits indicating respectively (1) that the CPU was the last to write to the semaphore data word, (2) that the DSP 10 was the last to write to the semaphore data word, (3) that the CPU has acknowledged the current data word, and (4) that the DSP 10 has acknowledged the current data word. When either the CPU or DSP 10 writes to the semaphore data word, the DSP 10 automatically sets the correct status bit and clears all others. When either the CPU or the DSP 10 writes to the semaphore ACK address, the appropriate ACK bit in the semaphore status register is set. Thus by reading the semaphore status register, both the CPU and the DSP 10 can determine the status of the other'activities relative to the semaphore data word and proceed accordingly.

As shown in FIG. 5, the 10-bit RDADDR bus 124, provided by instruction/operand fetch subsystem 20, is connected to the 10-bit address input of the read port of IRAM 310 as well as of EIRAM 312. RDADDR is also connected to OE logic 318, which provides output enables IRAMOE to the output enable input of IRAM 310, EIRAMOE to the output enable of EIRAM 312, CNTROE to the output enable of DSP clock counter 320, as well as various other output enables (not shown). RDADDR(9:0) bus 124 is also connected to one input port of a 2-input, 10-bit wide multiplexer 322, the output of which is connected to the input of two registers WRITE0 and WRITE1, 324 and 326, respectively. Control unit 26 determines which WRITE register will load in the value provided by multiplexer 322. These registers hold the address for writes by the DSP 10, and as explained hereinafter, also facilitate an automatic write-back function of the present embodiment.

The 10-bit outputs of the WRITE0 and WRITE1 registers 324 and 326 are provided as inputs to respective input ports of a 2-input, 10-bit wide multiplexer 328, the 10-bit output of which forms an internal WRADDR(9:0) bus 330. WRADDR(9:0) is connected to the 10-bit write address input of IRAM 310, and also to the input of a 10-bit EOADDR register 332. WRADDR is also connected to WE logic 334, which generates an IRAMWE write enable signal for IRAM 310, and EORAMWE signal for the EO address and data registers 332 and 340, and a RELOADWE signal for DSP clock reload register 336 (described below). WE logic 334 also includes a latch input 338 generated by control unit 26.

The WRDATA(15:0) bus from buffer/computation subsystem 22 is connected to the 16-bit write data input of IRAM 310. It is also connected to a 16-bit EODATA register 340, and to the input of reload register 336. As will be seen, the EOADDR register 332 and the EODATA register 340 emulate the function of the write-only random access memory locations destined for output through the EOFIFO.

When the DSP 10 resets, PC register 116 (FIG. 2) is reset to 0 and the value in reload register 336 is loaded into counter 320. The DSP 10 then begins executing the program as the counter 320 counts down in response to each tick of the system clock signal. When the counter 320 underflows, it asserts a signal on underflow line 344. Underflow line 344 is provided to reset logic 345, which also receives an externally supplied reset signal Ext.sub.-- Reset. Reset logic 345 generates a reset output which resets the PC register 116 to zero, thereby restarting the program at address 0. The counter 320 is also recycled by loading in the value from reload register 336. The DSP 10 is thus an inherently cyclic machine, having a cycle time of the number of system clock ticks indicated by reload register 336. After each such number of ticks, the entire program restarts.

Illustratively, the DSP system clock may operate at 568 times a CD audio sample rate, in which case the number loaded into reload register 336 would be 565 (since various delays add three ticks to the cycle time). If one input sample is processed in each cycle, then the DSP 10 can perform 568 ticks worth of operations for each sample. 568 clock ticks provide sufficient time to perform a significant amount of digital signal processing computation on each value in the incoming audio sample stream. Note that if the value in reload register 336 is zero, cycling is disabled and the DSP 10 operates as a normal linear machine.

More specifically, the processor 10 can be reset either non-cyclically, over the Ext.sub.-- Reset line shown in FIG. 5, or cyclically. Non-cyclic resets behave differently depending on whether Ext.sub.-- Reset is held asserted for one or two clock ticks. Cyclic resets occur either in response to the counter 320 underflow output or in response to an externally supplied AUDWS signal. AUDWS is provided to enable an external source to dictate the cycle time of a program. Such a technique, known as audlock, is useful if the audio serializer 362 output is to be provided to an output filter which requires its own crystal. The DSP 10 can enable or disable audlock by setting or clearing an audlock bit in the processor 10 (address 3EB).

Reload register 336 is automatically set to 565 by a non-cyclic reset and is writable by DSP software and readable by an external CPU. The default value of 565 creates a 568 tick cycle which is appropriate for CD-audio rates. The counter 320 decrements continuously when the DSP is turned on and is reloaded with the current reload register 336 value when it underflows. The counter 320 is read-only by DSP software.

When there is a non-cyclic reset, the reload register 336 is loaded with 565 and the counter 320 is loaded with the prior reload register value. This means that a non-cyclic reset must be held asserted for two or more ticks to allow the 565 to propagate into the counter. This also means that if the DSP software changes the reload value in the beginning of its code and then the external non-cyclic reset is held asserted for only one tick, the DSP 10 will operate at the software selected cyclic rate rather than 568 tick cycles. CPU software should be able to issue either a one or two tick reset to the DSP 10 over the Ext.sub.-- Reset line to take advantage of this. A non-cyclic hardware reset signal is always held asserted for at least two ticks and so will cause the DSP to return to a 568 tick cycle. Any non-cyclic reset zeroes all registers and latches in the DSP other than the counter and reload register. This includes a primary enable bit (not shown) bit which allows the DSP to run. The CPU must therefore restart the DSP after a reset.

Whenever the counter underflows, the DSP will be reset as previously described. All sequential logic will be zeroed and the DSP program will start afresh. If the current DSP program has to output audio data, and audlock is turned off, it must check the ready bits of the audio output FIFO to determine if there is space available. The audio FIFO is double buffered so the DSP software need only check the status every 568 ticks. Thus, programs running a cycle shorter than 568 ticks need only check the status once in the program.

If audlock is turned on, when the externally supplied AUDWS signal transits from high to low, the DSP will be reset. The DSP counter will behave as if a normal non-cyclic external reset occurred (it will reload with the current reload value) but counter underflows will not generate a DSP reset. Note that if software wishes to use the counter as a measurement of how much time is left in the cycle, it should set the reload value to indicate a cycle longer than the audlock cycle. This guarantees that the counter will not reload due to underflow and cause inaccurate readings.

Note that DSP memory is not affected in any way by any reset signal, except that a reset that occurs during a write to memory is likely to produce unpredictable datum at that location.

The 16-bit data output of the read port of IRAM 310 is connected to the RDDATA(15:0) bus provided to instruction/operand fetch subsystem 20 (FIG. 1). The data output of the read port in EIRAM 312 is also connected to the RDDATA(15:0) bus, as is the output of counter 320. The low-order 10 bits of RDDATA(15:0) bus are also provided to the second input port of multiplexer 322. The path from the read data outputs of IRAM 310 and EIRAM 312, through the multiplexer 322 and the write registers 324 and 326 to the WRADDR bus 330, is used for indirect write addressing.

Writes to addresses 300h-3FFh are, as previously mentioned, to the EO portion of DSP address space. These registers do not actually exist in the RAM/IO subsystem 24, but instead are emulated by the EOADDR register 332 and EODATA register 340. The outputs of both of these registers are connected to an EOFIFO control unit 346 which in turn writes EO data to an appropriate structure corresponding to the EO address, in an EOFIFO array 316. The EOFIFO array 316 contains four 16-bit wide, 8-word deep FIFOs corresponding to DSP address locations 3F0h-3F3h, sixteen 16-bit words (the "quick-out" latches), readable by an external CPU, a word for CPU interrupt data, and a word for the clock reload value to be read by an external CPU. The EOFIFO array 316 has separate read and write ports, and for the FIFOs, the read port is connected to a FIFO output bus 350, which is in turn connected to an input port of an EIO controller 351. The EIO controller 351 communicates bi-directionally with an external MEM bus 353. EIO controller 351 asserts DMA requests as appropriate to a local DMA arbiter/requestor 352, which in turn arbitrates with other devices in the system for control of MEM bus 353.

Writes to the two addresses of the EO portion of DSP address space which are for left and right audio output data, are coupled from the EO FIFO control unit 346 to an audio serializer 362, the output of which provides serial audio data to an output filter/DAC (not shown). Left and right audio data is provided to the serializer 362 in an alternating manner.

Since the EO addresses are intended to appear to programs running in the DSP 10 as true registers, the EO FIFO controller 346 should be able to read and pass on the data as fast as actual registers would receive the data, that is, once each tick. If a FIFO in the EO FIFO overflows, EO FIFO control unit 346 may generate an interrupt over a line 354.

The EIO controller 351 also has an output port 355 which is connected to the write port of a dual port EIFIFO FIFO array 314. The read port of EIFIFO FIFO array 314 is connected to an EI FIFO control unit 356. The EIFIFO unit 314 is an array of 15 16-bit wide, 8-word deep FIFOs, one corresponding to each of the addresses 0F0h-0FEh. The EI FIFO control unit 356 monitors the address bus RDADDR(9:0) as well as the EIRAMOE signal, and when it detects that information has been read from one of the addresses 0F0h-0FEh in EIRAM 312, it automatically reads a value from the corresponding FIFO in the EIFIFO array 314 and writes it into the location in EIRAM 312 from which the information was read. Accordingly, each time the DSP program reads a value from one of these addresses in EIRAM 312, it is replenished with a new value from an input FIFO. If the corresponding FIFO in EIFIFO array 314 is empty, then the last-read value is repeated. A FIFO underflow bit is also set in the FIFO status word, and can be set to interrupt an external CPU.

The FIFOs in EI FIFO array 314 corresponding to addresses 0FDh and 0FEh receive their input from an FM deserializer 360 rather than from the EIO controller 351. The FM deserializer 360 is one of several units which could be chosen as an input source to one of the FIFOs in the array 314, but is particularly appropriate for a digital signal processor optimized for audio applications. The input to the FM deserializer 360 is adapted to derive from a serial bit stream provided by an external audio synthesizer chip such as a Yamaha 2151. The deserializer can also accommodate serial sound data according to Philips I.sup.2 S format.

The EI FIFO control unit 356 also can receive input directly from a host CPU, over lines 358. The EI FIFO control unit 356 monitors external address and data bus lines, chip selects and read/write strobes, for this purpose. The EI FIFO control unit 356 is responsible for arbitrating between data arriving from the CPU directly and data from one of the EI FIFOs to be written into EIRAM 312. Note that the EI FIFO control unit 356 has temporary storage for only two half words of data from the CPU. Thus, if a program running in the DSP 10 reads a FIFO value on many consecutive ticks, the EI FIFO control unit 356 will not be able to receive and store additional words from the CPU. Accordingly, if input values are expected from the CPU over the line 358, the program running in the DSP should not read more than four consecutive FIFO addresses without pausing for two ticks, or not more than two FIFO reads without a one-tick pause. Additionally, the DSP program should not try to read from the same FIFO on two consecutive clock ticks, since the EI FIFO controller 356 replaces read EIRAM data with new FIFO data on the tick following the tick in which is was read from EIRAM. If the DSP reads from the same FIFO on two consecutive ticks, it will receive the same word both times.

FIG. 6 is a symbolic detail of control unit 26 (FIG. 1). It comprises three finite state machines, namely a fetch controller 410, an operand load controller 412, and a computation controller 414. Roughly, the fetch controller 410 controls the operation of instruction/operand fetch subsystem 20, the operand load controller 412 controls the loading of information into the double buffers in the buffer/computation subsystem 22, and the computation controller 414 controls the operation of the computation engine in the buffer/computation subsystem 22. The control unit 26 also includes several latches for storing additional variables used by one or another of the state machines. In particular, control unit 26 includes a 1-bit DO.sub.-- WRITE0 latch, which indicates that the WRITE0 latch 324 (FIG. 5) contains a valid write address, and also a DO.sub.-- WRITE1 latch which indicates that the WRITE1 latch 326 contains a valid write address. The control unit 26 also includes an OP.sub.-- RDY bit, which is written by the operand load controller 412 to indicate that all the operands necessary to accomplish a computation have now been loaded into the respective first stage latches of the double buffers in buffer/computation subsystem 22. The bit is read by the computation controller 414 to determine when it may begin computation. If this bit is set, and a computation is not currently in progress, the computation controller 414 automatically causes the loading of all the first stage registers into the second stage registers in the double buffers of the buffer/computation subsystem 22, clears the OP.sub.-- RDY bit, and begins the computation. In order for a computation to begin immediately, if the computation engine is available when the last operand is to be loaded into one of the double latches, the last operand is loaded directly into the second stage of the double latch via multiplexer 213 (FIG. 4). Additionally, the OP.sub.-- RDY latch should be designed to end up in the cleared state if the operand load controller 412 attempts to set the bit at the same time the computation controller 414 attempts to clear it. This can save a clock tick.

The control unit 26 also includes a COMPUTE.sub.-- WAIT double latch. The first stage of the COMPUTE.sub.-- WAIT latch is loaded by the fetch controller 410 to indicate the number of clock ticks which will be required for the compute engine to complete the next calculation. This value is loaded into the second stage of the COMPUTE.sub.-- WAIT double latch when the computation begins. In this second stage, it operates as a 4-bit shift register with a 1 in the bit indicating the number of clock ticks remaining. After each clock tick, the computation controller 414 shifts the value by one bit.

The control unit 26 also includes five latches identified as MULTI.sub.-- RQ, MULT2.sub.-- RQ, ALU1.sub.-- RQ, ALU2.sub.-- RQ and BS.sub.-- RQ. These bits are set by the fetch controller 410, based on an incoming instruction word, to indicate to the operand load controller 412 which of the double latches of the buffer/computation subsystem 22 need to be loaded with operands. The operand load controller 412 clears each of these bits as it obtains and loads in the specified operands. Each of the latches DO.sub.-- WRITE0, DO.sub.-- WRITE1, OP.sub.-- RDY, and the RQ latches, may be set-reset flip-flops.

The control unit 26 also includes a 5-bit OP.sub.-- MASK register which is loaded by the fetch controller 410 from bits 4:0 of an OP.sub.-- MASK instruction. The OP.sub.-- MASK register contains one bit corresponding to each of the request bits MULT1.sub.-- RQ, MULT2.sub.-- RQ, ALU1.sub.-- RQ, ALU2.sub.-- RQ and BS.sub.-- RQ. If an OP.sub.-- MASK bit is set when the fetch controller 410 is decoding an instruction to determine which operands to obtain, the fetch controller 410 is prevented from setting the .sub.-- RQ bit corresponding to the OP.sub.-- MASK bit which is set. Thus the computation called for in the instruction will proceed using one or more operands which were obtained for a prior instruction. In essence, masked operands become implied, and need not be re-specified in subsequent instructions. Note that a masked operand is re-used only for the same purpose for which it was used originally--the DSP 10 has no facility for moving operands among the different double buffers of FIG. 3, although that would be possible in a different embodiment.

The state machine definition for fetch controller 410 is illustrated in an emulation pseudocode in Appendix I, and the state machine definition for the operand load controller 412 is illustrated an emulation pseudocode in Appendix II. The state machine definition for computation controller 414 is illustrated an emulation pseudocode in Appendix III. Accordingly, these machines will not be further described except as necessary for a better understanding of the invention.

The operation of the DSP 10 will now be described with respect to the instruction and operand formats illustrated in FIG. 7.

FIG. 7 illustrates the six formats which a 16-bit word fetched from program memory 12 can have. The first word is always assumed to be an instruction rather than an operand, and each instruction includes an indication of the number of operands which follow. After the appropriate number of operand words are read, the next word is again assumed to be an instruction word. Accordingly, no bit is required to indicate whether a given word is an instruction word or an operand word.

Instruction words can either be arithmetic or control instructions. If bit 15 is 0, then the instruction is an arithmetic instruction, and if bit 15 is 1, the instruction is a control instruction. Format A illustrated in FIG. 7 is the format in which control instructions are provided. Control instructions include branch instructions, move instructions and various special instructions. It includes a branch condition code in bits 14:10, made up of two mode bits (MO and Ml in bits 14:13), a FLAG select bit S in bit 12, and two FLAGMASK bits in bits 11:10. The instruction also includes a 10-bit branch address BCH.sub.-- ADDRESS in bits 9:0. In modes 01, 10 and 11, the branch condition bits are used to test the value of five status bits provided by the ALU 254. These bits are set by ALU 254 in status register 255 as follows:

Together the branch condition codes can cause a branch in response to any of the following combinations of conditions:

Branch if overflow

Branch if negative

Branch if negative and overflow

Branch if equal to zero

Branch if carry

Branch if unsigned overflow

Branch if carry and zero

Branch if not overflow

Branch if positive

Branch if negative and overflow both not set

Branch if not equal to zero

Branch if carry clear

Branch if not unsigned overflow

Branch if carry and zero both not set

Branch if less than (signed)

Branch if less than or equal (signed)

Branch if greater than or equal (signed)

Branch if greater than (signed)

Branch if high (unsigned)

Branch if low or the same (unsigned

Branch if exact

Branch if not exact

Branch if all zero

Branch if not all zero

When a branch instruction is received in NRC 110 (FIG. 2), the fetch controller 410 detects this, tests the conditions specified, and if the branch is to be taken, loads the BCH.sub.-- ADDRESS from NRC(9:0) into the PC 116 via the first port of multiplexer 114. If a computation is currently proceeding in the computation subsystem 22, the fetch controller 410 waits for it to complete before testing the conditions. If the conditions are not satisfied, then the fetch controller 410 merely increments PC register 116.

If both the mode bits M1 and MO are zero in a control instruction, then any of several special instructions may be invoked depending on the remaining bits in NRC. In particular, if NRC(12:10) are not equal to 000, then they represent one of the following instructions:

If the mode is 00 and NRC(12:10) are 000, then an additional series of special instructions are indicated. These instructions are:

The mode 00 instructions are designed to execute in a single clock tick except the moves. The mode 00 instructions do not need to wait for the completion of a pending computation in buffer/ computation subsystem 22. In particular, on a JUMP instruction BCH.sub.-- ADDRESS is loaded directly into PC 116 from NRC(9:0) via the first input port of multiplexer 114. The same operation occurs on a JSR except that at the same time, the return address is also latched into SUBR latch 120 from the PC(9:0) bus 16. This bus contains the address following that which contained the JSR instruction, since the PC register 116 was automatically incremented when the JSR instruction was loaded into NRC 110. Thus, by the next clock tick, after fetch controller 410 has decoded the contents of NRC 110 to determine that a JSR is specified, PC 116 already contained the return address.

The BFM instruction is typically placed after another branch to take advantage of the one clock-tick latency before the branch is actually taken. Whenever a branch is taken, the fetch controller 410 automatically sets a JUST.sub.-- BRANCHED bit which is tested during the decode of each instruction loaded into NRC 110. Except if the instruction in NRC 110 is a special instruction or a BFM instruction, fetch controller 410 merely ignores the instruction in NRC 110 if JUST.sub.-- BRANCHED is set, increments the PC register 116, and awaits the next instruction to be loaded into NRC 110. It also clears the JUST.sub.-- BRANCHED bit. If the instruction in NRC 110 is one of a predefined set of the special instructions, then it is executed since it requires only one clock tick to accomplish. If the instruction in NRC 110 is a BFM instruction, the BCH.sub.-- ADDRESS from the BFM instruction is loaded into the PC register 116 via the first input port of multiplexer 114. Branch instructions other than BFM are not executed when JUST.sub.-- BRANCHED is set.

The operation of the BFM instruction can be better understood with reference to FIG. 8, which illustrates what information is loaded into the PC register 116 and the NRC register 110 on each of a sequence of five clock ticks. The figure assumes a "normal" instruction stream, which includes a branch instruction designating a branched target address followed by a BFM instruction designating a BFM target address. At clock tick 0, it is assumed that the address containing the branch instruction is loaded into the PC register 116. At clock tick 1, the branch instruction itself, pointed to by PC register 116, is loaded into the NRC 110. At the same time, PC register 116 is incremented to point to the address of the word following the branch instruction and containing the BFM instruction. The branch instruction has not yet been decoded. By the second clock tick, the branch instruction has been decoded and the branch target address is loaded into PC register 116. At the same time, however, the instruction word pointed to by PC register 116, namely the word containing the BFM instruction, is loaded into the NRC register 110.

On the third clock tick, the word then pointed to by PC register 116, now the first instruction of the branch target stream, is loaded into NRC register 110. By now the BFM instruction has been decoded and the target address specified therein is loaded into PC register 116.

By the fourth clock tick, the first instruction of the branch target stream has been decoded and no attempt is made to prevent its execution. However, the next instruction loaded into the NRC register 110 on the fourth clock tick is the instruction then pointed to by PC register 116 which is the first instruction of the BFM target stream. Also on the fourth clock tick, PC register 116 is incremented to now point to the word following the BFM target address.

Accordingly, it can be seen that the BFM instruction permits execution of a single instruction in a target stream specified by a branch instruction which immediately precedes the BFM instruction, after which control is automatically transferred to the address specified in the BFM instruction. The BFM instruction is beneficial for quickly jumping to a distant location and returning. Using BFM to accomplish such a task is faster than a traditional branch and return, since the instruction stream pipeline latency caused by a branch is reduced. The BFM instruction is beneficial also where subroutine nesting is limited. In the present embodiment, for example, subroutine nesting is limited to the one level for which a return address can be stored in SUBR register 120. The BFM instruction permits a call to what is essentially a one-instruction subroutine, without disturbing any higher-level subroutine return address which may then be stored in SUBR register 120. Further, the BFM instruction can help improve reliability of the DSP 10 in the situation where an external CPU desires to change a single instruction in the program memory 12 while the DSP 10 is running. Such an operation could be dangerous if the instruction is located in the middle of a program, but safer if it is located in a different part of the program memory 12. The BFM instruction permits the DSP 10 to retrieve and execute such a changeable instruction efficiently, without requiring the instruction to be located in the middle of the DSP program. It should be noted that the DSP 10 will execute branch target instruction only if it can be executed in one clock tick. Longer instructions, including any which require an operand in the location following the branch target instruction, will not be executed.

The BFM instruction is capable of many variations. For example, if the instruction pipeline is longer than two clock ticks, then the BFM instruction may permit more than one instruction (or a more-than-one tick instruction) to be executed from the branch target stream before control is transferred to the BFM target stream. In another variation, it can be seen that the BFM target address can be specified other than as an immediate value. Additionally, it can be seen that instructions other than branch instructions can be made available in the branch latency time period.

Referring again to FIG. 7, if the instruction in the NRC is a MOVEREG or MOVE, then the fetch controller 410 transfers control to the operand load controller 412 to execute the move. Before transferring control, the fetch controller 410 waits for the appropriate WRITE0 or WRITE1 register 324 or 326 (FIG. 5) to become available for storing the destination address, and waits for any indirection taking place in the operand load controller 412 to complete. The operand load controller 412 then loads the destination address into the appropriate write address register 324 or 326. If the instruction is a direct MOVE, then the destination address is taken from NRC(9:0) via the first input port of multiplexer 122 (FIG. 2), the RDADDR bus 124, and the second input port of multiplexer 322 (FIG. 5). If the instruction is a direct MOVEREG, then the destination address is taken from register logic 128 via the second input port of multiplexer 122, the RDADDR bus 124, and the second input port of multiplexer 322. If the instruction is an indirect MOVE or MOVEREG (i.e. a move to an indirect address), then the multiplexer 122 selects a direct address from either NRC(9:0) or register logic 128, as appropriate, onto the RDADDR bus 124. The direct address addresses the DSP memory space to combinationally generate an indirectly obtained address on the RDDATA(9:0) bus, which is selected by multiplexer 322 to the appropriate WRITE register 324 or 326.

In all such cases, the operand load controller 412 chooses the appropriate WRITE register 324 or 326 to avoid any write address which may be stored in one of these registers pending the outcome of a computation currently taking place in the compute engine of the buffer/computation subsystem 22. The fetch controller 410 then fetches the next word, which contains the operand in one of the formats C, D or E of FIG. 7, to be moved into the specified location. Format F is inappropriate since only one operand can be moved at a time, and format F is necessary only when three operands are to be specified. The operand load controller 412 controls the register decoding, immediate justification, or indirection as explained hereinafter required to place the operand onto the operand bus 134 (FIGS. 2 and 3), and to load it into the MOVE register 236 (FIG. 3).

It then controls multiplexer 270 to place the data from the move register 236 onto the WRDATA bus (FIGS. 3 and 5), and controls the multiplexer 328 to place the write address onto the WRADDR bus (FIG. 5) to write the data into the specified register address in IRAM 310, EODATA register 340, or reload register 336. It can be seen that the MOVE instruction and the MOVEREG instruction can be executed without affecting any calculation currently taking place in the compute engine of buffer/computation subsystem 22, and without needing to wait for such a computation to complete.

If the instruction in NRC register 110 is a BAC instruction (branch to accumulator), then the fetch controller 410 waits for any computation currently taking place to complete and then loads ACC(13:4) from the accumulator 258 (FIG. 3) into PC register 116 via the second input port of multiplexer 114 (FIG. 2).

If the instruction in NRC 110 is an OP.sub.-- MASK instruction, then the fetch controller 410 loads the value from NRC(4:0) into OP.sub.-- MASK register 138. Similarly, if the instruction in NRC 110 is an RBASE instruction, then the fetch controller 410 loads the value from NRC(5:0) into RBASE register 140, and if the instruction in NRC 110 is an RMAP instruction, then the fetch controller 410 loads the value from NRC(2:0) into RMAP register 142.

If the instruction in NRC 110 is an RTS (return from subroutine) instruction, then the fetch controller 410 loads the value from subroutine latch at 120 into PC register 116 via the third input port of multiplexer 114. Only one subroutine level is permitted in the processor 10.

If the instruction in NRC 110 is SLEEP, then the fetch controller 410 merely remains in its current state without loading any new instructions into NRC register 110. Unlike a conventional "JUMP to present address" instruction, no further fetches are made to external instruction memory after a SLEEP instruction is decoded. Any computations currently taking place in the computation engine continue through to completion, but no subsequent operations are initiated. The SLEEP instruction is useful to conclude a program, since the DSP 10 will do no further work until the program is restarted either by the underflow output 344 of counter 320 (FIG. 5) or by an external reset signal.

Arithmetic instructions are distinguishable from control instructions by the presence of a logic 0 in bit 15. Arithmetic instructions follow format B illustrated in FIG. 7. In particular, bits 14:13 indicate the number of operands which follow the instruction; bit 12, identified as M2.sub.-- SEL, indicates whether an ACC/carry word or one of the operands is to be used for the second input of the multiplier 252 (FIG. 3); bits 11:8 indicate which selections should be made by the dual multiplexer 264 (FIG. 3) in providing operands to the ALU 254; bits 11:10 select the source for the `A` input port of the ALU and bits 9:8 select the source for the `B` input port of the ALU. Bits 7:4 contain a 4-bit function select for the ALU 254, and bits 3:0 contain a 4-bit shift amount number for the barrel shifter 256.

When an arithmetic instruction is loaded into NRC 110 (FIG. 2), the fetch controller 410 first checks the OP.sub.-- RDY bit to determine whether valid operands from a previous instruction are still waiting in the first stage buffers of the double buffers in the buffer/computation subsystem 22. If OP.sub.-- RDY is set, the fetch controller 410 waits for it to be cleared. The fetch controller 410 also awaits the completion of any indirect address determination currently being resolved by operand load controller 412. Once these two conditions are clear, the fetch controller 410 determines from a decode of the instruction in the NRC 110, which of the double buffers 210, 230, 232, 234 and 250 (FIG. 3) will need to be filled with operands from subsequent words. It then sets the appropriate operand request (.sub.-- RQ) bits in control unit 26 (FIG. 6) corresponding to the double buffers which will need to be filled. If the OP.sub.-- MASK bit corresponding to one of the operands is set, then the fetch controller 410 does not set the corresponding operand request bit. Instead, the operation will proceed by re-using the operand most recently used for that corresponding operand.

Fetch controller 410 also sets an N.sub.-- OPS register with a logic 1 in the bit corresponding to the number of operands which need to be fetched (including a write address if appropriate). N.sub.-- OPS is a 4-bit shift register, each bit representing a corresponding number of operands which still need to be FETCHED from program memory. For example, a 1 in bit 0 indicates that one operand needs to be fetched. A 1 in bit 1 indicates that two operands need to be fetched and so on. No more than one bit in the shift register should be active at a time. The fetch controller 410 uses NRC(14:13) in determining the number of operands as follows:

Note that an instruction may have yet another operand to load in response to a 1000 in the BS field of NRC 110 as described below. That operand is not included in the number of operands shown in the table above.

Fetch controller 410 also determines from another decode of the instruction in NRC 110, the number of clock ticks that the computation engine in buffer/computation subsystem 22 will require to complete the specified computation. It then loads the first stage of the COMPUTE.sub.-- WAIT latch accordingly.

The operand load controller 412 latches the M2.sub.-- SEL field from NRC 110 into the first stage of the M2.sub.-- SEL double latch 238, the AMX field from NRC 110 into the first stage of AMX double latch 240, and the ALU field from NRC 110 into the first stage of ASEL double latch 242 in the buffer/computation subsystem 22. Additionally, if the value in the BS field of NRC 110 is anything but 1000, the operand load controller 412 loads the value into the first stage of BSEL double latch 250 via the second input port of multiplexer 248. Since the shift type (arithmetic or logical) depends on the ALU operation, specifically the high order bit of the ALU field of the arithmetic instruction, this bit is also loaded into the first stage of ET double latch 246 via the second input port of multiplexer 244. As explained hereinafter, only if BS=1000 is any operand fetching required to control the barrel shifter 256. The fetch controller 410 then proceeds to fetch the requested operands according to the .sub.-- RQ bits in the manner described hereinafter, and the load controller 412 writes them into the respective first stages in the corresponding double buffers in buffer/computation subsystem 22. Load controller 412 is responsible for shifting N.sub.-- OPS down as each operand is received and placed in its appropriate double buffer. If more operands are indicated by N.sub.-- OPS than are requested by the RQ bits, then the last operand is assumed to represent a write address. The write address is calculated from this operand like any other, and is stored in an available WRITE latch 324 or 326 (FIG. 5). The corresponding DO.sub.-- WRITE bit is also set (FIG. 6).

All the operand loading can take place while the computation engine of the buffer/computation subsystem 22 is performing a computation according to a previous instruction. This is because the new values written into the first stages of the double buffers in buffer/computation subsystem 22 do not affect the values in the second stages, which actually supply operands to the computation engine.

When all of the required operands are loaded, or if the instruction in NRC 110 does not require any operands, the computation controller 414 first awaits the completion of any computation then in progress in the computation engine in buffer/computation subsystem 22. If there is no computation taking place, then the computation controller 414 immediately transfers all the first-stage buffers of the double buffers into the second stages to begin the specified computation. If operands were required, then the computation controller 414 waits until the last operand is being loaded into its double buffer before transferring all the first-stage buffer information into the second stage. In the latter case, the last operand is loaded directly into the second stage of its double buffer, at the same time that all of the other first-stage buffer information is transferred to the second stage. In either case, once the computation begins, the computation controller 414 merely waits the number of clock ticks indicated by the second stage of COMPUTE.sub.-- WAIT, so that the calculation may propagate completely through the computation engine. At the conclusion of the waiting period, the computation controller 414 loads the result into accumulator 258 and the ALU status output bits into status register 255.

In addition to providing a conventional write address as described above, an instruction can instead merely indicate that the result of an operation is to be written back to the address of one of the input values. As explained hereinafter, several of the operand formats can specify whether the result of a calculation is to be written back to the address that an operand came from. If it is, then the operand load controller 412 will have written the write-back address into one of the WRITE0 or WRITE1 latches 324 or 326 (FIG. 5), and set the corresponding DO.sub.-- WRITE bit (FIG. 6). When the calculation is complete, if one of the DO.sub.-- WRITE bits is set (either because a conventional write address was provided or because a write-back bit was set), the computation controller 414 performs the write-back by enabling the appropriate WRITE latch 324 or 326 onto the WRADDR bus 330 via multiplexer 328 (FIG. 5), and enabling ACC(19:4) onto the WRDATA bus via the second input port of multiplexer 270 (FIG. 3). The computation controller 414 also clears the corresponding DO.sub.-- WRITE bit at this time. Writes can take place concurrently with the beginning of the next computation. If no DO.sub.-- WRITE bit is set, the result is still available for further use in the computation engine. It should be noted that if a MOVE or MOVEREG instruction is underway at the time a result is ready to be written, the write may be delayed until the move is complete.

The DSP 10 supports six basic types of operands: instant, immediate, direct, indirect, register direct, and register indirect. The only instant operands are those present in an arithmetic instruction itself, in the BS field. As mentioned above, for any value in the BS field other than 1000, the BT and BSEL double buffers 246 and 250 (FIG. 3) are loaded with data from the NRC register 110. No fetch of a subsequent word is required to obtain the operands and load them into these double buffers. If the BS field does contain 1000, then one of the subsequently identified operands contains the information to load into these double buffers.

Operands (other than instant operands) are written to the corresponding double latches for which the .sub.-- RQ bit is set (FIG. 6), in a predefined sequence. Immediate operands are identified by the presence of a `11` in bits 15:14 of an operand word. As shown in format C of FIG. 7, the immediate operand format includes a justify bit (bit 13) and 13 bits of an immediate value (bits 12:0). The justify bit indicates whether the 13-bit immediate value is to be left or right justified in a 16-bit field. If it is to be left justified, then zeros are added to the right, and if it is to be right justified, then the value is sign extended to the left. When an immediate format operand is retrieved from program memory and written to NRC register 110, the low-order 13 bits are extracted and justified by immediate justification logic 130 in accordance with NRC(13) (FIG. 2). The operand load controller 412 selects the output of immediate justification logic 130 onto the OP bus 134 via the first input port of multiplexer 132, and clocks it into the appropriate double latch in the buffer/computation subsystem 22 (FIG. 3).

Non-register direct or indirect operands are identified by the presence of `100` in bits 15:13 of the operand word. Such operands follow the format D illustrated in FIG. 7. In this format, bits 9:0 identify an operand address, bit 10 specifies whether the address is to be interpreted as direct or indirect, and bit 11 specifies whether "write-back" is desired to this operand. Any one operand may be marked for write-back except an immediate operand or a member of a 3-register group. The write-back feature speeds read-modify-write type operations and saves program space.

When a non-register direct or indirect format operand is loaded into NRC 110, the operand load controller 412 enables NRC(9:0) onto the RDADDR bus 124 (FIG. 5) via the first input port of multiplexer 122 (FIG. 2). Any address in IRAM 310 or EIRAM 312 may be read. The addressed one of these two units then outputs a data word onto the RDDATA bus. The RDDATA bus is enabled onto the OP bus 134 (FIG. 3) via the multiplexer 132 (FIG. 2), and on the next clock tick, assuming this is a direct operand address, it is loaded into the appropriate double latch in buffer/computation subsystem 22. If NRC(10) indicates that the operand address is indirect, then instead of loading the data into the appropriate double latch, the operand load controller 412 loads the low-order 10 bits of data from the RDDATA bus into the INDIRECT register 136 (FIG. 2). The output of the INDIRECT register 136 is then enabled onto the RDADDR bus 134 via multiplexer 122, and a new data value is read from either IRAM 310 or EIRAM 312 onto the RDDATA bus and provided to the OP bus 134 via multiplexer 132 (FIG. 2). If write-back bit NRC(11) is set, the operand load controller loads the address of the operand into one of the WRITE address registers 324 or 326 either from the RDADDR bus 124 via the second input of multiplexer 322, for direct addressing, or from the RDDATA bus 124 via the first input of multiplexer 322. As previously explained, the computation controller 414 will use this address to write back the computation results from the accumulator 258 (FIG. 3) to the specified address. It can be seen that non-registered immediate or directly addressed operands occupy one word of instruction space and require one clock tick to fetch and load into the appropriate double latch. Non-registered indirect addressing also uses one word of instruction space but requires two clock ticks to load the operand into the appropriate double latch. Indirect addressing modes benefit most from the write-back feature since it is the indirect address, not the direct address, which is stored in the WRITE address register. The indirection need only be resolved once in a read-modify-write situation.

The registered operand formats E and F illustrated in FIG. 7 essentially provide a level of indirection without incurring the overhead of indirection. A "register", as used with respect to these formats, is a shorthand identification of an operand address. A register number is 4 bits wide, and the address to which it refers can be specified as either direct or indirect. The registered 1- or 2-operand format illustrated as format E in FIG. 7, permits specifying up to two operands in registered format, either one of which can be indicated for write-back as well. In particular, bits 3:0 contain a first register number and bits 8:5 contain a second register number. Bit 4 indicates whether the address pointed to by the first register number is to be interpreted as direct or indirect, and bit 9 indicates whether the address pointed to by the second register number is to be interpreted as direct or indirect. Bit 11 of the operand word indicates whether the result is to be written back to the address specified by the first register number, and bit 12 indicates whether the result is to be written back to the address specified by the second register number. Bit 10 indicates whether one or both of the register numbers are valid. An operand word specified in registered 2-operand format is identified by the presence of the code `101` in bits 15:13 of the word.

Operand format F as illustrated in FIG. 7 is a registered 3-operand format. It differs from the registered 1- or 2-operand format in that one additional operand may be specified, but none of the three operand addresses can be indicated for write-back. In the registered 3-operand format, bits 3:0 contain a first register number, bits 8:5 contain a second register number, and bits 13:10 contain a third register number. Bit 4 indicates whether the address pointed to by the first register number is to be considered direct or indirect, bit 9 indicates whether the address pointed to by the second register number is to be considered direct or indirect, and bit 14 indicates whether the address pointed to by the third register number is to be considered direct or indirect. An operand word specified in registered 3-operand format is identifiable by the presence of a `0` in bit 15.

When an operand word in one of the registered formats is loaded into NRC 110 (FIG. 2), the operand load controller 412 causes the multiplexer 126 to select the left-most valid register number into register logic 128. If the operand is in Format E, then the register number at NRC(8:5) is used if it is valid, otherwise the register number at NRC(3:0) is used. If the operand is in Format F, then the register number at NRC(13:10) is used. As explained in more detail below, the register logic 128 converts the selected 4-bit register number to a 10-bit address according to RBASE and RMAP values previously specified by the program. The multiplexer 122 selects the output of register logic 128 onto the RDADDR bus 124, which is supplied to the IRAM 310 and EIRAM 312 (FIG. 5). Any indirection specified in NRC(4) is performed in the manner explained above, and the resulting operand is then loaded into the appropriate double buffer in the buffer/computation subsystem 22 (FIG. 3). If the operand was in Format E, and the write-back bit WB2 or WB1 corresponding to the selected register number is set, then the 10-bit operand address is also written to one of the WRITE registers 324 or 326 as explained above.

If the operand word was in Format E and NRC(10) indicated that only one register number is valid, then there are no more operands to load in response to the present operand word. If NRC(10) indicates that both register numbers are valid, then at this point operand load controller 412 controls multiplexer 126 to select NRC(3:0) into the register logic 128 for translation, the output of which is selected by multiplexer 122 onto the RDADDR bus 124. The second operand is then obtained by direct or indirect addressing in the same manner as the first operand. A write-back address is also written to one of the WRITE registers 324 or 326 in accordance with the WB2 bit in NRC(12). Note that no more than one of the write-back bits can be validly set.

If the word in NRC 110 is in Format F, then the operand load controller 412 obtains the first operand as specified by the register number in NRC(13:10). NRC(13:10) is selected via the third input of multiplexer 126 to the register logic 128, where it is translated and provided to multiplexer 122 which selects it onto the RDADDR bus 124. The operand is then obtained by direct or indirect addressing as explained above. Operand load controller 412 then goes on to obtain the second and third operands in the same manner, selecting respectively NRC(8:5) and NRC(3:0) to register logic 128.

FIG. 9 shows a detail of the register logic 128 (FIG. 2). The 4-bit register number from the output of multiplexer 126 (FIG. 4) enters the register logic 128 on a bus 510, and the 10-bit translated address (direct or indirect) is provided on output bus 512. Bits 0 and 1 of the register number on bus 510 are passed directly to respective bits 0 and 1 of the output bus 512. Bit 2 of the input register number is provided to one input of an XOR gate 514, the other input of which comes from bit 0 of the RBASE register 140. The output of XOR gate 514 forms bit 2 of the output bus 512. Bit 2 of the register number is also provided to an x input of twiddle logic 516, the content of which is explained hereinafter. Bit 3 of the input register number is provided to a y input of twiddle logic 516, the output of which forms bit 8 of the output bus 512. Bit 3 of the input register number is also provided directly as bit 9 of the output bus 512. Bits 5:1 of the RBASE register 140 are provided as bits 7:3, respectively, of the output bus 512, and the 3 bits of the RMAP register 142 are provided to a select (S) port of twiddle logic 516. FIG. 10 indicates, in the first two columns, the logic function performed by twiddle logic 516 in response to the 3-bit select value from RMAP register 142 (d indicates "don't care").

In a single instruction, all the 4-bit register numbers select from a single set of 16 addresses. Some of the addresses in DSP 10 duplicatively address the same physical locations, as previously mentioned. Thus, in the power-up default state of RMAP=0 and RBASE=0, the register address mapping will be as follows:

Accordingly, the default RMAP and RBASE values provide four registers in the external in (EI) address range, eight in the internal (I) address range and four in the external out (EO) address range. The registers can be remapped in several ways to allow better access for programs that need to place different emphasis on the different address ranges. For example, a program which requires heavy coefficient access, less intermediate storage and few output variables might use a register mapping which provides eight registers in the EI address range, four in the I address range and four in the EO address range. The last three columns of FIG. 10 set out the number of addresses within each of the three address ranges for each corresponding value of RMAP. The RMAP value may be set by the program using the RMAP instruction described above.

Bits 7:3 of the address specified by a register number in an operand word are provided by bits 5:1 of ABASE register 140. Essentially the addresses pointed to by register numbers can be thought of as being located in 8-word blocks of addresses, one block in each of the two address ranges, EI and EO, and two blocks in address range I. If RMAP is such that eight of the registers point to addresses in one of the address ranges, then those addresses occupy an entire 8-word block. If the RMAP value places four of the registers in one of the address ranges, then those four registers occupy one or the other half of the block. If the RMAP value places all sixteen registers in a single one of the address ranges, which can occur only in the I address range, then the designated address locations occupy two full blocks in that address range.

The RBASE instruction, described above, can be used by a program to change the value in RBASE in order to shift the 8-word blocks within their respective address ranges. Changing the base value changes the base for all of the registers.

Bit 0 of RBASE register 140 provides yet another level of flexibility in the choice of register mappings. In particular, if RBASE(0) equals 0, then the addresses pointed to by register numbers are at the low end or the high end of their block, depending on RMAP. If RBASE(0)=1, then they are at the opposite end of the block specified by RMAP.

It can be seen that the register mapping provided by register logic 128 affords the flexibility of indirection without the overhead of indirect operand fetching. Also, since two or three register identifications can be included within a single operand word (FIG. 7, formats E and F), the space savings achieved with register addressing can be as high as 3:1. Preferably, an assembler is provided with an "RBANK" pseudoinstruction, which translates automatically into a proper RBASE instruction.

It can be seen that a digital signal processor architecture has been described which contains numerous performance-enhancing features. Each feature alone can improve performance, but in combination the performance is enhanced markedly.

The invention has been described with respect to particular embodiments thereof, and it will be understood that numerous modifications are possible within its scope. ##SPC1##