Voltage Control Circuit for Input and Output Lines of Semiconductor Memory Device

The present invention relates to semiconductor memory devices, and more particularly, to a voltage control circuit that controls the voltage level of input and output lines of a semiconductor memory device. The voltage control circuit includes load transistors that are controlled by feeding back an output voltage on the input and output lines. The voltatge control circuit allows the memory device to access data at higher speeds and operate with less power.

In a semiconductor memory device, the demand for high speed operation has increased. Thus, an effort has been made to reduce access cycle time of memory devices. Recent research has been focused on synchronous memory devices where a high frequency synchronous signal is input to the memory device via a pin to operate the memory device. In a conventional synchronous memory device or non-synchronous memory device, input and output lines are connected to a bit line via a column select gate. The input and output lines have a great voltage swing between the power supply voltage Vcc and ground voltage Vss.

The input and output lines are precharged by an address transition detector (ATD) every time the column select line is changed by the change of address. As a result, data loaded on the bit line of a column to be selected can be output without being affected by the voltage of the previous input and output lines. Line precharging should allow high speed access operations while reducing current consumption during address transitions.

In the synchronous memory devices, the following conditions should be performed in order to reduce read cycle times to less than 10 nsec. First, it is necessary to eliminate the time (about 3-4 nsec.) required for precharging the input and output lines during data access. Second, a charge sharing operation should be performed for a short time to reduce the amount of voltage swing on the input and output lines while accessing data.

To achieve the above necessities, a precharging method is used on the input and output lines. According to the input and output line precharging method, the voltage on the input and output lines charged during a first data access, is discharged to a bit line sense amplifier during the next data access.

According to conventional methods, a pair of load transistors are connected to the pair of input and output lines and are both activated during a data access. A direct current (DC) continuously flows through the load transistors increasing current consumption. The voltage on the input and output lines is toggled by the bit line sense amplifier. However, the activated load transistors prevent the voltage on the input and output lines from switching between high level and low levels, in turn, slowing the toggle speed of the input and output lines.

It is an object of the present invention to provide a voltage control circuit that reduces current consumption and accelerates the toggle speed of the input and output lines of a semiconductor memory device.

A voltage control circuit is provided for input and output lines of a semiconductor memory device. The memory device has a pair of bit lines coupled to a plurality of memory cells. A bit line sense amplifier which is connected between the bit lines for sensing and amplifying the voltage difference betwen the bit lines during read operations. A pair of input and output lines are connected to the bit lines via a column select gate. An input and output line sense amplifier which is connected to the input and output lines for sensing and amplifying the voltage difference of the input and output lines. A pair of data lines are connected to the input and output line sense amplifier.

The input and output lines are separately controlled by a clamp circuit that clamps the voltage on the input and output lines while in a low state to a predetermined voltage level value between a ground potential and a power supply voltage. The clamp circuit is activated during read operations by feeding back the output from the input and output line sense amplifier.

In one embodiment, the clamp circuit comprises a pair of load transistors each connected to the input and output lines. The pair of load transistors maintain complementary states with each other according to the output fed back from the input and output line sense amplifier.

The voltage control circuit coupled to the input and output lines, eliminates direct current paths during voltage transition on the input and output lines, thereby lowering current consumption and increasing operation speed.

FIG. 1 is a diagram illustrating a conventional voltage control circuit coupled to input and output lines;

FIG. 2 is an operational timing diagram according to the circuit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a voltage control circuit coupled to input and output lines according to a preferred embodiment of the present invention; and

FIG. 4 is an operational timing diagram according to the circuit illustrated in FIG. 3.

First, the conventional voltage control method for input and output lines will be described with reference to FIGS. 1 and 2. All references to complementary signals are referenced with a tilde ".about.".

Referring to FIG. 1, a memory cell 10 stores data and is connected to a bit line BL0 and accessed in response to the activation of a word line WL. A P-type sense amplifier 12 has PMOS transistors MP1 and MP2 and an N-type sense amplifier 14 has NMOS transistors MN1 and MN2. Amplifiers 12 and 14 are connected between bit lines BL0 and BL1. When accessing data in the memory cell 10, the voltage level at the common node connecting the PMOS transistors MP1 and MP2 in the P-type sense amplifier 12 is equal to the power supply voltage VCC. The voltage level of the common node connecting the NMOS transistors MN1 and MN2 in the N-type sense amplifier 14 is equal to ground potential VSS. Column select transistors MN3 and MN4 are connected between the pair of bit lines BL0 and BL0.about. and input and output lines IO and IO.about., respectively. The above-described structure is common in memory devices.

Conventional voltage control circuits for input and output lines include a clamp device 20 comprising PMOS transistors MP3 and MP4. The PMOS transistors are coupled to input and output lines IO and IO.about., as a load. When reading data, the load transistors MP3 and MP4 are activated generating a direct current flow through MP4, MN4, MN2 and VSS in sequence. If there is no load, the voltage of the input and output line IO.about. is continuously decreased until it reaches 0V. However, if direct current flows through the load transistors MP3 and MP4, the voltage of input and output line IO.about. is obtained by the following formula (1) according to a voltage division principle. ##EQU1##

Thus, the amplitude of the voltage swing for the input and output line IO.about. can be fixed to a predetermined value by controlling a resistance value of the PMOS transistor MP4, that is, R.sub.MP4.

FIG. 2 is a timing diagram for a read operation with the circuit illustrated in FIG. 1. During a first page mode, column addresses CA0 and CA1 are input according to the cycling of a column address strobe signal CAS.about. and when a write enable signal W.about. is high. A column select line CSL0 is enabled by the column address CA0. The bit line BL0in a high state maintains the voltage level VCC. During a low state, the voltage level of the bit line BL0.about. is equal to V1, not VSS. The voltage V1 is due to the DC current path along MP4, MN4, MN2 and VSS formed when the load transistor MP4 is activated as described above.

When the column select line CSL0 toggles high, the voltage levels of the input and output lines IO and IO.about. are toggled by the P-type sense amplifier 12 and the N-type sense amplifier 14. The sense amplifiers are connected between the bit lines BL0 and BL0.about. and toggle the bit lines after a time T2. The voltage levels of the input and output lines IO and IO.about. are decreased by the amount of the threshold voltage V.sub.tn in the NMOS transistors MN5 and MN6 in a level shifter 40. The transistors MN5 and MN6 are coupled to the input and output lines IO1 and IO1.about.. The decreased voltage of the input and output lines IO1 and IO1.about. is amplified by an input and output (IO) sense amplifier 60 and then output to data lines DO and DO.about.. The voltage levels of the input and output lines IO and IO.about. and are decreased before feeding into the IO sense amplifier 60 in order to operate input transistors in a saturation region, when the IO sense amplifier 60 comprises a differential amplifier.

According to the conventional voltage control circuit shown in FIG. 1, DC current is continuously consumed from the load transistors MP3 and MP4 during the entire period that the first column select line CSL0 is enabled. When the voltage levels of the input and output lines are toggled by the bit line sense amplifiers 12 and 14, the load transistors MP3 and MP4 remain active. As a result, the voltage levels of the input and output lines are prevented from transitioning from the high level of VCC to the low level of VCC-.DELTA.V1. Thus, the toggle speed of the input and output lines is decreased. Here, .DELTA.V1 represents the voltage difference between the input and output lines IO and IO.about..

According to the present invention, a new voltage control circuit is used in conjunction with the input and output lines in the semiconductor device to reduce current consumption and to accelerate the toggle speed of the input and output lines.

Referring to FIGS. 3 and 4, a preferred embodiment of the present invention will be described. The circuits and devices which perform the same operation as those shown in FIGS. 1 and 2 have the same reference numerals as those shown in FIGS. 1 and 2.

FIG. 3 is a diagram illustrating a voltage control circuit for the input and output lines according one embodiment of the present invention. FIG. 4 is a timing diagram according to the circuit illustrated in FIG. 3.

Referring to FIG. 3, in the load transistor control circuit 30, .phi.WR signal is high during a read operation and low during a write operation. The output DO of the IO sense amplifier 60 serves as another input of the load transistor circuit 30. When .phi.WR is high and D0.about. is high, a node N2 becomes low. That is, when the data D0 is low, only the load transistor MP3 of clamp circuit 20a is activated. Thus, the voltage on the input and output lines is clamped, not lowered. When the data in the memory cell, selected by the next column address CA1 is high, the voltage of input and output lines IO and Io.about. should be toggled.

The voltage of the input and output line IO rapidly increases from the low level of VCC-.DELTA.V1 to the high level of VCC since the load transistor MP3 of the clamp circuit 20a is activated. Also, the voltage of the complementary input and output line IO.about. rapidly decreases from the high level of VCC to the low level of VCC-V.sub.tn -.DELTA.V2 since the load transistor MP4 of the clamp device 20a is deactivated. As a result, the time from the activation of the next column select line CSL1 to the time when the voltage of input and output lines IO and IO.about. toggles, is decreased to T21. The time T21 is less than the time T2 in the conventional voltage control circuit in FIG. 1, thereby speeding up memory access time. The high speed effect shown in FIG. 3 is further increased of prior art circuitry in memory chips having long input and output lines above 256 megabits.

When the data on the bit lines corresponding to the next column select line to be selected is transferred to the input and output lines IO and IO.about., the DC current path disappears during time T01 and T11 shown in FIG. 4. That is, during the time period when the data on the input and output lines IO and 1IO.about.I0 is toggled, the direct current path is removed decreasing current consumption.

In the operation of a level shifter 40a and a level shifter control circuit 50, PMOS transistors MP5 and MP6 of the level shifter 40a are small in size. The transistors MP5 and MP6 prevent the input and output lines IO and IO.about. from floating and always provide small direct current from MP5 to MN7, and from MP6 to MN8, respectively. Accordingly, the voltage of the input and output lines IO1 and IO1.about. is less than the voltage of the input and output lines IO and IO.about. by as much as the threshold voltage of NMOS transistors MN5 and MN6.

The level shifter control circuit 50 functions to deactivate the transistors MP5, MP6, MN7 and MN8 during a stand-by condition (.phi.YE=high) and a writing operation (.phi.WR=high). Here, the level shifter 40a is required for the IO sense amplifier 60 to easily sense a voltage difference of the input and output lines IO1 and IO1.about.. Like the above-described conventional circuit, when the IO sense amplifier 60 comprises a differential amplifier type, transistors of the IO sense amplifier 60 connected to the input and output lines IO1 and IO1.about. are operated in the saturation region, so that a small voltage difference can be easily sensed.

In the conventional voltage control circuit, the load transistors MP3 and MP4 are always activated during the read operation. In the voltage control circuit according to the invention, activation of the load transistors depends on the output of the IO sense amplifier 60. Thus, only the load transistor MP4 is activated during a high state and only the load transistor MP3 is activate during a low state. Accordingly, the direct current path is eliminated when the voltage levels of the input and output lines IO and IO.about. are toggled, increasing operation speed and reducing current consumption.

As described above, according to the voltage control method for the input and output lines of the present invention, the access time can be reduced in a synchronous memory device which should continuously access data during a short time cycle without precharge of the input and output lines, thereby performing a high frequency operation and preventing the increase of power consumption in the short time cycle.