Integrated Circuit and Method for Generating a Transimpedance Function

The present invention relates, in general, to integrated circuits, and more particularly, to frequency compensated integrated circuits.

Integrated circuit amplifiers are used in a variety of linear and nonlinear circuit applications. For example, they are used in integrator circuits, differentiator circuits, summing circuits, difference circuits, impedance converter circuits, rectifier circuits, peak detector circuits, etc. Generally, it is desirable for these circuits to have a large gain and be stable over a large frequency range, i.e., have a large bandwidth.

Typically, integrated circuit amplifiers include an input terminal and an output terminal. The integrated circuit amplifier can be frequency compensated by coupling the output terminal to the input terminal via a compensation capacitor. The compensation capacitor introduces a dominant low frequency pole into the output response, thereby causing the gain to roll-off at a slope of 20 decibels per decade of frequency (dB/DEC). However, the amplifier negates the roll-off effect of the pole by producing a non-zero output response at high frequencies. Thus, if the gain of the amplifier circuit does not reach unity before the phase angle becomes 180 degrees, the amplifier circuit becomes unstable and oscillates. Further, the output signal may become non-inverted at high frequencies, i.e., frequencies at which the impedance of the compensation capacitor is less than the resistance of the output transistor, thereby limiting the usefulness of the integrated circuit amplifiers at high frequencies.

Accordingly, it would be advantageous to have a method and circuit for providing a stable inverted output signal at high frequencies.

FIG. 1 is a schematic diagram of an example of an integrator circuit in accordance with a first embodiment of the present invention;

FIG. 2 is a schematic diagram of another example of an integrator circuit in accordance with the first embodiment of the present invention; and

FIG. 3 is a schematic diagram of an integrator circuit in accordance with a third embodiment of the present invention.

Generally, the present invention provides an integrator circuit and a method for generating a frequency compensated output signal. The integrator circuit includes a compensation diode, a transconductance amplifier, and a capacitor. The compensation diode provides an impedance that negates the impedance of the transconductance amplifier, thereby making the output signal a function of the capacitor. In a accordance with a method of the present invention a transimpedance function is generated. More particularly, a transconductance amplifier having a transconductance value, an inverting input, and an output terminal is provided. Further, first and second impedances are provided, wherein signal currents flow through the first impedance and create a voltage across the first impedance and signal currents flow through the second impedance and create a voltage across the second impedance. The value of the second impedance is a function of an inverse of the transconductance value of the transconductance amplifier. The voltage across the first and second impedances and the voltage appearing at the inverting input of the transconductance amplifier are summed to produce a voltage which is a function of the first impedance and the input current.

FIG. 1 is a schematic diagram of an example of an integrator circuit 10 in accordance with a first embodiment of the present invention. Integrator circuit 10 includes a transconductance amplifier 11, a compensation diode 12, a capacitor 13, and a bias stage 14. By way of example, transconductance amplifier 11 is comprised of an NPN bipolar transistor 15, wherein the base terminal of transistor 11 serves as a control electrode of amplifier 11 and the collector and emitter terminals of transistor 15 serve as the current carrying electrodes of amplifier 11. The emitter of transistor 15 is coupled for receiving a power supply voltage or source of operating potential such as, for example, ground. The base terminal of transistor 15 is connected to the cathode of compensation diode 12. The anode of compensation diode 12 is coupled to the collector terminal of transistor 15 via capacitor 13. In other words, a first terminal of capacitor 13 is connected to the anode of compensation diode 12 and the second terminal of capacitor 13 is connected to the collector of transistor 15. By way of example, compensation diode 12 is a diode-connected transistor.

Input stage 14 includes current sources 16, 17, and 18. A first terminal of current source 16 is connected to the cathode of compensation diode 12 and a second terminal of current source 16 is coupled for receiving a power supply voltage such as ground. Current source 16 sinks current for integrator 10, it is also referred to as a current sink. Current source (or sink) 16 ensures that compensation diode 12 operates in the forward conduction mode. A first terminal of current source 17 is commonly connected to the anode of compensation diode 12 and to the first terminal of capacitor 13. A second terminal of current source 17 is coupled for receiving a power supply voltage or source of operating potential such as, for example, V.sub.cc. A first terminal of current source 18 is commonly connected to the second terminal of capacitor 13 and to the collector terminal of transistor 15. A second terminal of current source 18 is coupled for receiving a power supply voltage such as, for example, V.sub.cc. A node 19 formed by the common connection of the collector terminal of transistor 15, the second terminal of capacitor 13, and the first terminal of current source 18 serves as an output node or terminal at which an output signal v.sub.o10 appears. A suitable circuit configuration for bias stage 14 may be a current source and a two transistor current mirror. This effectively cancels the base current of transistor 15 and improves the balance when the average direct current (dc) current of transistor 15 is twice that of the current mirror transistors.

In operation, bias stage 14 provides bias or quiescent currents I.sub.16, I.sub.17, and I.sub.18 via current sources 16, 17, and 18, respectively. In addition, current sources 16 and 17 cooperate to provide differential small signal currents "i.sub.d16 " and "i.sub.d17 ", respectively. Preferably, bias currents I.sub.16 and I.sub.17 are of equal value and bias current I.sub.18 is twice the value of bias currents I.sub.16 and I.sub.17. Accordingly, the emitter resistance of transistor 15 is half the emitter resistance of diode connected transistor 12. It should be noted that small signal currents "i.sub.d16 " and "i.sub.d17 " are differential currents that flow into node 33, which is an alternating current (ac) or virtual ground. Thus, capacitor 13 is coupled for receiving a differential current which is the sum of the currents i.sub.d16 and i.sub.d17. In accordance with the first embodiment of the present invention, currents i.sub.d16 and i.sub.d17 are of equal value and are typically identified by the letter "i". Using the notation "i" to represent currents i.sub.d16 and i.sub.d17, the current flowing through capacitor 13 has a value of "2*i" and the current flowing through compensation diode 12 has a value of "i." Accordingly, the transfer function for integrator 10 is given by equation 1 (EQT. 1) as:

where:

v.sub.o10 is the output voltage of integrator circuit 10;

.DELTA.V.sub.be15 is the small signal change in base-emitter voltage of transistor 15;

.DELTA.V.sub.be12 is the small signal voltage change of diode 12;

2*i is the small signal current;

s is a complex number representing a complex frequency; and

C.sub.13 is the capacitance value of capacitor 13.

EQT. 1 can be rewritten as equation 2 (EQT. 2):

where:

r.sub.e15 is the emitter resistance of transistor 15; and

r.sub.e12 is the emitter resistance of diode-connected transistor 12.

Because the emitter resistance of transistor 15 is half that of diode connected transistor 12, EQT. 2 can be written as equation 3 (EQT. 3):

Thus, compensation diode 12 provides an impedance that negates the emitter resistance of transistor 15. More particularly, transistor 11 and compensation diode 12 are biased such that the impedance of compensation diode 12 and the emitter resistance of transistor 15 in combination with the small signal current flowing through them cancel each other. Accordingly, the output signal is only a function of capacitor 13. It should be noted that the output signal of integrator 10 is inverting and has a gain roll-off having a slope of 20 dB/DEC. Thus, integrator circuit 10 is suitable for use in feedback applications.

Although feedback element 13 is shown as a capacitor, it should be noted that this is not a limitation of the present invention. Feedback element 13 may be a load impedance such as a resistor, a series combination of a resistor and a capacitor, or the like. Preferably, the impedance of feedback element 13 is not more than approximately 10 times the small signal resistance of transconductance amplifier 14.

FIG. 2 is a schematic diagram of another example of an integrator circuit 20 in accordance with the first embodiment of the present invention. It should be understood that the same reference numerals are used in the figures to denote the same elements. Integrator circuit 20 is similar to integrator circuit 10 of FIG. 1 except that a field effect transistor 21 serves as transconductance amplifier 11 and diode 23 is preferably formed from a diode connected field effect transistor. Thus, a gate of field effect transistor 21 serves as the control electrode of transconductance amplifier 11 and the drain and source serve as current conducting electrodes. The drain of transistor 21 is also coupled to the anode of compensation diode 23 through capacitor 13. A node 22 common to the second terminal of capacitor 53, the drain of transistor 21, and the first terminal of current source 18 serves as an output node or terminal at which an output signal V.sub.o20 appears. The transfer function for integrator circuit 20 is given by equation 4 (EQT. 4) as:

where:

v.sub.o20 is the output voltage of integrator circuit 20;

.DELTA.V.sub.ds21 is the small signal voltage change of the drain-source voltage of transistor 21;

.DELTA.V.sub.ds23 is the small signal voltage change of the voltage of diode 23;

2*i is the small signal current;

s is a complex number representing a complex frequency; and

C.sub.13 is the capacitance value of capacitor 13.

EQT. 4 can be rewritten as equation 5 (EQT. 4):

where:

r.sub.d21 is the emitter resistance of transistor 21; and

r.sub.d23 is the emitter resistance of diode-connected transistor 23.

Because the drain-source resistance of transistor 21 is half that of diode connected transistor 23, EQT. 5 can be written as equation 6 (EQT. 6):

It should be noted that similar to integrator circuit 10, the output of integrator circuit 20 is inverting and has a gain roll-off having a slope of 20 dB/DEC.

FIG. 3 is a schematic diagram of an integrator circuit 30 in accordance with a second embodiment of the present invention. Integrator circuit 30 includes a transconductance amplifier 11, a capacitor 13, a compensation diode 32, and a bias stage 14. It should be understood that the same reference numerals are used in the figures to denote the same elements. By way of example, transconductance amplifier 11 is comprised of an NPN bipolar transistor 15, wherein the base terminal of transistor 15 serves as a control electrode of transconductance amplifier 11 and the collector and emitter terminals of transistor 15 serve as the current carrying electrodes of transconductance amplifier 11. The emitter of transistor 15 is coupled for receiving a power supply voltage such as, for example, ground. The base terminal of transistor 15 is connected to the first terminal of capacitor 13. The second terminal of capacitor 13 is coupled to the collector terminal of transistor 15 via capacitor 13. In other words, a first terminal of capacitor 13 is connected to the base of transistor 15 and the second terminal of capacitor 13 is connected to the anode of compensation diode 32.

Input stage 14 includes current sources 16, 17, and 18. A first terminal of current source 16 is connected to the base terminal of transistor 15 and a second terminal of current source 16 is coupled for receiving a power supply voltage or source of operating potential such as, for example, ground. A first terminal of current source 17 is commonly connected to the first terminal of capacitor 13 and to the base terminal of transistor 15. A second terminal of current source 17 is coupled for receiving a power supply voltage or source of operating potential such as, for example, V.sub.cc. A first terminal of current source 18 is commonly connected to the second terminal of capacitor 13 and to the anode of diode-connected transistor 32. A second terminal of current source 18 is coupled for receiving a power supply voltage such as, for example, V.sub.cc. A node 34 formed by the connection of the collector terminal of transistor 15 and the anode of compensation diode 32 serves as an output node or terminal at which an output signal v.sub.o30 appears.

In operation, bias stage 14 provides bias or quiescent currents I.sub.16, I.sub.17, and I.sub.18 via current sources 16, 17, and 18, respectively. In addition, current sources 16 and 17 cooperate to provide differential small signal currents "i.sub.d16 " and "i.sub.d17 ", respectively. Preferably, bias currents I.sub.16 and I.sub.17 are of equal value. Accordingly, the emitter resistances of diode-connected transistor 32 and transistor 15 are the same. It should be noted that small signal currents "i.sub.d16 " and "i.sub.d17 " are differential currents that flow into node 35, which is an alternating current (ac) or virtual ground. Thus, the current flowing through capacitor 13 is the sum of the currents i.sub.d16 and i.sub.d17. In accordance with the second embodiment of the present invention, currents i.sub.d16 and i.sub.d17 are of equal value, thus the currents are also designated as having a value "i". Using the notation "i" to represent currents i.sub.d16 and i.sub.d17, the current flowing through capacitor 13 has a value of "2*i" and the current flowing through compensation diode 32 has a value of "2*i." Accordingly, the transfer function for integrator 10 is given by equation 7 (EQT. 7) as:

where:

v.sub.o30 is the output voltage of integrator circuit 30;

.DELTA.V.sub.bel4 is the small signal change in base-emitter voltage of transistor 15;

.DELTA.V.sub.be32 is the small signal change in voltage of diode 32;

2*i is the small signal current;

s is a complex number representing a complex frequency; and

C.sub.13 is the capacitance value of capacitor 13.

EQT. 7 can be rewritten as equation 8 (EQT. 8):

Because the emitter resistance of transistor 15 is the same as that of diode connected transistor 32 EQT. 8 can be written as equation 9 (EQT. 9) :

Thus, compensation diode 32 provides an impedance that negates the emitter resistance of transistor 34. More particularly, transistor 34 and compensation diode 32 are biased such that the impedance of compensation diode 32 and the emitter resistance of transistor 34, in combination with the small signal current flowing through them, cancel each other. Accordingly, the output signal is only a function of capacitor 13. It should be noted that the output signal of integrator 30 is inverting and has a gain roll-off having a slope of 20 dB/DEC. Thus, integrator circuit 30 is suitable for use in feedback applications.

Although feedback element 13 is shown as a capacitor, it should be noted that this is not a limitation of the present invention. Feedback element 13 may be a load impedance such as a resistor, a series combination of a resistor and a capacitor, or the like.

By now it should be appreciated that an integrated circuit and a method for providing a frequency compensated output signal have been provided. The integrated circuit is useful in integrators, operational amplifiers, etc. An advantage of the present invention is that it provides an increased range of integration in integrator circuit applications and an increased frequency range in amplifier applications.