US 5,751,033 AGrant

Frequency Converter Circuit Structure Having Two Sources

Issue Date:1998-05-12

•4 Claims

•5 Drawing Sheets

Abstract

A frequency converter has low noise figure and high conversion gain characteristics, and can drive directly a 50 Ohm load. In one embodiment, a dual-gate FET is employed that is composed of a first and second FET as the frequency mixing elements, and a third FET is connected in parallel to the first. The gate voltage of the first FET is set to be substantially equal to the pinch-off voltage in order to thereby ensure low noise figure. The second FET is set to a high g.sub.m, from which a frequency-converted signal is outputted. The gate bias of the third FET is set to provide a path for the current flowing through the second FET. As a result, the second FET can be set to a high g.sub.m regardless of the gate voltage of the first FET, in order to ensure high conversion gain.

Metadata

Assignee

NEC Corporation

Inventor

Tatsuya Miya

Application Information

Application Number:US 6769144

Filing Date:1996-07-08

Priority Date:1994-03-15

Art Unit:258

Classifications

IPC:

H01L 2980

Field of Search:

327455257113;298;355313;323;333365;287;401;270;206

Patent Drawings (5 sheets)

Description

Background of the Invention

1. Field of the Invention

The present invention relates to a frequency converter that employs a dual-gate FET as a frequency mixing element, and in particular to a frequency converter that handles signals in the microwave band.

2. Description of the Related Art

Dual-gate FETs have conventionally been used as frequency mixing elements in frequency converters (hereinafter abbreviated as "mixers"). FIG. 1 shows the composition of dual-gate FET mixer of the prior art. This mixer is made up of dual gate FET 5 for frequency mixing, matching circuit 6 for a RF frequency band, matching circuit 7 for a local frequency band, and matching circuit 8 for an IF frequency band. Here, the symbols G.sub.11, G.sub.12 D, and S labeling each terminal of dual-gate FET 5 denote the first gate, second gate, drain, and source, respectively. As shown in FIG. 1, an RF signal is supplied to the first gate by way of matching circuit 6, and a local signal is applied to the second gate by way of matching circuit 7. It is common for an IF signal to be derived from the drain by way of matching circuit 8. Frequency mixing is believed to be principally caused by the transconductance (hereinafter abbreviated as "g.sub.m ") of FET 5, as viewed from the first gate, modulated at a local frequency by a local signal applied to the second gate, with the modulated component thereof coupled with the RF signal voltage supplied to the first gate through the gate-source capacity. The magnitude of the IF component of the generated frequency-mixed components depends on the coefficient g.sub.1, for the fundamental oscillation of Fourier series, i.e., for k=1, wherein

and the greater g.sub.1, the greater the conversion gain from RF frequency toward IF frequency. In formula (1), k is a non-negative integer, and .SIGMA. is the sum from k=0 to k=.infin..

To make g.sub.1 greater, g.sub.m itself must be made greater, but when a dual-gate FET is actually employed as a mixer, it is normal in order to reduce noise figure to deeply bias the first gate of the mixer such that the drain current will be considerably smaller than the saturation drain current when the first gate is short-circuited to the source. In other words, the mixer is operated in such a state in which the current is reduced by applying to the first gate a voltage that is close to the cut-off voltage (hereinafter abbreviated as "V.sub.th ") of the FET. In FIG. 2, the dual-gate FET is represented as a serial connection of two FETs 11, 12, the circuit of FIG. 2 being equivalent to the dual-gate FET 5 of FIG. 1. In the following description, parts equivalent to FET11 of dual-gate FET 5 are referred to as the FET relating to the first gate, and parts equivalent to FET12 are referred to as the FET relating to the second gate. In the above-described dual-gate mixer of the prior art, g.sub.m is also lowered because the current is suppressed to a low level, and as a result, g.sub.1 is also reduced and conversion gain cannot be increased. In order to raise the value of g.sub.m at the operating point, it is also proposed to reduce the absolute value of the V.sub.th of the FET.

However, because FETs relating to the first and second gates of a prior art dual-gate FET have identical structures, the cut-off voltage V.sub.th relating to both gates is equal, and accordingly, when the absolute value of the cut-off voltage for the first gate is small, the absolute value of the V.sub.th for the second gate will also be small. As a result, there is the problem that when the second gate is driven by a local signal, which is normally strong, the cut-off period of the dual gate mixer lengthens due to the small absolute value of the cut-off voltage, imposing a limit on the increase of g.sub.1.

Directed to solving this problem, a dual-gate FET is disclosed in Japanese Patent Laid-open No. 289304 (1989) in which the dual-gate FET is formed so that the cut-off voltages V.sub.th for the first and second gates differ. FIGS. 3 and 4 show section views of the construction of the dual-gate FET disclosed in this patent publication. The FET shown in FIG. 3 is formed such that the concentration of impurities n.sub.2 in the active layer underlying the second gate is greater than that of impurities n.sub.1 in the active layer underlying the first gate. The FET shown in FIG. 4 is formed such that the active layer underlying the second gate is thicker than the active layer underlying the first gate. Thus, the above-described problem can be obviated by varying the injection conditions for the active layers underlying each gate so that the absolute value of the V.sub.th for the first gate is reduced in order to make g.sub.1 as great as possible, and that the absolute value of the V.sub.th for the second gate is increased. Although this prior art affords an increase in conversion gain, the increase of g.sub.1 is still limited even though the absolute value of the V.sub.th for the first gate is small, because the drain current itself is limited small by the first gate.

As described hereinabove, the current in a dual-gate FET mixer of the prior art is suppressed to a low level to reduce the noise figure. As a result, g.sub.m at the operating point is small and conversion gain cannot be made high. Although it is possible to increase g.sub.m by making the absolute value of V.sub.th of the FET small or, as shown by the prior art in the above-described patent application, by varying the injection conditions in the layer below each gate, there remains a limit to the increase of g.sub.m when these types of methods are employed. Furthermore, because the output current of a dual-gate FET mixer of the prior art is small, the load driving power is also small, and consequently, it has not been possible to connect a load of 50 .OMEGA. characteristic, for example, a 50 .OMEGA. coaxial cable directly to the output circuit of the mixer. As a result, when taking out an IF signal from the mixer, it has been necessary to connect an impedance matching circuit or an impedance converter to the output circuit to take out the IF signal.

The object of the present invention is to provide a frequency converter with a low noise figure having a high g.sub.m capable of driving a low-impedance load without an impedance matching circuit.

Summary of the Invention

To achieve the above-described object, the frequency converter of the present invention has a dual-gate FET as a frequency mixing element provided with a first gate that receives a first signal, a second gate that receives a second signal and a drain from which an IF signal is provided, said frequency converter also having a third FET that is connected in parallel to the first FET and that has a gate voltage biased such that a drain current flows which is substantially equal to the drain current of the second FET at the operating point thereof, with the first gate being biased to be substantially equal to the pinch off voltage, wherein the portion of the FET relating (operationally coupled) to the first gate is referred to as the first FET and the portion of the FET relating to the second gate is referred to as the second FET.

Thus, by connecting the third FET in parallel to the first FET to establish a current path from the second FET to the third FET, it becomes possible to set to a high value the transconductance, as seen from the first gate, of the frequency converter regardless of the value of the gate bias of the first FET. Consequently, even if the first gate is biased to be substantially equal to the pinch-off voltage to reduce the noise figure (hereinafter abbreviated as "NF") of a first signal, a high frequency conversion gain (high gain) for the first signal can be obtained by establishing the transconductance high at the operating point of the second FET. In this way, a frequency converter having low NF and high gain can be realized.

In the case that the dual-gate FET and the third FET are of depletion-type, it is desirable to set the bias voltage of the second gate such that the drain current at the operating point of the second FET is substantially (1/2) I.sub.DSS, wherein I.sub.DSS stands for the saturation drain current of the second FET at the time of gate-source short-circuit.

When depletion-type FETs are employed in the dual-gate FET and third FET, the biases of the FETs can easily be established, because it is possible to set the biases by using as a standard the saturation drain current I.sub.DSS produced by short-circuiting the gate and source of the second FET. When the drain current at the operating point of the second FET is set to (1/2) I.sub.DSS, the range of current clip narrows, thereby enabling the frequency conversion gain to be increased even when the second signal has a large amplitude.

In addition, it is desirable that the channel width of the third FET be substantially half the channel width of the second FET.

When I.sub.DSS of the second and third FETs is I.sub.DSS2 and I.sub.DSS3, respectively, and the channel width of the third FET is formed so as to be 1/2 the channel width of the second FET, I.sub.DSS3 =(1/2) I.sub.DSS2. On the other hand, if the gate bias of the first FET is set to the vicinity of the pinch-off voltage V.sub.th, the drain current I.sub.D1 of the first FET will decrease, and consequently the drain currents I.sub.D2 and I.sub.D3 of the second and third FETs will be substantially equal. Consequently, when the drain current at the operating point of the second FET is set to (1/2) I.sub.DSS2, the gate bias of the third FET must be set such that the saturation drain current of the third FET is (1/2) I.sub.DSS2 =I.sub.DSS3. This can easily be achieved by short-circuiting the gate and source of the third FET.

Further, the dual-gate FET and the third FET can be made self-biased. Through self-biasing, it is possible to have the frequency converter carry out the above-described operations automatically.

It is possible to connect a series resonance circuit having a resonance frequency equal to the frequency of the second signal between the second gate and a common potential, and output the frequency-converted signal from the drain of the second FET.

When a series resonance circuit is connected between the second gate and the common potential (ground terminal), the series resonance circuit both works as a filter of the second signal and has a low impedance for the frequency-converted output frequency. As a result, the second FET functions as an amplifier of the common gate drive (gate ground) for the output frequency, thereby increasing the frequency conversion gain.

It is preferable that the above-described frequency converter be constructed monolithically together with other semiconductor circuits.

Thus, according to the present invention, by deeply biasing the first gate so that a drain current flows which is considerably smaller than the saturation current at the time of gate-source short-circuit, the noise figure of the first FET can be reduced, and by causing the greater part of the drain current of the second FET to flow to the third FET, the second FET can be set to a high transconductance. In this way, a frequency converter having high conversion gain and low NF can be realized.

The above and other objects, features, and advantages of the present invention will become apparent from the following description referring to the accompanying drawings which illustrate examples of preferred embodiments of the present invention.

Brief Description of the Drawings

FIG. 1 shows a structural diagram of a dual-gate mixer of the prior art;

FIG. 2 shows a dual-gate FET represented as serially connected two FETs ;

FIG. 3 is a sectional view of the construction of an example of a dual-gate FET of the prior art;

FIG. 4 is a sectional view of the construction of an example of a dual-gate FET of the prior art;

FIG. 5 shows a circuit diagram of a first embodiment of the present invention;

FIG. 6 shows a circuit diagram of a second embodiment of the present invention;

FIG. 7 shows a circuit diagram of a third embodiment of the present invention;

FIG. 8 shows the FET structure of a frequency converter according to the present invention;

FIG. 9 shows the FET structure of a frequency converter according to the present invention;

FIG. 10 is a circuit diagram of a fourth embodiment of the present invention.

Detailed Description of the Preferred Embodiments

Explanation of the embodiments of the present invention will next be presented with reference to the figures. FIG. 5 is a circuit diagram of a first embodiment of the frequency converter of the present invention. This embodiment is an example of the application of the frequency converter of the present invention to an FM receiver.

The frequency converter is provided with FET 3 and dual-gate FET 4, both of which are depletion-type N-channel FETs. In the following explanation, the portion of dual-gate FET 4 having operationally to do with gate G.sub.1 is referred to as FET1, and the FET portion having operationally to do with gate G.sub.2 is referred to as FET2. Further, operation of each of these FETs in the saturation region with the gate and source being short-circuited is referred to as an I.sub.IDDS operation, and the saturation drain current in the I.sub.DSS operation is referred to as short-circuit saturation current I.sub.DSS.

In the present embodiment, the source of dual-gate FET 4, i.e., source S.sub.1 of FET1, is grounded, and the drain, i.e., drain D.sub.2 of FET2 is connected to power source V.sub.D by way of load resistance R.sub.L2. In addition, FET3 is connected in parallel with FET1, and the voltage of gate G3 is biased, via R.sub.G3, such that a drain current flows which is substantially equal to the drain current of FET2. Thus, by the addition of FET3, a current path from FET2 to FET3 is established, and the operating point of FET2 can be set to a high g.sub.m regardless of the gate bias, set by R.sub.G1, of FET1. As shown in FIG. 5, an RF signal is supplied to gate G1, and a local signal (local oscillator signal) is supplied to gate G.sub.2. An IF (intermediate frequency) signal is provided from drain D.sub.2. Gate bias V.sub.1, via R.sub.G1, of FET1 is set in the vicinity of the pinch-off voltage to reduce the noise figure. Gate bias V.sub.2, via R.sub.G2, of FET2 is set such that its drain current has an operating point in the vicinity of (1/2) I.sub.DSS2. Here, I.sub.DSS2 is the short-circuit saturation current of FET2. Gate bias V.sub.3, via R.sub.G3, of FET3 is set such that the drain bias current of FET3 has substantially the same magnitude as the drain bias current of FET2, (1/2) I.sub.DSS2.

In operation of the present embodiment, an RF signal is supplied to gate G.sub.1, and a local signal is supplied to gate G.sub.2. Since the gate bias V.sub.1 of gate G.sub.1 is set (by R.sub.G1) to the vicinity of the pinch-off voltage, FET1 is of low NF but its drain current is small. As a result, a drain current flows through FET3 which is nearly equal to the drain current of FET2. Normally, the local signal has a large amplitude. However, since the drain bias current of FET2 is set (by R.sub.L2) to (1/2) I.sub.DSS2, current clip occurs within a limited range and thus conversion gain increases.

As described above, in the present embodiment, drain current of FET2 is designed regardless of the gate bias V.sub.1 of FET1. Accordingly, g.sub.m of FET2 can be made high to cause a high conversion gain to be obtained. In the present embodiment, the channel widths of FET1, 2, and 3 are 200 .mu.m, V.sub.th is -1.0 V, V.sub.1 is set to between -0.5 and -0.8 V, V.sub.2 to between 1 and 3 V, and V.sub.3 to between 0.2 and 0.4 V. Through these settings, it is possible to realize a high-power frequency converter of low noise figure capable of driving a 50 .OMEGA. load without any impedance matching circuit.

FIG. 6 shows a circuit diagram of a second embodiment of the present invention. In this embodiment, the channel width of FET3 is substantially half that of FET2, and as in the embodiment of FIG. 5, gate bias V.sub.2 of FET2 is set (by R.sub.G2)such that the saturation drain current of FET2 is (1/2) I.sub.DSS2. The gate of FET3 is connected to the ground potential and the source thereof is also connected to the ground potential via a protecting resistor. Since substantially no current flows through the protection resistor, the gate and source are at equipotential. Accordingly, in the saturation region, a short-circuit saturation current I.sub.DSS3 equal to (1/2) I.sub.DSS2 flows through FET3. In this way, by merely placing the gate and source at equipotential, via R.sub.G3, the drain current characteristic of FET3 can be established such that the drain current (1/2) I.sub.DSS2 set in FET2 flows through FET3, whereby the circuit shown in FIG. 6 can achieve the same effect as the circuit shown in FIG. 5.

FIG. 7 shows a circuit diagram of a third embodiment of the present invention. In this embodiment, a resistance and a capacitor (labeled R2.sub.GS1, C.sub.GS1, and R2.sub.GS3, C.sub.GS3), connected in parallel are connected between the ground and each of the sources of FET1 and FET3 to provide self-biases. The self-biasing circuit of FET1 generates a bias voltage to place the gate-source voltage of FET1 in the vicinity of the pinch-off voltage. The self-biasing circuit of FET3 generates a bias voltage to make the saturation drain current of FET3 equal to the drain current of FET2.

FIGS. 8 and 9 illustrate the FET structure of a dual-gate FET frequency converter according to the present invention. The FETs of FIGS. 8 and 9 are identical in terms of equivalent circuits, but the FET of FIG. 9 differs from the FET of FIG. 8 in that drain and source electrodes are provided for each of the FETs relating to each gate of FIG. 8, each of the FETs of FIG. 9 thereby being structured as independent FETS.

FIG. 10 shows a circuit diagram of a fourth embodiment of the present invention. This embodiment is a frequency converter in which the gate circuit of FET2 of FIG. 5 is provided with a series resonance circuit (shown in FIG. 10 by the RLC circuit of R.sub.G2, L.sub.G2, and C.sub.G2). Each gate bias of the FETs making up the frequency converter of the present embodiment is set similarly to the circuit of FIG. 5. The resonance frequency of the series resonance circuit is equal to the frequency of the local signal, and this resonance circuit functions on one hand as a filter for the local signal, and on the other hand, as the low impedance for the IF signal. Accordingly, FET2 acts as an amplifier of the gate ground connection for an IF signal. As a result, a higher gain can be obtained in the frequency converter of FIG. 10 than in the frequency converter of FIG. 5.

The present invention may be summarized as follows:

1) By parallel connecting the third FET to the first FET, a second FET that outputs a frequency-converted signal can be set to high g.sub.m regardless of the gate bias of the first FET, and as a result, a frequency converter having large frequency conversion gain can be realized. Because the second FET can operate at a high g.sub.m, a relatively large current can flow through the second FET, by which the frequency converter can directly drive a 50 .OMEGA. load, thereby providing a greater degree of freedom in the design of the peripheral circuits of the frequency converter.

2) By setting the gate bias of a first FET to the vicinity of the pinch-off voltage, low noise figure can be achieved without losing high-gain frequency conversion characteristics.

3) By setting the operating point of the drain current of a second FET to 1/2 the short-circuit saturation current of that FET, the range of current clip can be limited even when the amplitude of the second signal supplied to the gate of the second FET is large, thereby enabling an increase in conversion gain.

4) By making the channel width of a third FET one half the channel width of a second FET, the effect described in item 3 above can be achieved by merely short-circuiting the gate and source of the third FET.

5) By self-biasing gate voltage, the effects described in items 1 to 4 above may be achieved without necessitating complicated processes.

6) By providing between the gate of the second FET and a common potential a series resonance circuit having a resonance frequency equal to the frequency of the second signal, the second FET can be made to function as an amplifier of the common gate connection for the frequency-converted IF signal, thereby enabling an increase in frequency conversion gain.

7) Monolithically forming the frequency converter together with other circuits facilitates both the setting of gate biases and the design of the frequency converter as well as of peripheral circuits.

It is to be understood, however, that although the characteristics and advantages of the present invention have been set forth in the foregoing description, the disclosure is illustrative only, and changes may be made in the arrangement of the parts within the scope of the appended claims.

Claims

What is claimed is:

1. A frequency converting circuit for high conversion gain comprising as a frequency mixing element, a first FET provided with a first, a second, and a third gate, said first FET having first and second sources which are aligned with each other and also having a drain, the first and second sources of said first FET being formed in parallel to said drain; and first and third gates being aligned with each other, the second gate being formed along one straight line and the first and third gates being formed along another straight line, said straight lines being located between and parallel to said drain and said sources, said one straight line being on the drain side of said straight lines and extending over a whole width of said drain, and said other line being on the source side of said straight lines so that said first gate controls a drain current which flows between said drain and said first source and also so that said third gate controls a drain current which flows between said drain and said second source; and said first FET also having a diffusion region formed between said second gate, and said first and third gates, so that said diffusion region acts as a source of a second FET which comprises the drain of said first FET, the second gate and the diffusion region acting as drains of both said first FET and a third FET which comprises the diffusion region, the first and third gates, and the first and second sources of the first FET, respectively; wherein said first gate is biased to be substantially equal to a pinch-off voltage and said third gate is biased so that a major part of a drain current of the first FET passes through the third FET.

2. A frequency converting circuit according to claim 1, wherein the channel widths of said first, second and third gates are equal.

3. A frequency converting circuit for high conversion gain having, as a frequency mixing element, a FET provided with a first, a second, and a third gate, said FET having first and second sources which are aligned in a line and a drain, the aligned sources of said FET being formed in parallel to said drain; and said first and third gates being aligned in a line and said second gate and the aligned first and third gates being formed along two straight lines located between and parallel to said drain and said sources, the second gate being formed along a first line on the drain side of said two straight lines extending over a whole width of said drain, and the first and third gates being formed along a second line on the source side of said two straight lines so that said first gate controls and a drain current which flows between said drain and said first source and that said third gate controls a drain current which flows between said drain and said second source; wherein said first gate is biased to be substantially equal to a pinch-off voltage and said third gate is biased so that major part of a drain current, which flows from the drain of said FET, flows to said second source.

4. A frequency converting circuit according to claim 3, wherein the channel widths of said first, second and third gates are equal.

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Abstract

Description