US 5,748,554 AGrant
Memory and Method for Sensing Sub-Groups of Memory Elements
Issue Date:1998-05-05
•30 Claims
•8 Drawing Sheets
Abstract
A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
Metadata
Assignee
- Rambus, Inc.
Inventors
- Richard M. Barth
- Donald C. Stark
- Lawrence Lai
- Wayne S. Richardson
Application Information
Application Number:US 7713037
Filing Date:1996-12-20
Priority Date:1996-12-20
Art Unit:251
Classifications
IPC:
B11C 1300
Field of Search:
365181.01;230.03;230.05;230.08;230.06
Patent Drawings (8 sheets)
Description
Field of the Invention
The present invention pertains to the field of computer memories. More specifically, the present invention relates to sub-word line access in computer memories.
Background of the Invention
Memory cells are typically physically and logically oriented in rows and columns, and share word lines and bit lines, respectively. In a dynamic random access memory, for example, a memory cell consists of a transistor and a capacitor connected to a bit line and a word line. The word line selects a memory cell. The bit line is what connects the memory cell to the sense amplifier to transfer data.
This is illustrated in the simplified diagram of FIG. 1a. Referring to FIG. 1a, a word line metal 110, is coupled to word line gate polysilicon 115 which runs in parallel with word line metal 110. Metal-polysilicon straps 120 are periodically added to reduce resistance. When the word line metal 110 is activated, word line gate polysilicon 115 is activated and enables the sense amplifiers 125 to sense or restore data to/from the coupled memory cells (not shown). The operations performed by sense amplifiers 125 are controlled by control signals 127, 129.
FIG. 1b illustrates a dual word line example. In this example, word line metal 110 is selectively connected to one of two word line gate polysilicon 117, 119 through AND gates 130, 135. Typically the AND gates are placed at intervals along the word lines and 110, gate polysilicon 117, 119 corresponding to locations of word line straps. Select signals 140, 145, which are complementary signals, are input to the AND gates 130, 135 to select the word line gate polysilicon to couple to the word line metal.
Some manufacturers have encountered performance problems utilizing longer word line lengths. This is due to increased capacitance and resistance. To minimize longer word line lengths effects, the word line polysilicon is broken up into a plurality of segments. When the word line metal is activated, all of the segments are activated, effectively activating the entire word line polysilicon composed of the segments.
All of these circuits require that the entire word line gate polysilicon associated with a particular row of memory cells be raised, even if only a small portion of the row of memory cells required access. In addition, the entire column of sense amplifiers is activated to perform the memory operation. For example, if a read operation is performed with respect to a subset of a row of memory cells, the entire word line gate polysilicon associated with a particular row of memory cells and the entire column of sense amplifiers are activated to transfer the data of the entire row to the sense amplifiers. It follows that a restore operation on the entire row is subsequently required.
One disadvantage associated with the this approach is that a significant amount of power is required to bring an entire row of information into the sense amplifiers. Another disadvantage associated with this approach is that the sense amplifiers can only store data from one row of memory cells at a time. Therefore, data that was placed there before will need to be flushed even if that particular data is required immediately afterwards.
Summary of the Invention
It is one object of the present invention to provide a memory in which power efficient memory accesses can be performed.
It is an object of the present invention to provide for sub-word memory accesses.
It is another object of the invention to provide for a memory in which sets of sense amplifiers corresponding to different sub-words of rows of memory can communicate data to different rows of the memory.
A memory design and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group. The sub-word lines are further coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power.
In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
Brief Description of the Drawings
The present invention is illustrated by way of example and not imitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
FIG. 1a is a prior art block diagram of a dynamic random access memory (DRAM) illustrating one example of word line connections and FIG. 1b is a prior art block diagram of a DRAM illustrating a dual word line connection.
FIG. 2 is a simplified block diagram of one embodiment of a DRAM in accordance with the teachings of the present invention.
FIG. 3 illustrates a block diagram of one embodiment of a portion of a DRAM that operates in accordance with the teachings of the present invention.
FIG. 4 illustrates one embodiment of a sub-group of memory cells and associated circuitry.
FIG. 5 illustrates an alternate embodiment of a sub-group of memory cells and associated circuitry.
FIG. 6a is a state diagram illustrating one embodiment of a process for accessing memory cells of the DRAM and FIG. 6b is a state diagram illustrating an alternate embodiment of a process for access memory cells of the DRAM.
FIG. 7 is a diagram illustrating the states of sense amplifiers after processing requests.
Detailed Description
The apparatus and method of the present invention provides for an innovative memory structure and method for accessing the memory cells contained therein. In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention unnecessarily.
Although the present invention is described with respect to dynamic random access memory (DRAM), it is apparent to one skilled in the art that the invention is readily applicable to other memories including static memories and electrically programmable memories (e.g. EPROMS).
The invention describes sub-group accessing of memory cells from the array. A group can be defined as a bank of memory cells. As is readily apparent to one skilled in the art, a group also can be defined to a subset or a superset of a bank of memory cells. In addition, the present invention is described with respect to memory of a determined size and the number of control signals and lines are correspondingly allocated. It is readily apparent that the present invention is not limited to a memory of a particular size and the number of control signals and lines can be varied to accommodate the size of the memory.
FIG. 2 is a simplified block diagram of one embodiment of the DRAM of the present invention. FIG. 2 illustrates a dual word line structure that includes word line metal 205 and word line gate polysilicon zero (GP0) and one (GP1). Word lines GP0 and GP1 are each broken up into unconnected segments, each approximately spanning the distance of a sub-group of memory cells. For example, referring to FIG. 2, word line GP0 is broken up into segments 255, 260, 265, 270 and word line GP1 is broken up into segments 210, 215, 220, 225, each segment capable of being separately enabled using control signals sel 0.3-0.1, 1.3-1.0!.
Furthermore, the DRAM includes logic that enables a corresponding subset of the sense amplifiers in order to perform a memory operation. In particular, the SAP and SAN signals are expanded to be multiple bits, e.g., SUBSAP 3:0!, SUBSAN 3:0!, in order to address specific subsets of sense amplifiers of the column of sense amplifiers 260. These signals can be routed separately from top to bottom, or generated in the area near the subset (e.g., in the strap areas) from a master signal. Area penalty is minimal as the width of the areas and size of the drivers need only be one fourth of the original width and size. Thus, the word line segments and corresponding subsets of sense amplifiers are selectively enabled to perform memory access for a sub-group of a row of memory cells. It can readily be understood that substantial power savings are achieved as only a fraction of the sense amplifiers and a corresponding fraction of the word line gate polysilicon are activated. As is readily apparent, use of SUBSAP and SUBSAN control signals are exemplary; different control signals can be used for different memories and differents types of DRAMS.
FIG. 3 is a slightly more detailed block diagram of a DRAM constructed in accordance with the teachings of the present invention. It is apparent to one skilled in the art, numerous details not distinctive to the teachings of the present invention are omitted for purpose of explanation.
Furthermore, certain control logic is shown in functional block form; it is readily apparent that a variety of implementations can be used to perform the function described.
Referring to FIG. 3, the DRAM 114 includes a memory array, or portion thereof, 350 sense amplifier circuitry 360 row decoder circuitry 311, column decoder circuitry 371 and controller 118.
In the present embodiment, the controller 118 receives control signals from memory controller 117, including signals to indicate that sub-group sensing is to be performed. For example, in one embodiment, the memory controller 117 issues signal SUBACT, to indicate that sub-group sensing is to be performed and SADR3:0! which identifies the sub-group(s) to be sensed.
As is readily apparent to one skilled in the art, the present invention is not limited to these specific control signals or the structure of the memory controller 117 issuing certain signals to controller 118. A variety of embodiments, in which different embodiments of signals including signals that may be issued by a processor (not shown) coupled to the memory controller 117 or memory 114 is contemplated. Furthermore, embodiments which do not include on chip controller circuitry also are contemplated.
Continuing with the present embodiment, the controller 118 issues control signals to selectively activate a word line segment (e.g., segments 365, 366, 367, 368) and corresponding sub-group of the sense amplifier (e.g., sub groups 361, 362, 363, 364). For example, to perform a memory access operation with respect to one sub-group of memory cells, delineated by area 352, controller 118 issues an activation signal on line 119. Thus, when row decoder 311 selects a corresponding word line metal to activate, for example, word line metal 305, the controller 118 activates line 119 such that gate 321 activates word segment 366. In addition, controller 118 issues SUBSAP, SUBSAN signals to activate the corresponding portion 362 of sense amplifier circuitry 360.
FIG. 4 is a slightly more detailed diagram of one sub-group 352 of the memory that is individually accessible in accordance with the teachings of the present invention. This embodiment, illustrative of a single or conventional word line access, selects a sub-group of the memory array represented by cells 401, 402, 403. Activation of word line segment 367 by activation of the sub word line select signal 119 by controller 118 and word line metal 305 causes the data to be available on the bitlines represented by lines 315, 316 and 317. The controller issues the appropriate SUBSAP3:0! and SUBSAN 3:0! to select the corresponding portion 362 of sense amplifier circuitry to perform the desired operation (e.g., sense). FIG. 5 is illustrative of an embodiment which utilizes a dual word line structure. As is readily apparent to one skilled in the art, sub-group access can be applied to different memory access structures to improve the efficiency of access.
The architecture of memory array therefore allows a sub-group of memory cells to be sensed during a row operation. Thus, when only a portion of a row of memory cells needs to be accessed, only the corresponding word line section and sub-group of sense amplifiers designated to sense those memory cells are activated. By turning on only the necessary circuitry required for sensing requested data, power consumption is reduced.
In an alternate embodiment, the structure for sensing sub-groups of rows of memory cells can be configured to concurrently access sub-groups of cells from different rows of the memory. In this embodiment, the row decoder circuitry would be modified to activate more from one word line metal at a time. The control signals issued to control the selection of sections of the word lines and corresponding sub-groups of the sense amplifiers would also be modified correspondingly. Additional control logic would be required to ensure that only the sub-group associated with the desired row is sensed. For example, in one approach, additional control signals are issued by controller 118, each control signal separately connected to a different segment in a different row. Alternately, a row/segment control signal is issued and the gate (e.g., 320-331, FIG. 3) is expanded to include logic to decode the row/segment control signal to activate the specified segment in the particular row.
It will be appreciated that the memory architecture of the present invention may be implemented for pulse word line sensing and level word line sensing operations. For a memory that implements level word line sensing, where the word line remains activated after a sense cycle and restore cycle, subsequent writes to the sense amplifier circuitry will update both the sense amplifier circuitry and the memory cells selected by the word line. In a memory that implements pulse word line sensing where the word line deactivates after a sense and restore cycle, an explicit restore cycle is executed before retiring a row when the data in the sense amplifier circuitry has been updated by an earlier write (e.g., by a CAS write). This is desirable as updates done to the sense amplifiers are not updated in the memory cells.
FIG. 6a shows one embodiment of the state transitions that occur for a level word line memory. If a row already is in the sensed state, bringing in a new row requires as executing a precharge followed by a sense and a restore. As is well known in the art, the term precharge refers to the process of turning off the sense amplifiers and setting all the bit lines to Vdd/2. All information that was in the sense amplifiers is lost; new data can then be placed in the sense amplifiers. The term sense refers to the process of activating the selected word line or section of a word line, activating the corresponding sense amplifiers and latching the data into the sense amplifiers. Since the transfer of data from the memory cells to the sense amplifiers is a destructive read, a restore operation is needed to write the data from the sense amplifiers back to the memory cells. The term restore therefore refers to an implicit, automatic restore operation that occurs after the sense operation. After the restore, CAS read and write operations can be executed to that row or a portion of that row. In this implementation, all writes are updated in both the sense amplifiers and the memory cells and the sense amplifiers can be turned off at any time using a precharge operation without any ill effects.
FIG. 6b illustrates one embodiment of a state transition diagram for pulsed word line operation. This process utilizes an explicit restore state in which a word line or segment of a word line is activated and data is transferred from the sense amplifiers back to the memory cells selected by the word line. The explicit restore state is performed prior to a precharge if the sense amplifiers have been updated via a CAS write (i.e., the sense amplifier are dirty). This action activates the word line and updates the memory cells associated with the row currently sensed. If the sense amplifiers have not been updated via a CAS write (i.e., the sense amplifiers are clean), then the precharge operation can occur without executing an explicit restore cycle.
The utilization of level word line sensing and pulse word line sensing will now be discussed. Without adding circuitry to enable multiple word line activation, one way of implementing subwordline sensing using a level word line implementation would be to turn off all sense amplifiers before bringing in a new row (with 1 to 4 sections activated). Data can also be brought from multiple word lines. This is illustrated by the following example. Assume a simple case in which a memory core includes a single bank of memory cells. Each bank consists of 1024 rows and each row contains 2048 bits coupled to 2048 sense amplifiers. Each word line is subdivided into 4 sub-groups, each controlling 512 sense amplifiers.
Assume an initial state that the sense amplifiers are turned on, but the data contained in the sense amplifiers is clean. The example includes the processing of the following three requests:
Request 1: Bring in row 100, sections 1 and 2
Request 2: Bring in row 200, sections 2 and 3
Request 3: Bring in row 300, sections 3 and 4
In a level word line implementation, the following events would happen in response to the requests:
Request 1: Precharge Turn off the sense amplifiers in sections 1 and 2. Set bitlines in sections 1 and 2 to Vdd/2.
Sense Turn on word line 100 polysilicon for sections 1 and 2. Latch data onto sense amplifiers in sections 1 and 2.
Restore Drive sense amplifiers data back to word line 100 and polysilicon for sections 1 and 2.
Request 2: Precharge Turn off the sense amplifiers in sections 2 and 3 Set bitlines in sections 2 and 3 to Vdd/2. Release word line 100 polysilicon for section 2
Sense Turn on word line 200 polysilicon for sections 2 and 3. Latch data onto sense amplifier sub-groups 2 and 3
Restore Drive sense amplifier data back to word line 200 and polysilicon for sections 2 and 3
Request 3: Precharge Turn off the sense amplifiers in sections 3 and 4. Set bitlines in sections 3 and 4 to Vdd/2. Release word line 200 polysilicon for section 3.
Sense Turn on word line 300 polysilicon for sections 3 and 4. Latch data onto sense amplifier sections 3 and 4.
Restore Drive sense amp data back to word line 300 and word line polysilicon for sections 3 and 4.
FIG. 7 illustrates the state of the sense amplifiers after processing Requests 1, 2 and 3 for level word line sensing implementation described above and the pulse word line implementation described below.
In the pulse word line implementation, the following events would happen in response to the requests:
Request 1: Precharge Turn off the sense amplifiers in sections 1 and 2. Set bitlines in sections 1 and 2 to Vdd/2.
Sense Turn on word line 100 polysilicon for sections 1 and 2. Latch data onto sense amplifiers in sections 1 and 2.
Restore Drive sense amplifier data back to word line 100 and polysilicon for sections 1 and 2.
Request 2: Explicit An explicit restore would be performed on Restore word line 100 polysilicon for section 2 (if necessary)
Precharge Turn off the sense amplifiers in sections 2 and 3 Set bitlines in sections 2 and 3 to Vdd/2.
Sense Turn on word line 200 polycide for sections 2 and 3. Latch data onto sense amplifiers 2 and 3
Restore Drive sense amplifier data back to word line 200 and polycides for sections 2 and 3
Request 3: Explicit An explicit restore would be performed on Restore word line 100 polycide for section 3 (if necessary)
Precharge Turn off the sense amplifiers in sections 3 and 4. Set bitlines in sections 3 and 4 to Vdd/2.
Sense Turn on word line 300 polysilicon for sections 3 and 4. Latch data onto sense amplifier sections 3 and 4.
Restore Drive sense amplifier data back to word line 300 and polysilicon for sections 3 and 4.
It should be noted that explicit restores are not always required. For example, if the data were not changed (i.e., the sense amplifiers were not written to or "clean"), an explicit restore is not necessary. An explicit restore is needed after a sense amplifier has been written to or "dirty".
Furthermore, in this implementation, the controller in the memory would maintain a memory address tag to determine whether the address indicated in a request matches the address of data in the sense amplifier, a valid bit tag to determine whether data in the sense amplifiers is valid, and a dirty bit tag to determine whether the sense amplifiers are dirty for each subwordline section. These tags are used to determine whether or not a subwordline section has been made dirty and if so, which row address to explicitly restore it to.
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims
What is claimed is:
1. A memory comprising: a memory array of storage locations; a plurality of word lines for selecting rows of the memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line; a plurality of sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers selectively coupled to one storage location associated with the word line, each set of sense amplifiers corresponding to a segment; a first select logic for selecting at least one segment of a word line during a sense operation; and a second select logic for selecting at least one corresponding set of sense amplifiers.
2. The memory as set forth in claim 1, wherein the memory is located on a component and the first select logic comprises a controller located on the component.
3. The memory as set forth in claim 1, wherein the memory is located on a component and the second select logic comprises a controller located on the component.
4. The memory as set forth in claim 1, wherein the first select logic issues a select signal to a gate having as inputs the select signal and a row signal indicative that the row is selected, the output of the gate activating the selected segment when the select signal and the row signal are active.
5. The memory as set forth in claim 1, wherein the memory further comprises a plurality of gates, an output of each gate coupled to selectively activate a segment, each gate receiving as input a row signal indicative that a row is selected and a select signal indicative that a segment is selected.
6. The memory as set forth in claim 1, wherein the first select logic comprises a controller which issues a first select signal and a plurality of decoders each coupled to receive the first select signal and selectively activate a segment when row decode logic indicates that the corresponding row is selected.
7. The memory as set forth in claim 1, wherein the second select logic issues the following signals: SUBSAP3:0! and SUBSAN 3:0! wherein the bits set indicate the set of sense amplifiers that is to be activated.
8. A method for accessing a memory comprising a plurality of storage locations, said method comprising the steps of: providing a plurality of word lines for selecting rows of a memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line; identifying sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers coupled to one storage location associated with a word line, each set of sense amplifiers corresponding to a segment; selecting at least one segment of a word line that is to be activated during a sense operation; and selecting at least one corresponding set of sense amplifiers.
9. The method as set forth in claim 8, wherein the set of selecting a segment comprises the steps of: issuing a segment select signal to identify a segment to be selected; issuing a row select signal to identify a row to be selected; selecting a particular segment in a particular row based on the segment select signal and row select signal issued.
10. The method as set forth in claim 8, wherein the step of selecting a corresponding set of sense amplifiers comprises the step of issuing a set select signal to select a set of sense amplifiers.
11. The method as set forth in claim 8, wherein the access performed is a read operation, said method further comprising the steps of: sensing the data of the selected segment, said sense operation placing the data in the corresponding set of sense amplifiers; restoring the data to the selected segment; and performing a column address strobe (CAS) wherein the data in the corresponding set of sense amplifiers is output from the memory.
12. The method as set forth in claim 11, further comprising the step of precharging the sense amplifiers prior to performing the step of sensing the data.
13. The method as set forth in claim 8, wherein the access performed is a write operation, said method further comprising the steps of: performing a level word line access, wherein the selected segment remains activated until another segment is selected; and performing a column address strobe (CAS) wherein data to be written is latched into the corresponding set of sense amplifiers, said CAS causing the data to further be stored in storage locations coupled to the selected segment.
14. The method as set forth in claim 8, wherein the access performed is a write operation, said method further comprising the steps of: performing a pulse word line access, wherein the selected segment is activated prior to performing a sense cycle and restore cycle and deactivated after completion of the restore cycle; performing a column address strobe (CAS) wherein data to be written is latched into the corresponding set of sense amplifiers; and performing an explicit restore operation thereby causing the data located in the corresponding set of sense amplifiers to be stored in storage locations coupled to the selected segment.
15. A memory comprising: a plurality of word lines for selecting a row of a memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line; a plurality of sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers selectively coupled to one storage location associated with a word line, each set of sense amplifiers corresponding to a segment; a first select logic for selecting during a sense operation at least one segment from a first word line and at least one segment from a second word line; and a second select logic for selecting corresponding sets of sense amplifiers to access storage locations along the first segment and the second segment.
16. The memory as set forth in claim 15, wherein the memory is located on a component and the first select logic comprises a controller located on the component.
17. The memory as set forth in claim 15, wherein the memory is located on a component and the second select logic comprises a controller located on the component.
18. The memory as set forth in claim 15, wherein the first select logic issues a first select signal to a first gate and a second select signal to a second gate, the first gate and second gate further respectively receiving as input a first row signal and second row signal indicative that the first row and second row, respectively, are selected, the output of the first gate activating the first selected segment when the first select signal and the first row signal are active and the output of the second gate activating the second selected segment when the second select signal and the second row signal are active.
19. The memory as set forth in claim 15, wherein the memory further comprises a plurality of gates, an output of each gate coupled to selectively activate a segment of a row, each gate receiving as input a row signal indicative that a row is selected and a select signal to indicate selection of a segment in a particular row.
20. The memory as set forth in claim 15, wherein the first select logic comprises a controller which issues a first select signal and a plurality of decoders each coupled to receive the first select signal and selectively activate a coupled segment when row decode logic indicates that the corresponding row is selected.
21. The memory as set forth in claim 15, wherein the second select logic issues the following signals: SUBSAP3:0! and SUBSAN 3:0! wherein the bits set indicate the set of sense amplifiers that is to be activated.
22. A method for accessing a memory comprising a plurality of storage locations, said method comprising the steps of: providing a plurality of word lines for selecting rows of a memory array, each word line comprising a plurality of segments, each segment spanning a portion of the distance of the word line; identifying sets of sense amplifiers, each sense amplifier of the sets of sense amplifiers coupled to one storage location associated with a word line, each set of sense amplifiers corresponding to a segment; selecting at least one segment of a first word line to activate during a sense operation; selecting at least one segment of a second word line that is to be activated during a sense operation; and selecting sets of sense amplifiers corresponding to the at least one segment of the first word line and at least one segment of the second word line to access storage locations along the first segment and the second segment.
23. The method as set forth in claim 22, wherein: the step of selecting at least one segment of a first word line comprises the steps of issuing a first select signal; and the step of selecting at least one segment of a second word line comprises the step of issuing a second select signal.
24. The method as set forth in claim 22, further comprising the step of issuing a select signal that identifies at least one segment of at least one row to be selected; wherein the steps of selecting at least one segment of a first word line and at least one segment of a second word line comprise decoding the select signal to determine the segments to select.
25. The method as set forth in claim 22, wherein the step of selecting sets of sense amplifiers comprises the step of issuing the following signals: SUBSAP3:0! and SUBSAN 3:0! wherein the bits set indicate the set of sense amplifiers to activate.
26. The method as set forth in claim 22 wherein the access performed is a read operation, said method further comprising the steps of: sensing the data of the selected segments, said sense operation placing the data in the corresponding set of sense amplifiers; restoring the data to the selected segments; and performing a column address strobe (CAS) wherein the data in the corresponding sets of sense amplifiers are output from the memory.
27. The method as set forth in claim 26, further comprising the step of precharging the sense amplifiers prior to performing the step of sensing the data.
28. The method as set forth in claim 22, wherein the access performed is a write operation, said method further comprising the steps of: performing a level word line access, wherein the selected segments remains activated until another segment is selected; and performing a column address strobe (CAS) wherein data to be written are latched into the corresponding sets of sense amplifiers, said CAS causing the data to further be stored in storage locations coupled to the selected segments.
29. The method as set forth in claim 22, wherein the access performed is a write operation, said method further comprising the steps of: performing a pulse word line access, wherein the selected segments are activated prior to performing a sense cycle and restore cycle and deactivated after completion of the restore cycle; performing a column address strobe (CAS) wherein data to be written is latched into the corresponding sets of sense amplifiers; and performing an explicit restore operation thereby causing the data located in the corresponding sets of sense amplifiers to be stored in storage locations coupled to the selected segments.
30. The method as set forth in claim 22, wherein the access performed is a write operation, said method further comprising the steps of: performing a pulse word line access, wherein the selected segments are activated prior to performing a sense cycle and restore cycle and deactivated after completion of the restore cycle; performing a column address strobe (CAS) wherein data to be written is latched into the corresponding sets of sense amplifiers; performing an explicit restore operation with respect to the first segment thereby causing the data located in the corresponding set of sense amplifiers to be stored in storage locations coupled to the first segment; and performing an explicit restore operation with respect to the the second segment thereby causing the data located in the corresponding set of sense amplifiers to be stored in storage locations coupled to the second segment .
Patent Citations (54)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4377855 | 1983-03-01 | Lavi | |
| US4542483 | 1985-09-01 | Procyk | |
| US4569036 | 1986-02-01 | Fuji et al. | |
| US4646268 | 1987-02-01 | Kuno | |
| US4698788 | 1987-10-01 | Flannagan et al. | |
| US4700328 | 1987-10-01 | Burghard | |
| US4710902 | 1987-12-01 | Pelley, III et al. | |
| US4730275 | 1988-03-01 | Baskett | |
| US4740921 | 1988-04-01 | Lewandowski et al. | |
| US4758993 | 1988-07-01 | Takamae | |
| US4787858 | 1988-11-01 | Killian, Jr. | |
| US4796230 | 1989-01-01 | Young | |
| US4800525 | 1989-01-01 | Shah et al. | |
| US4811302 | 1989-03-01 | Koishi | |
| US4825413 | 1989-04-01 | Tran | |
| US4837743 | 1989-06-01 | Chiu et al. | |
| US4843264 | 1989-06-01 | Galbraith | |
| US4862421 | 1989-08-01 | Tran | |
| US4888732 | 1989-12-01 | Inoue et al. | |
| US4903344 | 1990-02-01 | Inoue | |
| US4961168 | 1990-10-01 | Tran | |
| US4982370 | 1991-01-01 | Matsumoto et al. | |
| US4984196 | 1991-01-01 | Tran et al. | |
| US4991141 | 1991-02-01 | Tran | |
| US5046050 | 1991-09-01 | Kertis | |
| US5093806 | 1992-03-01 | Tran | |
| US5111434 | 1992-05-01 | Cho | |
| US5119340 | 1992-06-01 | Slemmer | |
| US5121358 | 1992-06-01 | Slemmer et al. | |
| US5124610 | 1992-06-01 | Conley et al. | |
| US5124951 | 1992-06-01 | Slemmer et al. | |
| US5128897 | 1992-07-01 | McClure | |
| US5132931 | 1992-07-01 | Koker | |
| US5181205 | 1993-01-01 | Kertis | |
| US5193072 | 1993-03-01 | Frenkil et al. | |
| US5214610 | 1993-05-01 | Houston | |
| US5241503 | 1993-08-01 | Cheng | |
| US5249165 | 1993-09-01 | Toda | |
| US5251178 | 1993-10-01 | Childers | |
| US5263002 | 1993-11-01 | Suzuki et al. | |
| US5267215 | 1993-11-01 | Tsujimoto | |
| US5274596 | 1993-12-01 | Watanabe | |
| US5291444 | 1994-03-01 | Scott et al. | |
| US5305280 | 1994-04-01 | Hayano | |
| US5321646 | 1994-06-01 | Tomishima et al. | |
| US5337283 | 1994-08-01 | Ishikawa | |
| US5343438 | 1994-08-01 | Choi et al. | |
| US5383159 | 1995-01-01 | Kubota | |
| US5390308 | 1995-02-01 | Ware et al. | |
| US5414662 | 1995-05-01 | Foss et al. | |
| US5418737 | 1995-05-01 | Tran | |
| US5455802 | 1995-10-01 | McClure | |
| US5471425 | 1995-11-01 | Yumitori et al. | |
| US5485430 | 1996-01-01 | McClure |
Non-Patent Literature (12)
- SP 23.1: A 60ns 1 Mb Nonvolatile Ferroelectric Memory with Non-Driven Cell Plate Line Write/Read Scheme, IEEE International Solid-State Circuits Conference, 1996, pp. 368-369.
- SP 23.2: A 1MB, 100MHz Integrated L2 Cache Memory with 128b Interface and ECC Protection, IEEE International Solid-State Circuits Conference, 1996, pp. 370-371.
- SP 23.5: A 16.GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture, IEEE International Solid-State Circuits Conference, 1996, pp. 376-377.
- SP 23.4: A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay, IEEE International Solid-State Circuits Conference, 1996, pp. 374-375, 300-301, 480.
- SP 23.6 A 32-Bank 1 Gb DRAM with 1GB/s Bandwidth, IEEE International Solid-State Circuits Conference, 1996, pp. 378-379, 304-305, 481-482.
- SP 23.3: A 7.68GIPS 3.84GB/s 1W Parallel Image-Processing RAM Integrating a 16Mb DRAM and 128 Processors, IEEE International Solid-State Circuits Conference, 1996, pp. 372-373, 298-299, 479.
- "Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAM's", IEEE Journal of Solid-State Circuits, vol. 29, No. 8, Aug. 1994, pp. 887-893.
- FA 14.4: A 150 MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods, IEEE International Solid-State Circuits Conference, 1995, pp. 250-251, 192-193, 356-357.
- FA 142: A 29ns 64 Mb DRAM with Hierarchical Array Architecture, IEEE International Solid-State Circuits Conference, 1995, p. 246-247, 188-189, 355.
- WP 3.5: A 30ns 256Mb DRAM with Multi-Divided Array Structure, IEEE International Solid-State Circuits Conference, 1993, pp. 50-51, 40-41, 215.
- A 30ns 256-Mb DRAM with a Multidivided Array Structure, IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1092-1097.
- Session XVIII: STATIC RAMs, FAM 18.6: A 64Kb CMOS RAM, IEEE International Solid-State Circuits Conference, 1982, pp. 258-259.