Method and Apparatus for Modulus Error Checking

1. Technical Field of the Invention

This invention relates to a method and apparatus for checking the operation of electronic circuits performing floating point arithmetic operations. More particularly, the invention relates to the use of the effective subtract signal to compare the modulus 3 residue of the final result to the correct mathmatical combination of operand residue addition, subtraction, multiply-addition and multiply-subtraction calculation.

2. Background Art

The residue algorithm states that the residue of a final sum is equivalent to the sum of the residues of each operand. A similar postulation exists for multiplication and subtraction. See F. Sellers, Jr., Mn-Yue Hgiao, and L. Bearnson, Error Detecting Logic for Digital Computers, TK7888.354, QA76.5543, at pages 76 ff.

Using the residue algorithm to check the operation of an arithmetic logic unit as it performs such floating point operations generally requires providing circuitry or steps for carrying the residue of all operands, calculated floating point result and the residue sign through all calculations. This directing increases the number of circuits required to implement residue checking and reduces the performance of the checking function.

There is, therefore, a need in the art for an apparatus and method to perform mod3 residue checking which eliminates the need to maintain the sign value of individual operand residues as well as the sign of the resultant residue.

A computer implemented method and apparatus is provided for checking the operation of an arithmetic logic unit by checking the final result of floating point arithmetic operations by calculating an effective subtract signal, and based thereon selecting the correct mathematical combination of residue addition, subtraction, multiply-addition and multiply-subtraction to be used in checking the residue of the final floating point result.

Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompany drawings.

FIG. 1 is a block diagram representation of the apparatus of the invention.

FIG. 2 is a schematic logic diagram representation in greater detail of the select compare blocks of FIG. 1.

This invention eliminates the need to maintain the sign value of the individual operand residues as well as the sign of the resultant residue by employing the use of an effective subtract signal which is already in use and logically required to generate the final arithmetic answer.

With this technique, the effective subtract signal is used in selecting the correct mathematical combination of residue addition, subtraction, multiply-addition and multiply-subtraction in checking the residue of the final floating point result. In the event that the selected residues do not compare, an error signal is generated indicating that one or more circuits within the arithmetic logic unit have failed. In response to that error signal, corrective action may be taken, such as issuing an interrupt to cause execution of a correction routine outside of the scope of this invention.

Referring to FIG. 1, by way of general overview and introduction, the result of an addition of two operands FA 110 and FB 100 is checked by the addition of the operand residues, the result of which is compared to the residue of the calculated sum, if this operation turns out to be an effective add, such as 1+2. If the addition, in reality, is an effective subtract, such as 1+(-2), then the result is checked by the compliment mathmatical calculation of subtraction. In practice for modulus 3 calculations, the residue compliment of an addition is the same as the residue calculated for a straight residue subtraction, and vice versa. This means that an addition operation that results in an effective subtract can be checked by the subtract residue checker. Likewise, a subtract operation that results in an effective add can be checked by the addition residue checker.

The effective subtract signal is externally calculated from comparisons of input operand sign values and the floating point mathematical function to be performed. Effective subtract is considered active for addition if operands are of different sign, for subtraction if operands are of same sign, for multiply-add (MAD) if the resultant product sign is different from the add operand sign, and for multiply-subtract (MSUB) if the resultant product sign is equal to the subtract operand sign.

More complexity results from multiple floating point instructions such as multiply-add and multiply-subtract, where it is not clear if the magnitude of the results of multipling two operands FA 110 and FC 112 will cause an effective add or effective subtract with third operand FB 100. Use of the carry out signal 145 from final adder block 134, correctly handles these situations and increases the number of floating point instructions that can be checked for better checking coverage, better performance and with fewer logic circuits.

Referring further to FIG. 1, a block diagram illustrating the apparatus of the invention is set forth. The residue check apparatus of the invention receives as inputs floating point operand FA 110, floating point operand FB 100 and floating point operand FC 112, where the relationship between operands FA, FB and FC, and the operations to be performed thereon, may take the following forms, or cases:

Tables 1 through 12 are VHDL code listings for logic blocks in FIG. 1 representing the preferred embodiment of the invention, specifically a floating point unit modulus 3 result checker logic. VHDL is the VHSIC (very high speed integrated circuit logic) hardware description language of the IEEE standard 1076, and is described also in Libsett, Schaefer and Ussery, VHDL: Hardware Description and Design, Kluwe Academic Publishers, copyright 1989, Library of Congress TK7887.5.L57 1989 621.39'2 89-11114 ISBN 0-7923-9030-X.

Table 1 provides various initialization declarations, including ports and shift register latches (SRLs) for the memory elements. Table 2 provides clock synchronization to input interface signals. Tables 3 through 12 will be referred to hereinafter in connection with the description of FIG. 1.

Tables A and B cross reference the signal lines in FIGS. 1 and 2, respectively, with the signal names in Tables 1 through 12.

The following signals are low level signals not shown in the VHDL source code: 312, 314, 322, 324, 332, 334, 342, and 344. The following blocks are low level blocks and not shown in the VHDL source code: 236, 311, 313, 321, 323, 331, 333, 341 and 343. The following signal is a compliment, and not shown in the VHDL source code: not effective subtract 237 is a compliment of effective subtract 137.

Referring now to FIG. 1 in connection with Table 6, operand FB block 100 output line 101 is fed to shift right block 102, the output of which is fed on line 103 to complimenter 104. The output of complimenter 104 is fed on line 105 as one hundred and sixty one bits fpfbsht1.sub.-- out(1 to 80), fpfbsht2.sub.-- out(81 to 160) to modulus calculator for operand FB 106 and to carry save adder (CSA) tree 116. The output of modulus calculate for operand B block 106 is fed as a two bit residue value bm1h and bm2h on line 107 to add modulus result block 124, to subtract modulus result block 126, to multiply-add (MAD) modulus result block 130, and to multiply-subtract (MSUB) modulus result block 132.

Referring to FIG. 1 in connection with Table 3, the output of floating point operand FA block 110 is fed on line 109 as 53 bits fpfafraw.sub.-- in(0 to 52) to carry save adder CSA tree 116 and modulus calculate block 120. As shown in Table 3, modulus calculate block calculates the mod3 residue of operand FA. The output of modulus calculate block 120 is latched and fed on two bit line 121 as residue signals fpam1L1(1) and fpam2L1(1) to add modulus result block 124, subtract modulus result block 126 and to multiply modulus result block 128. Modulus signal fpam1L1(1) is a one bit signal indicating, when on, that the result of the modulus 3 calculation on operand FA equals "1". Modulus signal fpam2L1(1) is a one bit signal indicating, when on, that the result of the modulus 3 calculation on operand FA equals "2". If both signals fpam1L1(1) and fpam2L1(1) equal zero, then the modulus 3 calculation on operand FA equals "0". Two similar output bits are used at the outputs of each of modulus 3 calculators 106, 120, 122 to signal the residue values of "0", "1" or "2" on two-bit lines 107 (bm1h, bm2h), 121 (fpam1L1(1), fpam2L1(1)), and 123 (fpcm1L1(1), fpcm2L1(1)), respectively.

Referring to FIG. 1 in connection with Table 4, the output of operand FC block 112 is fed as 53 bits fpfcfraw.sub.-- in(0 to 52) on line 113 to decode block 114, and to modulus operand FC calculate block 122. The output of modulus calculate block 122 is latched and fed as two one-bit signals fpcm1L1(1) and fpcm2L1(1) on line 123 to multiply modulus result block 128.

Decode block 114, in this embodiment, is a Boothe decoder which for multiply operations provides a partial product decode which is sent via line 115 through carry save adder (CSA) tree 116, and is used to reduce n bits at a time. For add operations, the input to Boothe decoder 114 is gated straight through. Carry save adder tree 116, in this embodiment, provides a three to two partial adder, which outputs carry and sum bits on line 117 to partial product latch 118. The results are wrapped around on line 119 to be fed back through decode 114 into carry save adder tree 116 along with new operand bits from lines 109. The output of partial product block 118 is also fed on lines 119 to final adder 134, also referred to as Carry Propagate Adder (CPA) block 134, or full adder 134. Output 135 of full adder block (carry propagate adder CPA) 134 comprises one hundred sixty one bits zm1(0) to zm1(160) and is the result that is being checked by the residue checker of the invention. This result 135 is latched (for timing purposes) into modulus calculate (result) block 138, and the carry out bit is fed on line 145 as a carry out signal 145 to subtract modulus result block 126 and multiply subtract (MSUB) modulus result block 132.

The output of sign unit 136 is fed on line 137 as effective subtract signal 137 to Add select/compare block 142, to MAD select/compare block 140, to subtract (SUB) select/compare block 152 and to multiply-subtract (MSUB) select/compare block 154, and is there used to gate the appropriate select/compare block 142, 140, 152, 154 result to error detect block 150. Multiply compare 156 is not affected by effective subtract.

Effective subtract signal 137 is externally calculated as fpmd3sin.sub.-- in from comparisons of input operand sign values and requested floating point mathematical function, wherein effective subtract is considered active for addition if operands are of different sign, for subtraction if operands are of same sign, for MAD if resultant product sign is different from add operand sign, and for MSUB if resultant product sign is equal to subtract operand sign.

Referring to FIG. 1 in connection with Table 5, the output of modulus calc (result) block 138 is fed as two one-bit signals zm1h and zm2h on two-bit line 139 to select/compare multiply block 156, select/compare MSUB block 154, select/compare SUB block 152, select/compare MAD block 140 and select/compare ADD block 142.

Operand calculate result blocks are identified by grouping block 158 to include ADD result block 124, SUB result block 126, MULT result block 128, MAD result block 130 and MSUB result block 132.

Referring to FIG. 1 in connection with Table 7, the output of add modulus result block 124 is fed as two bit signals aab1 and aab2 on line 125 to add select/compare block 142 and subtract select/compare block 152. The output of subtract modulus result block 126 is fed as a four bit signal asb1, asb2, asbn1, asbn2 on line 127 to subtract (SUB) select/compare block 152 and to add select/compare block 142. The output of multiply modulus result block 128 is fed as signals amc1 and amc2 on two bit line 129 to multiply subtract (MSUB) modulus result block 132, multiply add (MAD) modulus result block 130, and to MULT select/compare block 156. The output of multiply add (MAD) modulus result block 130 is fed as two bit signal mad1 and mad2 on line 131 to select MAD select/compare block 140 and to multiply subtract select/compare block 154. The output of multiply subtract (MSUB) modulus result block 132 is fed as a four bit signal on line 133 (msub1, msub2, msubn1, and msubn2) as residue for msub1 result signal msub1, residue of msub2 result signal msub2, and as compliment signals msubn1 and msubn2, respectively, to select MSUB select/compare block 154 and to multiply add select compare block 140. Hereafter, in connection with FIG. 2, the structure and operation of one example embodiment of select/compare blocks 142, 140, 152, 154 and 156 will be further described.

Referring further to FIG. 1 in connection with Tables 3, 4 and 6, modulus calculators 106, 120 and 122 calculate the mod 3 residues of operands 100, 110 and 112. As shown in Tables 7, 8, 9, 10 and 11, modulus adders 124, 126, 128, 130 and 132 calculate, using the outputs of modulus calculators 106, 120 and 122, the modulus 3 results, or residues, of combinations of floating point operands 100, 110 and 112. Herein, each residue value at the output of adders/calculators 106, 120, 122, 124, 128 and 130, respectively, is a two bit value 107 (bm1h, bm2h), 121 (fpam1L1(1), fpam2L1(1)), 123 (fpcm1L1(1), fpcm2L1(1)), 125 (aab1, aab2), 129 (amc1, amc2), and 131 (mad1, mad2), representing "0", "1" or "2", which are the only three possible residue values in modulus 3 arithmetic. Herein, each residue value at the output of adders/calculators 126 and 132, respectively, is a four bit value 127 and 133, representing "0", "1" or "2" or mathmatical residue compliment function of residue "0", "1" or "2". Adders 106, 120, and 122, calculate their output values substantially in parallel from the values of the initial operands 100, 110, and 112.

Referring to FIG. 1 in connection with Tables 7, 8, 9, 10 and 11, in this embodiment, result select/compare blocks 142, 140, 152, 154 and 156 substantially concurrently compare the final modulus calculate result signals zm1h and zm2h on line 139 to each of the possible mathematical result generators 124, 126, 128, 130, and 132. In connection with Table 7, MULT compare results are shown as signals m1cmp and m2cmp, Table 8 ADD compare result are shown as signals aab1cmp and aab2cmp, Table 9 SUB compare result are shown as signals asb1cmp and asb2cmp, Table 10 MAD compare result are shown as signals mad1cmp and mad2cmp, and Table 11 MSUB compare result are shown as signals msub1cmp and msub2cmp.

Referring to FIG. 1 in connection with Tables 9 an 11, carry out signal 145 is used to select SUB modulus results asb1/asb2 or SUB compliment modulus results asbn1/asbn2, to generate two-bit subtract operand residue results asbx1/asbx2, shown as line 127, for comparison to final modulus result 139. In a like fashion, now referring to FIG. 1 and Table 11, carry out signal 145 is used to select MSUB modulus results msub1/msub2 or MSUB compliment modulus results msubn1/msubn2, to generate two-bit MSUB operand residue results msubx1/msubx2, shown as line 133, for comparison to final modulus result 139.

As shown in Tables 7, 8, 9, 10, and 11, MULT error check signal 165 is generated as fpmmod3.sub.-- out(2), or mulchk; ADD error check signal 161 is generated as fpmmod3.sub.-- out(0), or addchk; SUB error check signal 163 is generated as fpmmod3.sub.-- out(1), or subchk; MAD error check signal 162 is generated as fpmmod3.sub.-- out(3), or madchk; and MSUB error check signal 164 is generated as fpmmod3.sub.-- out(4), or msubchk.

Referring to FIG. 1 in connection with Table 12, valid OP generator block 160 provides a five bit signal addval, madval, subval, msubval and mulval on line 151. These five valid OP signals enable ADD select/compare block 142, MAD select/compare block 140, SUB select/compare block 152, MSUB select/compare block 154 and MULT select/compare block 156, as will be more fully described hereafter in connection with FIG. 2, where these five valid operation signals 151 are shown as five lines 251, 351, 451, 551 and 651.

Referring to FIG. 1 in connection with Table 12, as will be more fully described hereafter in connection with FIG. 2, effective subtract signal fpmd3sin.sub.-- in, shown as line 137, is used to select the correct modulus result calculator 158 by gating the applicable line 125, 127, 129, 131 or 133 into the corresponding select/compare block 140, 142, 152, 154 or 156:

for ADD generating the final ADD check result addchkf on line 161,

for SUB generating the final SUB check result subchkf on line 163,

for MAD generating the final MAD check result madchkf on line 162,

for MSUB generating the final MSUB check result MSUBchkf on line 164.

Straight multiply modulus results on line 165 are not affected by effective subtract 137.

Referring to FIG. 1 in connection with Table 12, the output signals 161 (fpmmod3.sub.-- out(0)), 162 (fpmmod3.sub.-- out(3)), 163 (fpmmod3.sub.-- out(1)), 164 (fpmmod3.sub.-- out(4)) and 165 (fpmmod3.sub.-- out(2))of select/compare add block 142, MAD block 140, SUB block 152, MSUB block 154 and MULT block 156, respectively, are fed to error detector block 150, the output of which appears on line 167 (fpmmod3.sub.-- out(0 to 4)).

In operation, the effective subtract signal fpmd3sin.sub.-- in 137 from sign unit 136 and the carry out signal fpcpasL2(1) 145 from final adder 134 are used to select the correct residue checker 124, 126, 128, 130 or 132 for comparison in compare units 142, 140, 152, 154 and 156 to detect and signal at error detect line 150, 167 an error in the result out of full adder 134. In this way, the result is provided without reference to the residue sign calculation required in the residue checkers of the prior art, and thus results in a saving of the logic circuits required.

Referring now to FIG. 2, further description will be provided with respect to the select/compare blocks 142, 140, 152, 154 and 156 of FIG. 1, illustrating one specific embodiment for utilizing effective subtract signal 137 for gating the appropriate modulus 3 compare results to the error detect line 150, 167.

In FIG. 2, add compare block 242, and gates 311 through 317, correspond to add select compare block 142. A similar correspondence exists with respect to multiply add compare block 240 and its associated gates down through 327, with multiply add select compare 140. And so on, for subtract compare 252 and subtract select/compare 152; and multiply subtract compare 254 and multiply subtract/compare 154.

As shown in FIG. 2, modulus calculate result block 138 output 139 (zm1h, zm2h) is fed to add compare 242, multiply add compare 240, subtract compare 252, multiply subtract compare 254 and multiply compare 256. Add modulus result 124 output line 125 (aab1, aab2) is fed to add compare 242; multiply add modulus result block 130 output 131 is fed to multiply add compare block 240; subtract modulus result block 126 output 127 (asbx1, asbx2) is fed to subtract compare 252, multiply subtract modulus result block 132 output 133, (msubx1, msubx2) is fed to multiply subtract compare 254; and multiply modulus result block 128 output 129 (amc1, amc2) is fed to multiply compare block 256. Each of compare blocks 242, 240, 252, 254 and 256 provide an active signal on their respective output lines 243, 241, 253, 255 and 257 if the modulus calculate result 139 compares equal to respective input modulus results 125, 131, 127, 133 and 129.

The output of add compare block 242 is fed on line 243 (aab1cmp, aab2cmp) to AND gates 311 and 331. The output of multiply add compare block 240 is fed on line 241 (mad1cmp, mad2cmp) to gates 321 and 341. The output of subtract compare block 252 is fed on line 253 to gates 313 and 333. The output of multiply compare block 254 is fed on line 255 (msub1cmp, msub2cmp) to gates 323 and 343. The output of multiply compare block 256 is fed on line 257 (m1cmp, m2cmp) to gate 357, where it is gated by multiply 651 to output line 165.

Sign unit 136 output 137 appears as effective subtract signal 137 at gates 313, 323, 331 and 341, and, after inversion in block 236, as not effective subtract signal 237 at gates 311, 321, 333 and 343. The output 312 and 314 of AND gates 311 and 313, respectively, are fed to OR gate 315; of AND gates 321 and 323 as signals 322 and 324, respectively, to OR gate 325; of and gates 331 and 333 as signals 332 and 334, respectively, to OR gate 335; and of AND gates 341 and 343 as signals 342 and 344, respectively, to or gate 345.

Valid operation generate block 160 provides operation signals 151, including add 251 (addval) to AND gate 317, subtract 351 (subval) to AND gate 337, multiply add 451 (madval) to AND gate 327, multiply subtract 551 (msubval) to AND gate 347, and multiply 651 (mulval) to AND gate 357 where they gate the outputs of 0R gates 315, 325, 335, and 345 and multiply compare 256 on lines 316 (addchkf), 326 (madchkf), 336 (subchkf) and 346 (msubchkf), and 257 (mulchk) respectively, to output lines 161, 162, 163, 164 and 165, respectively.

In operation, by way of example for an add operation, line 251 is active, and depending upon whether or not effective subtract 137 or not effective subtract 237 is active, gates the output of add compare 242 or subtract compare 252 through to error signal output line 161. Thus, if for an add operation, with line 251 active, and for not effective subtract 237 active, if add compare 252 determines that modulus calculate result line 139 and add modulus result line 125 are equal, line 161 is not active, indicating that no error was detected in the operation of circuits performing the add operation. Similarly, for an add operation, with line 251 active, and for effective subtract 137 active, if add subtract compare 252 determines that subtract modulus result 126 output signal 127 compares equal to the modulus calculate result 138 output signal 139, then the result of subtract compare signal 253 (asb1cmp, asb2cmp) gates a no error signal from gates 313 and 315 through gate 317 to output line 161.

By way of further description of the operation of the invention, a computer implemented method is provided for checking the operation of circuitry, herein including blocks 114, 116, 118 and 134, used in calculating the final result on line 135 (signal fptrfL2.sub.-- in(1 to 160)) of floating point arithmetic operations. Effective subtract signal 137 (fpmd3sin.sub.-- in) is generated by sign unit 136, and responsive to that effective subtract signal 137, the modulus 3 residue of the selected mathmatical function or the modulus 3 residue of the add/subtract complimentary mathmatical function from modulus result blocks 124, 126, 130 and 132 are selected as final error determination of the operation of circuits providing the floating point arithmetic result at line 135.

In this preferred embodiment, effective subtract signal 137 is calculated as fpmd3sin.sub.-- in from comparisons of input operand 100, 110 and 112 sign values and the floating point mathematical function being performed. Sign unit 136 operates to provide an effective subtract 137 signal which is active for addition if operands FB 100 and FA 110 are of different sign, for subtraction if operands FB 100 and FA 110 are of same sign, for multiply-add (MAD) if resultant product sign is different from the add operand FB sign, and for multiply-subtract (MSUB) if resultant product sign is equal to the subtract operand FB sign. A modulus 3 of final result full adder 134 shown on line 135 is generated by result modulus calculator 138 and appears on line 139 as two bit values zm1h and zm2h. This final result modulus is compared to each of the arithmetic modulus calculators 124, 126, 128, 130 and 132 for addition, subtraction, multiplication, multiply-add and multiply-subtract in blocks 142, 152, 156, 140 and 154 respectively. For addition, result modulus 139 is selected for comparison with addition modulus result calculator 124 when effective subtract 137 is inactive. Conversely for addition, result modulus 139 is selected for comparison with subtraction modulus caaalculator 126 when effective subtract 137 is active. Likewise for subtraction, result modulus 139 is compared to subtract modulus calculator 126 for effective subtract 137 active and to addition modulus calculator 124 for effective subtract 137 inactive.

When a floating point arithmetic operation is a multiply of operands FA 110 and FC 112, the mod 3 residues 121 and 123 of those operands are calculated in modulus calculate blocks 120 and 122, respectively, and combined in multiply modulus result block 128 to form operand multiply result modulus 129. The modulus of the final result product of operands FA 110 and FC 112 is calculated in modulus calculate result 138. Multiply select/compare block 156 determines if modulus result 139 and modulus of the product 129 are equal, and if not, generates an error signal 165 to error detect block 150.

Responsive to a floating point arithmetic operation adding operands FA 110 and FB 100, FB operand 100 is magnitude right shifted in block 102 for decimal alignment to operand FA 110. Complimenter block 104 calculates either the true or compliment of operand FB 100 for addition or subtraction functions as determined by the sign unit. Block 106 calculates the modulus 3 residue of operand FB 100 as signals bm1h and bm2h. Modulus calculate operand FA block 120 calculates the modulus 3 residue 121 of operand FA 110. Sign unit block 136 generates an effective subtract signal 137 inactive if the sign of operand FB100 and FA110 are equal for addition, and effective subtract signal 137 active if the sign of operand FB 100 and FA 110 are not equal for addition.

Responsive to a floating point arithmetic operation which is a subtract of operands FA 110 and FB 100, FB operand 100 on line 101 is magnitude right shifted in block 102 for decimal alignment to operand FA 110, and complimented in block 104 for effective subtract (that is, for use in the event of effective subtract). The modulus 3 residue of operand FB 100 is calculated in block 106, the modulus 3 residue of operand FA is calculated in block 120, and the residue addition and residue subtraction of residues FA and FB on lines 121 and 107 are calculated in add modulus result block 124 and subtract modulus result block 126, respectively. The modulus 3 result of the final result on line 135 is calculated in modulus calculate result block 138. For effective subtract line 137 inactive, the residue addition on line 125 is compared to the result residue on line 139; and for effective subtract active, the residue subtraction on line 127 is compared with the result residue on line 139. In this specific embodiment, these comparisons are always made, and the result gated by effective subtract 137 through to the error detect block 150, as previously described in connection with FIG. 2.

Responsive to a floating point arithmetic operation which is a multiplication of operands FA and FC and addition of operand FB, processing proceeds as follows. The modulus 3 residues of FA and FC operands are calculated in blocks 120 and 122 and combined in block 128 to form the operand multiply result modulus at line 129. The modulus 3 residue of the remaining FB operand 100 is calculated as above. The final operand residue is formed in block 130 from the operand multiply result modulus on line 129 and the modulus 3 residue of operand FB 100 on line 107. As above, the modulus 3 residue of the floating point result is calculated and placed on line 139. For effective subtract inactive, the modulus result on line 139 and the addition operand modulus on line 131 are compared; and for effective subtract active, the modulus result on line 133 is compared with modulus result on line 139. Based on the selected comparison (or on that comparison which is gated through by effective subtract signal 137), error detect block 150 is provided, for non-equivalence, an error signal on line 162 or 164.

Responsive to a floating point arithmetic operation which is a multiplication of operands FA and FC and subtraction of operand FB, the checking of the operation of circuits executing the operation is as follows: (1) the modulus 3 residues of FA and FC operands are calculated in blocks 120 and 122, respectively; (2) the modulus 3 residues on lines 121 and 123 are combined in block 128 to form an operand multiply result modulus at line 129; (3) the modulus 3 residue of the remaining FB operand is calculated in block 106; (4) in block 132, a final operand residue is formed from the product and FB residue values on lines 129 and 107, respectively; (5) in block 130, a final operand compliment residue is formed from the same product and FB residue values 107 and 129, respectively; (6) in block 138, the modulus 3 residue of the floating point result from full adder 134 is calculated; and (7) in block 154, for effective subtract inactive, the modulus result 139 and the final operand residue 133 are compared for equivalence; for effective subtact active, the modulus result 139 and final operand compliment residue 131 are compared for equivalence; and an error signal is generated on line 164 to error detect 150 in the event of non-equivalence.

Herein, the requested mathematical residue for an add function is the output of add modulus result 124, and the compliment requested mathematical residue is the output of subtract modulus result 126; and visa versa for a subtract function. For a multiply-add function, the requested mathematical residue is the output of MAD modulus result 130, and the compliment requested mathematical residue is the output of MSUB modulus result 132; and visa versa for a multiply-subtract function.

Add 11+4

Add line 251 is active

Effective subtract line 137 is inactive

In Example 1, had there been an error in the calculation result out of full adder 134, it is likely that the residue of that calculation derived by modulus calculate result 138 and placed on line 139 would not have been equal to the residue on line 125; in which event, add select/compare 142 would have detected the inequality and signalled an error on line 161.

Add 11+(-4)

Add line 251 is active

Effective subtract line 137 is active

In Example 2, at the Mod Calc Op FA 120,121 step, note that number magnitudes only (that is, absolute values, such as .vertline.-4.vertline.) are used in calculations, requiring no logic for sign propagation.

Calculate 11+(4*2)

Multiply add line 451 is active

Effective subtract line 137 is inactive (line 237 active)

Line 131 is selected for this compare in block 140 by effective subtract line 137 being inactive, as has been previously described in connection with FIG. 2.

By this invention, there is provided an apparatus and method performing modulus 3 residue checking of floating point arithmetic operations which eliminate the need to maintain the sign value of individual operand residues as well as the sign of the resultant residue. This results in a savings in logic circuits or programming steps with resultant lower cost and faster response than possible with prior art devices.

It will be appreciated that, although a specific embodiment of the invention has been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. In particular, use of the effective subtract signal may also be used to select complimented modulus calculations rather than complimented arithmetic function.

The application of the effective subtract for true and compliment modulus selection for final result modulus comparison, additionally applies to all other value based modulus calculations.

Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.