Short Circuit Protection for Power Factor Correction Circuit

This invention relates to power factor correction (PFC) circuits used in power converters, and more particularly to a short circuit protection arrangement which prevents harmful current surges through the output switching transistor.

Power converters which convert commercial AC power to regulated DC power conventionally contain a PFC circuit whose input is the raw full-wave rectified AC input power source, and whose output is a DC voltage higher than the peak voltage of the AC power source. This DC voltage output can be used as the input to a DC-to-DC converter whose output, in turn, consists of one or more regulated DC voltages.

The objective of a typical basic PFC converter is to cause the input current drawn by the converter to follow the input voltage waveform so that the converter presents a resistive load to the input power source. A typical prior art conventional switched power supply operates as a capacitive input load for the rectified line voltage. Such a load draws relatively high currents near the peaks of the alternating current cycle, and substantially zero current for the remainder of the cycle. This results in a poor power factor, which manifests itself as a larger RMS current for a given input voltage and power load, than if the load were purely resistive. Consequently, for a given line current, the typical prior art switched power supply is capable of delivering only a fraction of the power which could be delivered if the line current were sinusoidal, which is the case when the load is primarily resistive. Typically, a conventional switched-mode power supply may have a relatively low power factor, e.g., of the order of 0.65. Such a power supply would only be able to draw 160 watts from a 110-volt 12 amp power outlet. By contrast, if the power factor were unity, the supply could draw 1,320 watts from that power outlet.

Active PFC converters generally use a boost converter topology since the input current can be made to be continuous. In a typical boost topology, a boost inductor is coupled in series with a rectifier between input and output ports of the boost connector. A switch is coupled between the output side of the boost inductor and ground and is switched on and off at a frequency (e.g., 30 kHz) much greater than the AC power frequency (e.g., 50 to 60 Hz). In each switching cycle, energy is stored in the inductor when the switch is closed (ON period) and released to the output port via the rectifier when the switch is opened (OFF period). Due to the inductance of the boost inductor, the current through the switch increases nearly linearly with time during the ON period. Additionally, the current through the boost inductor during each switch cycle increases linearly during the ON period and decreases linearly during the OFF period, creating a current peak at the end of each ON period. A bulk capacitor at the output of the converter smooths this output.

In a typical basic PFC converter, a clock signal generally starts the ON-period of each switching cycle. During each ON-period, the current through the switch is measured and compared against a line voltage reference signal, sometimes called a sinewave reference signal. The line voltage reference signal has a waveform (i.e., shape) which follows the sinusoidal waveform of the input voltage. When the switch current ramps up to a value equal to the line voltage reference signal, the ON period is ended. The switch current thereby has a pulsed shape, with the envelope of pulse peaks following the line voltage reference signal. The inductor current, and hence the input current, equals the switch current during the ON periods, and ramps up during each ON period. During the OFF periods, the inductor current ramps down as the inductor couples current to the output. Accordingly, both the inductor current and the converter's input current generally follow the waveform of the line voltage reference signal. Specifically, the current peaks of the boost inductor trace out an envelope which generally has a waveform corresponding to the input voltage. The amplitude of the current peaks is regulated by using the output voltage of the PFC circuit to control the switch so as to provide sufficient output current from the PFC circuit.

Because it is necessary to control the current flow to the bulk capacitor which forms part of the boost converter, and to the output load connected across it, a power metal oxide silicon field effect transistor (MOSFET) or an IGBT is typically connected in series between the rectifier and the bulk capacitor and output load. A gate drive circuit rams the power MOSFET on and off in response to appropriate control signals.

If a short circuit occurs in the output of the PFC circuit, overcurrent sensing circuitry can be used in conjunction with the gate drive circuit to turn the power MOSFET off. Nevertheless, a large momentary overcurrent or continued operation of the power MOSFET at its upper current limit can stress the power MOSFET and reduce its useful life. It is therefore desirable to control the power MOSFET in such a way that it shuts off before a short circuit condition can ever draw excessive current through it.

The present invention accomplishes the desired result by monitoring not the power MOSFET current itself, but rather the relationship between the input voltage and the output voltage. A function of the voltage at the input to the boost converter, increased a fixed amount by a zener diode or a resistive network, is applied to one input of a comparator, while a function of the output voltage is applied to the other input of the comparator. The comparator output is applied to a gate drive which shuts off the power MOSFET if the comparison indicates a short circuit condition.

Normally, the output voltage is always higher than the zener-adjusted input voltage. When a short circuit occurs, however, on the output side of the power MOSFET, the output voltage instantly drops below the zener-adjusted peak input voltage. This condition triggers shutoff in the inventive circuit before the current through the power MOSFET has time to build up to a harmful level.

FIG. 1a is a circuit diagram illustrating the circuit of this invention;

FIG. 1b is a circuit diagram similar to FIG. 1 but illustrating an alternative embodiment of the invention; and

FIG. 2 is a time-amplitude diagram illustrating the action of the circuit.

FIG. 1a illustrates a PFC circuit 10 according to a first preferred embodiment of the invention. Commercial AC power applied across terminals 12, 14 is rectified, preferably by a full-wave bridge rectifier 16, and applied to a PFC network consisting of inductor 18, switching transistor 20, diode 22, and capacitors 24 and 26. The output of circuit 10 is applied to a DC-to-DC converter 28 which converts the unregulated DC output of circuit 10 into one or more regulated DC voltages for DC power supplies.

The network consisting of inductor 18, switching transistor 20, diode 22 and capacitors 24 and 26 constitutes a conventional boost converter. The function of the boost converter is to make the DC voltage on line 30 substantially higher than the peak voltage of the rectified AC supply on line 32. Its use and functioning in achieving power factor correction is detailed in U.S. Pat. No. 5,001,620, which is incorporated herein by reference.

Power transfer from the input to the output of the circuit 10 is controlled by power MOSFET 34, which in turn is controlled by a conventional gate drive circuit 36. The gate drive circuit 36 translates in a conventional manner the output of comparator 38 into a control signal appropriate for mining power MOSFET 34 on and off. The gate circuit 36 is so arranged that it rams the power MOSFET 34 off when the output of comparator 38 is low.

The subtractive input 40 of the comparator 38 is connected to the center point of a voltage divider consisting of resistors 42 and 44. The voltage divider 42, 44 is connected in series through a zener diode 46 to line 32, i.e. the unboosted rectified AC input power voltage. The additive input 48 of the comparator 38 is connected to the center point of a second voltage divider consisting of resistors 50 and 52. The voltage divider 50, 52 is connected to the output voltage appearing across bulk capacitor 26 and the input of the load, DC-to-DC converter 28.

In the embodiment of FIG. 1a, the resistance ratio R.sub.50 /R.sub.52 of resistors 50, 52 is made equal to the ratio R.sub.42 /R.sub.44 of resistors 42, 44 by making R.sub.42 =R.sub.50 and R.sub.44 =R.sub.52. Consequently, the gate drive circuit 36 will turn the power MOSFET 34 on when V.sub.26 >V.sub.32 +V.sub.46, and will turn it off when V.sub.26 .ltoreq.V.sub.32 +V.sub.46, where V.sub.26 is the output voltage, V.sub.32 is the voltage on line 32, and V.sub.46 is an offset voltage equal to the zener voltage of zener diode 46. Inasmuch as the latter condition exists on startup of the circuit 10, gate drive circuit 36 must not respond to the shutoff signal from comparator 38 until the bulk capacitor 26 has been sufficiently charged through power MOSFET 34 to bring V.sub.26 to the former condition.

This startup override may be accomplished in many conventional ways, of which the following is merely exemplary: V.sub.32 is also applied through diode 60 to an RC network 62, 64 whose midpoint is connected to the subtractive input 66 of comparator 68. The additive input 70 of comparator 68 is connected to a source of reference voltage V.sub.ref. The resistance R.sub.62 of resistor 62, the capacitance C.sub.64 of capacitor 64, and the reference voltage V.sub.ref are so dimensioned as to cause the output of comparator 68 to be substantially positive until the bulk capacitor 26 has had time to charge to a voltage higher than the peak of V.sub.32. At that time, the output of comparator 68 goes negative, and diode 72 disconnects it from the input 48 of comparator 38. The circuit 10 thereafter functions in its normal mode described above.

If a short circuit occurs in the output of circuit 10 while circuit 10 is in normal operation, V.sub.26 will drop sharply to a value lower than V.sub.32 +V.sub.46. This drives the output of comparator 38 negative and causes the gate drive circuit 36 to immediately shut off power MOSFET 34, before a substantial increase in current flow (delayed by the action of bulk capacitor 26) can occur through power MOSFET 34.

The circuit 10 of FIG. 1b is the same as that of FIG. 1a except for the omission of the zener diode 46 and the use of a different conventional startup override circuit. The offset voltage of the zener diode 46 can be created in the circuit of FIG. 1b without the zener diode 46 by so scaling the voltage dividers 42, 44 and 50, 52 in a conventional manner that a constant voltage differential of V.sub.k exists during normal operation between the inputs 40 and 48 of comparator 38. The power MOSFET then turns on if V.sub.26 >V.sub.32 +V.sub.k, and shuts off if V.sub.26 <V.sub.32 +V.sub.k.

In the circuit of FIG. 1b, the startup override function is accomplished by ORing the outputs of comparators 38 and 68 in an OR gate 74 so as to enable gate driver 36 whenever the output of either comparator is positive.

FIG. 2 illustrates the time relationships involved in the operation of the circuit 10. At power-on time A, V.sub.26 is zero. In the circuit of FIG. 1a, the output of comparator 38 (curve (e)) nevertheless goes high because the shutoff override signal from comparator 68 (curve (d)) applied to input 48 of comparator 38 is high on startup. In the circuit of FIG. 1b, the output of comparator 38 is low at turn-on (as shown in phantom in curve (e)), but the shutoff override signal enables the gate driver 36 through OR gate 74.

The bulk capacitor 26 now begins to charge (curve (b)). When it has reached sufficient charge at time B for V.sub.26 to be greater than V.sub.32 plus V.sub.46 or V.sub.k, the output of comparator 38 goes (or remains) high to keep the power MOSFET 34 on. As the bulk capacitor 26 continues to charge toward full operating voltage, the shutoff override signal (d) goes low at time C but this now has no effect because V.sub.26 keeps the output of comparator 38 high.

If a short circuit now occurs at time D, V.sub.26 rapidly drops. The power MOSFET current (curve (f)) tries to rise, but before it can rise very far, V.sub.26 has dropped to a value lower than V.sub.32 plus V.sub.46 or V.sub.k. This causes the output of comparator 38 to go low at time E and shut the power MOSFET 34 off.

It will be seen that the present invention provides a simple and effective way to handle short circuits in the output of a PFC circuit without stressing the power MOSFET.