Field Effect Controlled Semiconductor Component With Integrated Resistance Therein

1. Field of the Invention

The invention is directed to a field effect controlled semiconductor component. This component has a semiconductor body on which a doped polysilicon layer is arranged and insulated from the surface of the semiconductor body. The doped polysilicon layer has two parts. The first part of the polysilicon layer is a gate electrode and the second part is a contact surface for a gate lead.

2. Description of Prior Art

Semiconductor components controllable by field effect of the above general type, such as power MOSFETs or IGBTs, are known in the art. In modules, many such semiconductor components are generally connected in parallel. The parasitic line inductances in the control circuit tend to oscillate when activated. This oscillation prevents a defined (simultaneous) turn-on of all components.

In the past, resistor chips were built into the modules. These resistor chips are connected by bond wires to the gate terminals of the semiconductor components and the external gate terminals of the module. A solution to this problem requires additional space in the module and additional connecting lines.

An object of the invention is based on improving a field effect controlled semiconductor component that is suited for parallel circuitry even without separate resistors.

This object is achieved by electrically connecting the contact surface to the gate electrode through at least one integrated ohmic resistor. The integrated ohmic resistor lies between the contact surface and the gate electrode.

The invention is explained in greater detail on the basis of a few exemplary embodiments in conjunction with the drawings.

FIG. 1 is a plan view of a preferred embodiment of a semiconductor component.

FIG. 2 is a plan view of an alternative embodiment.

FIG. 3 is a plan view of an alternative embodiment.

FIG. 4 is a sectional view of an embodiment.

FIG. 1 shows a portion of a field effect controlled semiconductor component. The surface of a semiconductor body is covered with an insulating layer (not shown). The doped polysilicon layer is arranged on top of the insulating layer. The polysilicon layer has a first part that serves as the gate electrode 1 and a second part that forms the contact surface 3 for fastening a gate lead. The gate electrode 1 is provided with openings 2 that are insulated from the polysilicon layer through which the source zones of the individual cells of the semiconductor component are contacted. These openings 2 form a regular pattern distributed over the surface of the gate electrode 1. Broader areas 7 can be free of holes between neighboring cells for the acceptance of gate contact fingers for better distribution of the gate potential given larger chips.

The gate electrode 1 has a recess 4 in which the contact surface 3 is arranged. The doped polysilicon layer is etched between the contact surface 3 and the gate electrode 1. Islands 5 that form integrated ohmic resistors lie in the recess 4 between the contact surface 3 and the gate electrode 1. These integrated ohmic resistors are preferably composed of doped polycrystalline silicon and have the same doping as the contact surface 3 and the gate electrode 1. They also preferably have the same thickness as the gate electrode 1 and the contact surface 3.

The islands 5 are connected by interconnects 6 to the gate electrode 1 and the contact surface 3.

The islands 5 can be produced simultaneously with the structuring of the contact surface 3 and of the gate electrode 1. Their length and their cross section are based on the intended size of the gate resistor R.sub.g (not shown), i.e., the desired voltage drop thereacross.

In FIG. 2, the contact surface 3 is connected to the gate electrode 1 by ridges 8. The ridges 8 are composed of polysilicon. Their length and their cross section are again based on the intended value of resistance of the gate resistor R.sub.g.

The islands 5 in FIG. 1 or the ridges 8 in FIG. 2 are formed by 0.5 to 1 .mu.m thick polysilicon according to an exemplary embodiment. Their width and their length can amount to 0.5 mm. The polysilicon can be doped such that it has a resistance of 20 ohms/.quadrature..

The embodiment in FIG. 3 differs from that in FIG. 1 in that the islands 5 are arranged in the recesses 4 of a contact surface 3. Here, as in the embodiment of FIG. 1, the islands 5 are contacted by interconnects to the contact surface 3 and the gate electrode 1. As shown, the recesses 4 can lie at the corners of the contact surface 3 or at some other locations of the circumference. Like the recesses 4, the islands 5 can be quadratic; other shapes are also possible.

FIG. 4 shows the surface of a semiconductor component having semiconductor zones 11, 13 covered with an oxide layer 12. The structured polysilicon layer is composed of the contact surface 3, the islands 5 and the gate electrode 1. This structured layer lies on the oxide layer 12. An insulating layer 10, which covers the gate electrode 1, the contact surface 3 and the islands 5, lies on the polysilicon layer. A metal layer 14 is arranged on the insulating layer 10 above the contact surface 3. A gate contact finger 15 mentioned in conjunction with FIG. 1 is seated on the gate electrode 1. It is formed as part of the metal layer 14. The metal layer 14 on the contact surface 3 is electrically connected with the polysilicon layer by the holes 19. In the same way, the gate contact finger 15 is connected to the gate electrode 1 by holes 16. Since the island 5 is also covered with the oxide layer 10, the separate interconnects 6 are connected over holes 17 to the polysilicon of the island 5, which represents the resistor. The metal layer 14 is in communication with an external terminal of the semiconductor component via a bond wire 18.

Only a single resistor island 5 was shown in the section of FIG. 4 by way of simplification. As in FIGS. 1, 2 and 3, however, a plurality of resistors can also be integrated. The value of resistance for R.sub.g is then lowered corresponding to the plurality of resistors connected in parallel.

Although modifications and changes may be suggested by those skilled in the art, it is the intention of the inventors to embody within the patent warranted hereon all changes and modifications as reasonably and properly come within the scope of their contribution to the art.