Reduction of the Address Pins of the Integrated Circuit

The invention relates to a method and circuit for inputting address signals to an integrated circuit using reduced number of address pins.

The state-of-art process of integrated circuit (IC) allows much higher scale of circuit integration on a single silicon chip. As a result, the complicated circuits within the chip requires more external pins configuration to communicate with external devices. Typically, as number of pins of an integrated circuit increases, the IC package cost increases accordingly. Therefore, the cost involved in making an integrated circuit rests mainly on number of pins configured instead of number of circuits integrated. The designer sometimes has to choose a second-choice IC package, which has higher number of pins than needed, just because his circuit design needs one or two more pins than number of pins of the best-choice IC package within his list. For instance, in field of personal computer, the most popular package used is Quad Flat Package (QFP) with 100 pins or 160 pins configuration. If, after the evaluation of the circuit integration, the design needs 101 or 102 external pins, the most cost-effective Quad Flat Package with 100 pins can not be employed. And when IC package with 160 pins is utilized, the package cost definitely increases, other than the drawback of inherent increase of size of the corresponding printed circuit board. From another point of view, reducing the scale of integration will definitely affect the competitiveness of the integration circuit in the market place.

The instant invention, based on the above observations, uses an external multiplexer circuit with an IC of reduced address pins to input the address signals.

The invention makes reduced number of address pins of an IC possible while keeping higher integration scale of the circuit.

The conventional arrangement of the address pins of integrated circuit is shown in FIG. 1. It is evident that when address signals A.sub..o slashed. .about.A.sub.n are required, the integrated circuit needs n+1 pins to connect the address lines. Those address pins are respectively thereafter connected to DA.sub..o slashed. .about.DA.sub.n of the address decoder 13 within the integrated circuit 11. The signals then are used by the address decoder 13 to generate the chip select signal.

The FIG. 2 shows the timings address bus signals and (Read/Write) signals when read or write access to the integrated circuit is performed. In typical, the signals on the address bus was activated earlier than Read/Write signal which provides a setup time to internal address decoder 13 to decode the address value. As Read/Write signal is activated, the Data Bus within the integrated circuit is 11 then open to connect to the external data bus which allows the operation of data read or data write. It is obvious from FIG. 2, the address signals A.sub..o slashed. .about.A.sub.n are effective only during the activation of the Read/Write signal, i.e., the interval of tA.

A method and circuit for inputting the address signals to an integrated circuit using reduced number of address pins is provided.

The method includes (1) inputting value of A.sub.1, A.sub.3 .about.A.sub.n to the address decoder during a first time interval, and, during the first time interval, an access-control signal is disabled to prohibit access operation; and (2) inputting value of A.sub..o slashed., A.sub.2 .about.A.sub.n-1 to the address decoder during a second time interval, and, during the second time interval, the access-control signal is enabled to allow access operation corresponding to address value of A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n.

The circuit for inputting an address signal A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n, includes an integrated circuit having an address decoder for receiving value of the address signals and a multiplexer.

The multiplexer has a plurality of input terminals for receiving the address signals A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n, and supplying value of A.sub.1, A.sub.3 .about.A.sub.n during a first time interval to the address decoder. During the first time interval, an access-control signal is disabled to prohibit access operation of the integrated circuit. The multiplexer supplies value of A.sub.526, A.sub.2 .about.A.sub.n-1 to the address decoder during a second time interval. During the second time interval, the access-control signal is enabled to allow access operation corresponding to address value of A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n.

FIG. 1 discloses address pins arrangement according to one conventional approach.

FIG. 2 shows the timings of signals in FIG. 1.

FIG. 3 discloses the instant invention in block forms.

FIG. 4 shows the timings of signals regarding to the instant invention.

As shown in FIG. 3, the circuit of the invention, including an integrated circuit 31 and a plurality of multiplexer 34, inputs the address signals A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n. The integrated circuit 31 has an address decoder 33 which has address input lines DA.sub..o slashed., DA.sub.1, DA.sub.2 .about.DA.sub.n for inputting the address signals A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n at specified time interval. The multiplexer 34 has two inputs which receive the address signals (A.sub..o slashed., A.sub.1), (A.sub.2, A.sub.3) . . . (A.sub.n-1, A.sub.n) respectively in accordance with the way shown in FIG. 3. Under control of RWEN signal, the multiplexers 34 inputs value of A.sub.1, A.sub.3 .about.A.sub.n to the address decoder 33 during a first time interval. During this first time interval, the RWEN :signal is disabled to prohibit the integrated circuit performing the access operation. Afterwards, the multiplexers 34 supply value of A.sub..o slashed., A.sub.2 .about.A.sub.n-1 to the address decoder 33 during a second time interval. During the second time interval, the RWEN signal is enabled to allow the access operation by the integrated circuit. The descriptions of timings may be referred to the corresponding recitations regarding to FIG. 4.

The integrated circuit 31 includes an address latch 35 for latching values of A.sub.1, A.sub.3 .about.A.sub.n during the first time interval and outputting these values to the address decoder 33. The RWEN signal, which is the select signal to the multiplexers 34, is obtained by ANDing the Read and Write signals. Furthermore, the RWEN signal is also the signal enabling the address latch 35. The RWEN signal may be input to the address latch 35 via one external pin of the integrated circuit (not shown), or, alternatively, may be generated within the integrated circuit by the AND gate 37 within the integrated circuit 31.

Referring to FIG. 4, during tS in which RWEN signal is logic HIGH, the terminals Z.sub.1 .about.Z.sub.m of the multiplexer 34 outputs values of A.sub.1, A.sub.3 .about.A.sub.n. Therefore, the pins A.sub.1 '.about.A.sub.m ' of the integrated circuit 31 input values of A.sub.1, A.sub.3 .about.A.sub.n. During this time interval, the inputs (LA.sub.1 '.about.LA.sub.m ') and outputs (LA.sub.1, LA.sub.3 .about.LA.sub.m) of address latch 35 within the integrated circuit 31 have values of A.sub.1, A.sub.3 .about.A.sub.n. At this time, the input lines DA.sub..o slashed., DA.sub.1, DA.sub.2 .about.DA.sub.n of the address decoder 33 receive values of A.sub.1, A.sub.1, A.sub.3,.about.A.sub.n, A.sub.n. Although this address value is not correct, the IC chip 31 would not actually perform the access corresponding to this incorrect address due to the inactivation of the RWEN signal. Once the RWEN signal changes to logic LOW, the address latch 35 turns off in response and lines LA.sub.1, LA.sub.3 .about.LA.sub.m hold values of A.sub.1, A.sub.3 .about.A.sub.n. During this time interval, the external multiplexer 34 shifts to the input of pin .O slashed.. The terminals Z.sub.1 .about.Z.sub.m output values of A.sub..o slashed., A.sub.2 .about.A.sub.n-1, the pins A.sub.1 ', A.sub.2 '.about.A.sub.m ' of integrated circuit 31 and DA.sub..o slashed., DA.sub.2 .about.DA.sub.n-1 of address decoder 33 input values of A.sub..o slashed., A.sub.2 .about.A.sub.n-1. Although, during this time, LA.sub.1,.about.LA.sub.m have values of A.sub..o slashed., A.sub.2 .about.A.sub.n-1, value of LA.sub.1 (DA.sub.1), LA.sub.3 (DA.sub.3).about.LA.sub.m (DA.sub.n) are still A.sub.1,A.sub.3,A.sub.5 .about.A.sub.n due to inactivation state of the address latch 35. Therefore, during the tA interval of FIG. 4, the values seen by the address decode 33 are A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1 as required for access operation.

There are different ways for the multiplexers 34 to receive the address signals A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n which are still within the intended scope of protection of the appended claims. For instance, alternatively, the first multiplexer 34 may receive address signals A.sub..o slashed. A.sub.(N+1)/2, while the second multiplexer 34 inputs A.sub.1 A.sub.(n+3)/2, and the third multiplexer 34 inputs A.sub.2 A.sub.(n+5)/2,etc.. By this arrangement, A.sub.(n+1)/2, A.sub.(n+3)/2 .about.A.sub.n are input to the address decoder 33 during the first time interval in which the Read/Write signal is disabled. And A.sub..o slashed., A.sub.1 .about.A(.sub.n-1)/2 are input to the address decoder 33 during the second time interval in which the Read/Write signal is enabled to allow the access operation.

It is also evident that inputting value of A.sub.526 , A.sub.2 .about.A.sub.n-1 to the address decoder during a first time interval, and inputting value of A.sub.1, A.sub.3 .about.A.sub.n to the address decoder during a second time interval is another modification of the instant invention in light of the above recitation and appended drawings.