Performing Tree Additions via Multiplication

This application is based on provisional application Ser. No. 60/000,272, filed Jun. 16, 1995.

The present invention concerns computer operations implemented in hardware and particularly hardware which performs tree additions.

In computer systems one or more arithmetic logic units (ALUs) are generally utilized to perform arithmetic operations. In addition to ALUs, high performance computing often include other special hardware to expedite the performance of specific tasks. For example, a computing system may include hardware devoted to performing multiplication and/or hardware devoted to performing division.

Complex operations for which there is no devoted hardware are generally implemented by a series of instructions. For example, a tree add operation is useful for video compression. In one case of a tree add instruction, four sixteen-bit half words originally in a single sixty-four bit register are added together. In another case of a tree add instruction, eight bytes originally in a single sixty-four bit register are added together. In another case of a tree add instruction, four bytes originally in a single thirty-two bit register are added together. And so on.

In order to perform a tree add instruction, it is generally required to place each operand in a separate register and then, to successively use the add operation implemented by the ALU to add operands together, two at a time. As will be understood, such an execution of a tree add instruction will generally take a large number of instruction cycles. As long as tree additions are rare, this is not a significant hindrance to high performance in a computing system. However, for a computing system which frequently performs tree additions, for example for video compression, implementing the tree add using a large number of instruction cycles could have a negative impact on overall system performance.

In accordance with the preferred embodiment of the present invention, a multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree addition is performed. A second value is input into the multiplier in place of a second multiplicand. Each bit of the second value is at logic zero except for a first subset of bits. The first subset of bits are bits of the second value, starting with the low order bit, which are at intervals equal to a bit length of each addend. Each of the first subset of bits is set to logic one. In partial product rows in the multiplier which correspond to the first subset of bits, certain partial products are forced to logic zero. This is done in such a way that all the addends for the tree addition are aligned in columns of the multiplier. The partial products are then summed to produce a result.

In the preferred embodiment, the partial products are generated using three-input logic AND gates. Particular partial products are forced to zero by plating a zero on a control input of the three-input logic AND gate used to generate the partial product.

Also, in the preferred embodiment, the partial products are summed in two steps. In a first step, the partial products are reduced into two rows of partial products. A carry propagate addition is then performed on the two rows of partial products to produce the result.

The present invention allows for a implementation of a tree addition with only minor changes to a multiplier.

FIG. 1 shows a simplified block diagram of a multiplier in accordance with the prior art.

FIG. 2 shows a block diagram of a multiplier in accordance with the prior art.

FIG. 3 shows a simplified block diagram of circuitry which generates partial products for a modified multiplier in accordance with the preferred embodiment of the present invention.

FIG. 4 shows a simplified block diagram of circuitry which generates control inputs used to generate partial products for a modified multiplier in accordance with the preferred embodiment of the present invention.

FIG. 1 shows a block diagram of an integer or mantissa multiplier. Partial product generation logic 11 generates rows of partial products. Row reduction logic 12 uses three-to-two counters to reduce the rows of partial products to two rows. A three-to-two counter is implemented using a one-bit adder slice which adds three one-bit inputs to produce a two-bit output. Carry propagate addition logic 13 performs a full carry-propagate add on the two remaining rows to produce a final product.

FIG. 2 shows a four-bit multiplier in accordance with the prior art. The multiplier multiplies a four-bit first multiplicand X.sub.3 X.sub.2 X.sub.1 X.sub.0 (base 2) with a four-bit second multiplicand Y.sub.3 Y.sub.2 Y.sub.1 Y.sub.0 (base 2) to produce an eight-bit result Z.sub.7 Z.sub.6 Z.sub.5 Z.sub.4 Z.sub.3 Z.sub.2 Z.sub.1 Z.sub.0 (base 2). As is understood by those skilled in the art, logic AND gates 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215 and 216 may be used to generate partial products for the multiplication. A partial product sum circuit 220 sums the partial products generated by logic AND gates 201 through 216 to produce the result. Partial product sum circuit includes both reduction logic and carry propagate addition logic, as described above.

The two multiplicands, X.sub.3 X.sub.2 X.sub.1 X.sub.0 and Y.sub.3 Y.sub.2 Y.sub.1 Y.sub.0, the partial products generated by logic AND gates 201 through 216, and the result produced by partial product sum circuit 220 may be placed in a table in such a way as to summarize operation of the multiplier. For example, such a table is shown as Table 1 below:

In the notation used in Table 1 above, the bit position of each bit of both multiplicands and the result is specifically identified. Additionally, the bits of the multiplicand which are used to form each partial product are specifically set out. As is understood by those skilled in the art, the information shown in Table 1 above may be set out using abbreviated or simplified notation, as in Table 2 below:

In Table 2 above, each row of partial products is shown without the Y component. Thus, the first row of partial products is listed in Table 2 as follows:

However, this is a simplified notation which represents the following partial products:

Similarly, the last row of partial products listed in Table 2 represents the following partial products:

Using the simplified notation of Table 2, an eight-bit multiplier may be described as shown in Table 3 below:

The multiplier shown in Table 3 multiplies an eight-bit first multiplicand X.sub.7 X.sub.6 X.sub.5 X.sub.4 X.sub.3 X.sub.2 X.sub.1 X.sub.0 (base 2) with an eight-bit second multiplicand Y.sub.7 Y.sub.6 Y.sub.5 Y.sub.4 Y.sub.3 Y.sub.2 Y.sub.1 Y.sub.0 (base 2) to produce an sixteen-bit result Z.sub.15 Z.sub.14 Z.sub.13 Z.sub.12 Z.sub.11 Z.sub.10 Z.sub.9 Z.sub.8 Z.sub.7 Z.sub.6 Z.sub.5 Z.sub.4 Z.sub.3 Z.sub.2 Z.sub.1 Z.sub.0 (base 2). To further simplify notation, the partial products and the sixteen-bit result may be written without subscripts. Thus, the eight-bit multiplication may be represented as in Table 4 below:

Generally, most of the circuitry and execution latency of a multiplier exists in row reduction logic 12 and carry propagate addition logic 13. In the preferred embodiment, no changes are made to row reduction logic 12 or carry propagate additional logic 13 of a multiplier in order to perform a tree addition. But in partial product generation logic 11, the two input logic AND gates are replaced with three input logic AND gates.

FIG. 3 shows that in partial product generation logic 11, the two input logic AND gates are replaced with three input logic AND gates. The multiplier multiplies a four-bit first multiplicand X.sub.3 X.sub.2 X.sub.1 X.sub.0 (base 2) with a four-bit second multiplicand Y.sub.3 Y.sub.2 Y.sub.1 Y.sub.0 (base 2) to produce an eight-bit result Z.sub.7 Z.sub.6 Z.sub.5 Z.sub.4 Z.sub.3 Z.sub.2 Z.sub.1 Z.sub.0 (base 2). As is understood by those skilled in the art, logic AND gates 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314 and 315 may be used to generate partial products for the multiplication. When generating partial products for multiplication, control inputs B.sub.0, B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8, B.sub.9, B.sub.10, B.sub.11, B.sub.12, B.sub.13, B.sub.14 and B.sub.15 are all set to logic 1 in order to generate partial products P.sub.0, P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5, P.sub.6, P.sub.7, P.sub.8, P.sub.9, P.sub.10, P.sub.11, P.sub.12, P.sub.13, P.sub.14 and P.sub.15.

In addition, selection of multiplicands and selection of values of control inputs B.sub.0, B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8, B.sub.9, B.sub.10, B.sub.11, B.sub.12, B.sub.13, B.sub.14 and B.sub.15 can be used to perform a tree add as is further described below.

Particularly, when a tree add is to be performed on a plurality of addends within a first register, a first value in the first register is input in place of the first multiplicand for the multiplier. The first value is a concatenation of the addends. A second value is input into the multiplier in place of the second multiplicand. Each bit of the second value is at logic zero except for a first subset of bits. The first subset of bits includes a low order bit of the second value, and includes bits of the second value which, starting from the low order bit, are at intervals which are equal to a bit length of each addend. Each of the first subset of bits is set to logic one;

For partial product rows in the multiplier which correspond to the first subset of bits, a portion of partial products in the partial product rows are forced to logic zero, so that addends for the tree addition are aligned in columns of the multiplier. The row reduction logic 12 and carry propagate addition 13 generate a result for the tree add, which is shifted to the left a number of bits equal to the bit length used by all addends less one.

FIG. 4 shows control input generation 400 which generates control inputs B.sub.0, B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8, B.sub.9, B.sub.10, B.sub.11, B.sub.12, B.sub.13, B.sub.14 and B.sub.15 for a tree add. Control input generation 400 generates control inputs B.sub.0, B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8, B.sub.9, B.sub.10, B.sub.11, B.sub.12, B.sub.13, B.sub.14 and B.sub.15, for example, during register read-out time so that generation of the control inputs does not delay operations performed by the multiplier. In addition, control input generation may be used to generate control inputs B.sub.0, B.sub.1, B.sub.2, B.sub.3, B.sub.4, B.sub.5, B.sub.6, B.sub.7, B.sub.8, B.sub.9, B.sub.10, B.sub.11, B.sub.12, B.sub.13, B.sub.14 and B.sub.15 for other operations such as a population count.

For example, in order to perform a tree add on two four-bit words, "abcd" and "efgh", using a modified eight-bit multiplier, the value "abcdefgh" is used in place of the first multiplicand X.sub.7 X.sub.6 X.sub.5 X.sub.4 X.sub.3 X.sub.2 X.sub.1 X.sub.0 (base 2). The value 00010001 is used in place of an eight-bit second multiplicand Y.sub.7 Y.sub.6 Y.sub.5 Y.sub.4 Y.sub.3 Y.sub.2 Y.sub.1 Y.sub.0 (base 2). For the top row, the control inputs for the four least significant bit positions are forced to logic zero. For the fifth row down, the control inputs for the most least significant bit positions are forced to logic zero. The row reduction logic 12 and carry propagate addition 13 generate a result for the tree add, which is shifted to the left four bits-the bit length of all addends (eight bits) less the bit length of one addend (four bits).

Table 5 below illustrates the use of a modified multiplier to perform this tree addition:

In Table 5 above, each "*" indicates a value forced to logic zero by a control input. The result of the tree add is the value "ZZZZZ". In the result register, this value is shifted four bits to the left of the least significant bit.

In order to perform a tree add on four four-bit words, "abcd," "efgh," "ijkl," "mnop,".pi.using a modified sixteen bit multiplier, the value "abcdefghijklmnop" is used in place of the first multiplicand. The value 0001000100010001 is used in place of a second multiplicand. For the top row, the control inputs for the twelve least significant bit positions are forced to logic zero. For the fifth row down, the control inputs for the eight least significant bit positions and the four most significant bit positions are forced to logic zero. For the ninth row down, the control inputs for the four least significant bit positions and the eight most significant bit positions are forced to logic zero. For the thirteenth row down, the control inputs for the twelve most significant bit positions are forced to logic zero. The row reduction logic 12 and carry propagate addition 13 generate a result for the tree add, which is shifted to the left twelve bits-the bit length of all addends (sixteen bits) less the bit length of one addend (four bits).

Table 6 below illustrates the use of a modified multiplier to perform this tree addition:

In Table 6 above, each "*" indicates a value forced to logic zero by a control input. The result of the tree add is the value "ZZZZZZ". In the result register, this value is shifted twelve bits to the left of the least significant bit.

In order to perform a tree add on two eight-bit words, "abcdefgh" and "ijklmnop," using a modified sixteen bit multiplier, the value "abcdefghijklmnop" is used in place of the first multiplicand. The value 0000000100000001 is used in place of a second multiplicand. For the top row, the control inputs for the eight least significant bit positions are forced to logic zero. For the ninth row down, the control inputs for the eight most significant bit positions are forced to logic zero. The row reduction logic 12 and carry propagate addition 13 generate a result for the tree add, which is shifted to the left eight bits--the bit length of all addends (sixteen bits) less the bit length of one addend (eight bits).

Table 7 below illustrates the use of a modified multiplier to perform this tree addition:

In Table 7 above, each "*" indicates a value forced to logic zero by a control input. The result of the tree add is the value "ZZZZZZZ". In the result register, this value is shifted eight bits to the left of the least significant bit.

As will be understood by persons of ordinary skill in the art, as a variation on the present invention, any partial product with a value of logic zero may be generated using the control input for the partial product. For example, in order to perform a tree add on two eight-bit words, "abcdefgh" and "ijklmnop," using a modified sixteen bit multiplier, the value 1111111111111111 is used in place of a second multiplicand. For all rows except the top row and the ninth row, the control inputs are forced to logic zero. For the top row, the control inputs for the eight least significant bit positions are forced to logic zero. For the ninth row down, the control inputs for the eight most significant bit positions are forced to logic zero. The row reduction logic 12 and carry propagate addition 13 generate a result for the tree add, which is shifted to the left eight bits--the bit length of all addends (sixteen bits) less the bit length of one addend (eight bits).

Table 8 below illustrates the use of a modified multiplier to perform this tree addition:

In Table 8 above, each "*" indicates a value forced to logic zero by a control input. The result of the tree add is the value "ZZZZZZZZZ". In the result register, this value is shifted eight bits to the left of the least significant bit.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, the partial products might be generated with logic equivalents of a three input logic AND gate or with a 2-to-1 multiplexor. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.