Code Breakpoint Decoder

1. Field of Invention

The present invention relates to code breakpoint decoders used for debugging software in microprocessors, and in particular, to code breakpoint decoders in which decoding of the address information is performed in multiple steps in such a manner as to reduce the amount of support circuitry and processing time needed for such function.

2. Description of the Related Art

The use of code breakpoints for debugging software in a microprocessor is well known in the art. This debugging technique allows designers and users to debug software by causing a program to pause or stop at specified points in the execution of such program so as to allow various data or status registers to be monitored or tested. However, conventional code breakpoint techniques suffer from a number of disadvantages.

One disadvantage is the fact that a relatively significant amount of circuitry is required, particularly in the decode stage of a pipeline processor, to support the breakpoint function. Another disadvantage is that the processor pipeline itself is used for determining whether an address match exists, thereby introducing a delay into the normal processing of the program. In other words, with the pipeline pausing to perform the address match determination, the actual program is not performed at normal processing speed. This not only introduces a delay into the execution of the program, but also prevents the possibility of testing for most hardware-based problems (e.g. effects due to parasitic capacitances, etc.).

Accordingly, it would be desirable to have an improved code breakpoint technique which reduces the amount of circuitry required to support this function and minimizes delays in normal program execution while performing such function.

A computer with a pipelined processor and code breakpoints for performing debug operations in accordance with one embodiment of the present invention includes a debug register, a prefetch stage, a decode stage, an execution stage, and first and second comparison stages. The debug register is for receiving and storing breakpoint information representing an address of one of a plurality of preselected instructions. The prefetch stage is for receiving and storing program address information representing one of a plurality of program instructions and in accordance therewith receiving and storing binary information representing such program instruction. The decode stage is coupled to the prefetch stage and is for receiving and decoding the stored binary information and in accordance therewith providing decoded binary information representing such program instruction. The execution stage is coupled to the decode stage and is for receiving the decoded binary information and executing an operation in accordance with such decoded binary information. The first comparison stage is coupled to the debug register and the prefetch stage and is for receiving and comparing a first portion of the stored breakpoint information and a first portion of the stored program address information and in accordance therewith providing a first address match signal which indicates whether such first portions of the stored breakpoint and program address information match one another, wherein the comparison of such first portions of the stored breakpoint and program address information is performed simultaneously with the storing by the prefetch stage of the binary information representing the program instructions. The second comparison stage is coupled to the first comparison stage, the debug register and the prefetch stage and is for receiving and comparing a second portion of the stored breakpoint information and a second portion of the stored program address information and in accordance therewith providing a second address match signal which indicates whether such first and second portions of the stored breakpoint information match the first and second portions of the stored program address information, respectively.

These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.

FIGS. 1A and 1B are a functional block diagram of an integrated circuit with a microprocessor which includes a code breakpoint design in accordance with the present invention.

FIG. 2 is a high-level functional diagram of the microprocessor in FIG. 1A.

FIG. 3 is a detailed, functional block diagram of the pipeline of the microprocessor of FIG. 1A.

FIG. 4 represents the various debug registers forming the debug section shown in the primary write stage of the pipeline of FIG. 3.

FIG. 5 is a functional block diagram of the debug registers of FIG. 4.

FIG. 6 is a signal timing diagram for the debug registers of FIG. 5.

FIG. 7 is a functional block diagram of those debug registers of FIG. 5 used for breakpoint addresses.

FIG. 8 is a functional block diagram of that portion of the match logic of FIG. 5 used for instruction address matching.

Referring to FIG. 1A, an integrated circuit 10 with a microprocessor 12 is ideally suited for using a code breakpoint design in accordance with the present invention. Referring to FIG. 2, such microprocessor 12 uses a pipeline design which includes prefetch, decoding, execution and write functions.

Referring to FIG. 3, the pipeline design for the microprocessor 12 is shown in more detail. A prefetch stage 14 fetches instructions from an instruction cache or directly from memory and provides such instructions to the decode stage 16. After decoding the instructions received from the prefetch stage 14, the decode stage 16 provides the entry microcode address for the instruction, register addresses, immediate values, displacement values and segment information to the execution stage 18. The execution stage performs the arithmetic and logic operations, as well as generate linear address information and limit checking. The primary write stage 20 and secondary write stage 22 complete the process by writing the results received from the execution stage 18 to either memory or a peripheral. The primary write stage 20 includes a debug section 100 which, as discussed in more detail below, is programmed with address information 101 for comparison with code address information 103 (for instructions) or data address information 105 (for data or operands) in accordance with which a 32-bit output 107 is provided to the execution stage 18.

As discussed in more detail below, the decode stage 16 includes a prefetch buffer 200 which is loaded via another prefetch buffer 202 in the prefetch stage 14 (or from cache or external memory). Each of these prefetch buffers 200, 202 is eight bytes wide, and together they are for receiving and storing the incoming instruction address information which will ultimately be decoded and/or compared against preprogrammed breakpoint information. Accordingly, with each prefetch buffer 200, 202 being eight bytes wide, the difference between the addresses of corresponding instruction bytes stored therein is B, where B=8 and 2.sup.N =B, and only bits ›N:0! of such addresses will vary, where N=2. (It should be appreciated that the 8-byte width of these prefetch buffers 200, 202 is not mandatory and the widths of such buffers can be selected as desired.)

Referring to FIG. 4, the debug section 100 includes four debug address registers 102, 104, 106, 108 for storing breakpoint address information and two debug control registers 110, 112 for storing control, configuration and status information. Such control, configuration and status information is identified below in Tables 1 and 2.

Referring to FIG. 5, the debug registers 102, 104, 106, 108, 110, 112 are interconnected with an input latch 114, output buffer 116, read/write control logic 118 and match logic 120. As noted above and discussed in more detail below, the debug address registers 102, 104, 106, 108 are programmed with data 101 representing address information for comparison with code address information 104 and/or data address information 105, while the debug control registers 110, 112 are programmed with data 101 representing control, configuration and status information. Additionally, the match logic 120 receives the four least significant bits (LSBs) 123 of the linear address of the first byte of the instruction whose address is being compared. Additionally, the match logic 120 receives a two-bit load signal 125, a match valid signal 127 identifying whether the match outputs 119 (discussed in more detail below) are valid, the three least significant bits 129 of the address of the operand whose address is being compared, a two-bit signal 131 representing the size of the incoming operand, a signal 133 identifying whether a write or read function is being performed, and a signal 135 identifying whether the incoming operand is valid. Based upon these input signals, the match logic 120 provides a four-bit instruction match signal 137 and a four-bit data match signal 139, depending upon whether address information for instructions or data are being compared. Further, the match logic 120 receives selected configuration, control and status information 115f from the second debug control register 112. Lastly, the match logic 120 provides select signals 117 for the debug address registers 102, 104, 106, 108 which perform a portion of the breakpoint address comparison (discussed in more detail below).

In accordance with load signals 109, 111 from the read/write control logic 118, the input latch 114 and debug registers 102, 104, 106, 108, 110, 112 store the incoming data 101 representing either address information or control, configuration or status information. The input latch 114 acts as a "master" latch, while the debug registers 102, 104, 106, 108, 110, 112 act as "slave" registers. The relative timing relationships of the load signals 109, 111 and latching action of the input latch 114 and debug registers 102, 104, 106, 108, 110, 112 are illustrated in FIG. 6. Subsequently, the information stored in the debug registers 102, 104, 106, 108, 110, 112 is provided as an output signal 115 in response to a read signal 113 from the read/write control logic 118. These output signals 115 are buffered by the buffer 116 in a time-division-multiplexed manner to produce the output 107 of the debug section 100.

Each of the breakpoint debug address registers 102, 104, 106, 108 also receives the aforementioned code address 103 and data address 105 signals. As discussed in more detail below, the 29 most significant bits (MSBs) of each of these signals 103, 105 are selectively compared with the corresponding bits of the programmed address information 101. If a match exists between such bits, a match signal 119 is asserted and provided to the match logic 120. Also provided to the match logic 120 are the three LSBs 121 of the programmed address information 101.

Referring to FIG. 7, the storage and comparison functions of the breakpoint debug address registers 102, 104, 106, 108 can be better understood. The programmed address information 101 is stored in a register 122 in accordance with the load signal 111. Of this stored information, the least significant three bits 121 are provided for the match logic 120 (FIG. 5), while the 29 most significant bits 141 are provided to a digital comparator 126. Meanwhile, all 32 bits are provided to a buffer 128 for outputting in accordance with the read control signal 113.

Of the code address information 103 and data address information 105, the 29 MSBs 103a, 105a of each are provided to a multiplexor 124 which, in accordance with the select signal 117 from the match logic 120, provides one set 143 of such bits to a digital comparator 126. These bits 143 are compared with the 29 MSBs 141a of the programmed address information 141 and, if a match is found to exist, the match signal 119 is asserted.

Referring to FIG. 8, operation of that portion 120a of the match logic 120 which determines whether an instruction breakpoint match has occurred can be better understood. The match signal bit 119 is stored in one of two latches 130, 132 in accordance with the two states 125a, 125b of the load signal 125. In other words, the match signal bit 119 is loaded into the first 130 and second 132 latches during assertion of the first 125a and second 125b states, respectively, of the load signal 125. During a prefetch request, the first 125a and second 125b states of the load signal 125 are asserted when the state of bit 3 of the prefetch pointer is a logic 0 and a logic 1, respectively. One of these stored bits 145, 147 is then selected by a multiplexor 134 in accordance with the most significant bit (bit 3) 123b of the four LSBs 123 of the instruction address, i.e. the address of the first byte of the instruction decoded by the decode stage 16 (FIG. 3).

The three LSBs 121 of the programmed address information 101 are compared in a three-bit comparator 136 with the three LSBs 123a of the instruction address 123. The resulting multiplexor output 149 and comparator output 121 are then logically ANDed with the match valid signal 127 and the multiplexor select signal 117 in an AND gate 138 to produce the instruction match signal 137.

When the instruction reaches the execution stage 18, and such instruction is to be executed, the code breakpoint is then taken.

The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Ser. No. 08/451,319, entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA"; U.S. patent application Ser. No. 08/451,965, entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES"; U.S. patent application Ser. No. 08/453,076, entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS (DMA) CONTROLLER"; U.S. patent application Ser. No. 08/452,001, entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH"; U.S. patent application Ser. No. 08/451,503, entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION"; U.S. patent application Ser. No. 08/451,924, entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING"; U.S. patent application Ser. No. 08/451,444, entitled "BARREL SHIFTER"; U.S. patent application Ser. No. 08/451,204, entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH"; U.S. patent application Ser. No. 08/451,195, entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH"; U.S. patent application Ser. No. 08/451,571, entitled "METHOD FOR PERFORMING SIGNED DIVISION"; U.S. patent application Ser. No. 08/452,162, entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER"; U.S. patent application Ser. No. 08/451,434, entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT"; U.S. patent application Ser. No. 08/451,535, entitled "NON-ARITHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT"; U.S. patent application Ser. No. 08/445,563, entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION"; U.S. patent application Ser. No. 08/450,153, entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" now U.S. Pat. No. 5,546,353; U.S. patent application Ser. No. 08/451,495, entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER"; U.S. patent application Ser. No. 08/451,219, entitled "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK"; U.S. patent application Ser. No. 08/451,214, entitled "INCREMENTOR/DECREMENTOR" now U.S. Pat. No. 5,583,453; U.S. patent application Ser. No. 08/451,150, entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY"; U.S. patent application Ser. No. 08/451,198, entitled "CODE BREAKPOINT DECODER"; U.S. patent application Ser. No. 08/445,569, entitled "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS"; U.S. patent application Ser. No. 08/445,564, entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR"; U.S. patent application Ser. No. 08/452,306, entitled "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE"; U.S. patent application Ser. No. 08/452,080, entitled "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486.TM. MICROPROCESSOR COMPATIBLE POP INSTRUCTION"; U.S. patent application Ser. No. 08/450,154, entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY"; U.S. patent application Ser. No. 08/451,742, entitled "METHOD OF IMPLEMENTING FAST 486.TM. MICROPROCESSOR COMPATIBLE STRING OPERATION"; U.S. patent application Ser. No. 08/452,659, entitled "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID"; U.S. patent application Ser. No. 08/451,507, entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS"; U.S. patent application Ser. No. 08/451,420, entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT"; U.S. patent application Ser. No. 08/452,365, entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER"; U.S. patent application Ser. No. 08/451,744, entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE"; U.S. patent application Ser. No. 08/451,206, entitled "CONFIGURABLE POWER MANAGEMENT SCHEME"; U.S. patent application Ser. No. 08/452,350, entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE"; U.S. patent application Ser. No. 08/452,094, entitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECTION CIRCUIT"; U.S. patent application Ser. No. 08/451,503, entitled "IN-CIRCUIT EMULATOR STATUS INDICATOR CIRCUIT"; U.S. patent application Ser. No. 08/450,156, entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY"; U.S. patent application Ser. No. 08/450,726, entitled "INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" now U.S. Pat. No. 5,541,935; U.S. patent application Ser. No. 08/445,568, entitled "DECODE BLOCK TEST METHOD AND APPARATUS".

Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.