Inverse Quantizer for Use in MPEG-2 Decoder

The invention relates to a video signal decoding apparatus; and, more particularly, to an inverse quantizer for use in an MPEG-2 decoder.

In various electronic applications such as high definition TV and video telephone systems, a video signal may be transmitted in a digital form. When the video signal comprising a sequence of video "frames" is expressed in a digital form, there occurs a substantial amount of digital data: for each line of a video frame is defined by a sequence of digital data elements referred to as "pixels". Since, however, the available frequency bandwidth of a conventional transmission channel is limited, in order to transmit the substantial amounts of digital data through the fixed channel, a video signal encoding apparatus is normally used to compress the digital data.

Conventional video signal encoding apparatus typically includes a transform coder, e.g., DCT (Discrete Cosine Transform) coder, which sequentially converts a plurality of blocks of, e.g., 8.times.8, pixels contained in a video frame signal into a plurality of blocks of 8.times.8 transform coefficients. The blocks of transform coefficients are sequentially processed with a quantizer wherein they are converted into quantized transform coefficients as set forth in the video coding syntax of ISO/IEC 13818-2, Committee Draft prepared by Motion Picture Expert Group (MPEG), which is also known as an MPEG-2 scheme.

Actually, MPEG-2 regulates an inverse quantizer, for use in a video signal decoder, for inverse quantizing QF›V!›U!, i.e., a quantized transform coefficient, inputted thereto from, e.g., a variable length decoder and an inverse scanner on a block-by-block basis, QF›V!›U! being determined from an encoded data stream provided to the decoder from a corresponding encoder. The inverse quantizer provides inverse quantized transform coefficient F"›V!›U! which is determined as follows:

wherein V and U represent a position in an 8.times.8 block; W›V!›U! is an element of an 8.times.8 weight matrix corresponding to QF›V!›U!, the weight matrix being predefined or downloaded from the encoder; the quantizer.sub.-- scale is determined as shown in Table 1 hereof based on "quantizer.sub.-- scale.sub.-- code" and "q.sub.-- scale.sub.-- type" which are obtained from the encoded data stream; "/" represents an integer division with truncation of the result toward Zero; and Sign(X) is a function of a variable X defined as: ##EQU1##

As specified in MPEG-2 scheme, QF›V!›U! ranges from -2047 to 2047 and, therefore, "2QF›V!›U!+K" may be represented by using 13 bits; W›V!›U! is an 8-bit integer; and the quantizer.sub.-- scale ranges from 1 to 112 and, therefore, can be represented with 7 bits.

After the quantization, the inverse quantized transform coefficient F"›V!›U! is subject to other procedures such as saturation, mismatch control, inverse DCT, and so on.

Referring to FIG. 1, there is shown a block diagram of a conventional inverse quantizer in accordance with the MPEG-2 scheme described above, which includes two multipliers 20 and 30, a quantizer.sub.-- scale providing block 10, and a divider 40.

The quantizer.sub.-- scale providing block 10 provides the quantizer.sub.-- scale as specified in Table 1, to the multiplier 20 in response to the quantizer.sub.-- scale.sub.-- code and the q.sub.-- scale.sub.-- type which are decided from the encoded data stream and provided thereto. From Table 1, it can be seen that the quantizer.sub.-- scale providing block 10 may be implemented as a lookup table, equivalent to a 64.times.7 ROM(Read Only Memory).

Then, the 7-bit quantizer.sub.-- scale is multiplied with the 8-bit W›V!›U! at the multiplier 20, to thereby provide a 15-bit quantization step size to the multiplier 30. An input value "2QF›V!›U!+K" is coupled to the multiplier 30 and multiplied with the quantization step size therein, to thereby provide 28-bit data to the divider 40. At the divider 40, the 28-bit data is divided by 2.sup.5, to thereby provide the 23-bit inverse quantized transform coefficient.

As described above, the conventional inverse quantizer uses multipliers and a divider which can deal with data having many bits, to thereby render the production cost thereof rather high.

It is, therefore, a primary object of this invention to provide an improved inverse quantizer which is constructed with multipliers dealing with a smaller number of bits, to thereby lower the implementation cost thereof.

In accordance with the invention, there is provided an apparatus, for use in an MPEG-2 video signal decoder, for providing an N1-bit inverse quantized transform coefficient F in response to an N2-bit input value MQF, according to

wherein the quantizer.sub.-- scale is an integer ranging from 2.sup.0 to 2.sup.M -1 M being a positive integer, and W is a (N1+5-N2-M)-bit predefined value, the apparatus comprising:

a quantizer.sub.-- scale providing block for generating a (M-L)-bit modified quantizer.sub.-- scale and a selection signal based on the quantizer.sub.-- scale, L being an integer ranging from 1 to (M-1);

a first multiplier for multiplying the modified quantizer.sub.-- scale with W, to provide a (N1+5-N2-L)-bit quantization step size;

a second multiplier for multiplying the N2-bit input value with the quantization step size, to provide an (N1+5-L)-bit first value;

a bit appending block for appending L zero bits to the first value, to provide (L+1) (N1+5)-bit second values;

a multiplexor for selecting one of the (L+1) (N1+5)-bit second values in response to the selection signal; and

a divider for dividing the selected second value provided from the multiplexor by 2.sup.5, to thereby provide the N1-bit inverse quantized transform coefficient.

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional inverse quantizer;

FIGS. 2A and 2B show block diagrams of an inverse quantizer in accordance with a first preferred embodiment of the present invention; and

FIG. 3 describes a block diagram of an inverse quantizer in accordance with a second preferred embodiment of the present invention.

Referring back to Table 1, it is noted that the quantizer.sub.-- scale can be represented with less than 6 bits except when it has one of underlined values, 64, 72, 80, . . . , 112 (or equivalently, the quantizer.sub.-- scale.sub.-- code is one of values 25 to 31 and the q.sub.-- scale.sub.-- type is "1"). In addition, all of the underlined values are multiples of 2. Therefore, if quantizer.sub.-- scale/2 is used instead of the quantizer.sub.-- scale for the underlined cases, quantizer.sub.-- scale can be expressed as 6 bits. Accordingly, Eq. (1) can be modified as follows: ##EQU2##

Referring to FIG. 2A, there is shown a block diagram of an inverse quantizer 200 in accordance with a first preferred embodiment of the present invention, which selectively performs the operation given in Eq. (2A) or (2B). Similar to the conventional inverse quantizer shown in FIG. 1, it includes a quantizer.sub.-- scale providing block 110, two multipliers 120 and 130 and a divider 140. The quantizer.sub.-- scale providing block 110 provides a modified quantizer.sub.-- scale (quantizer.sub.-- scale' in Eqs. (2A) and (2B)) instead of the quantizer.sub.-- scale given in Table 1 to the multiplier 120, in response to the quantizer.sub.-- scale.sub.-- code and the q.sub.-- scale.sub.-- type, wherein the modified quantizer.sub.-- scale for any of the underlined cases (case 2) in Table 1 is given by the quantizer.sub.-- scale therein divided by 2 and it is identical to the quantizer.sub.-- scale in Table 1 for the remaining cases (case 1). Accordingly, all values of the modified quantizer.sub.-- scale can be represented with 6 bits. The quantizer.sub.-- scale providing block 110 also provides a selection signal identifying either of the case 1 or 2 to a multiplexor 134. The quantizer.sub.-- scale providing block 110 may include a lookup table, equivalent to a 64.times.6 ROM and a supplementary circuitry for providing the selection signal.

Then, the 6-bit modified quantizer.sub.-- scale is multiplied with 8-bit W›V!›U! at the multiplier 120, to thereby provide a 14-bit quantization step size to the multiplier 130. The 13-bit "2QF›V!›U!+K" is inputted to the multiplier 130 and multiplied by the 14-bit quantization step size therein, to thereby provide 27-bit data to a bit appending block 132. The bit appending block 132 outputs two 28-bit data (which will be referred to as an MSB (Most Significant Bit) appended data and an LSB (Least Significant Bit) appended data) to a multiplexor 134 by appending a zero bit, i.e., a bit having "0" value, in front of an MSB and next to an LSB, respectively, of the 27-bit data provided from the multiplier 130. For example, if "101 11010001 01101010 11001100" is provided to the bit appending block 132, the MSB appended data and the LSB appended data are "0101 11010001 01101010 11001100" and "1011 10100010 11010101 10011000", respectively, wherein the underlined bit represent the appended bit. It is noted that while the MSB appended data is identical to the original data before appending, the LSB appended data is equivalent to the original data multiplied by 2.

At the multiplexor 134, one of the two 28-bit data is selected in response to the selection signal provided from the quantizer.sub.-- scale providing block 110. Specifically, for the case 2, the LSB appended data is selected, and for the case 1, the MSB appended data is selected. Since the bit appending block 132 and the multiplexor 134 compensate the effect of division by 2 of the quantizer.sub.-- scale for the case 2, the 28-bit data provided from the multiplexor 134 is identical to the output of the multiplier 30 shown in FIG. 1.

At the divider 140, the 28-bit data is divided by 2.sup.5, to thereby provide the 23-bit inverse quantized data F"›V!›U!.

As described above, by using the 6-bit modified quantizer.sub.-- scale instead of the 7-bit quantizer scale, the two multipliers 120 and 130 can be implemented with a 6-bit by 8-bit multiplier and a 14-bit by 13-bit multiplier, respectively, which can be more easily constructed than the conventional 7-bit by 8-bit and 15-bit by 13-bit multipliers.

In a similar manner, Eq. (1) can be further modified as follows: ##EQU3##

Referring to FIG. 2B, there is shown an inverse quantizer 300 which performs the operation given in one of Eqs. (3A) to (3C). The functions of blocks included in the inverse quantizer 300 is similar to those of the corresponding blocks shown in FIG. 2A. However, in the inverse quantizer 300, a modified quantizer.sub.-- scale (quantizer.sub.-- scale") provided from the quantizer.sub.-- scale providing block 210 is represented with 5 bits, and therefore, the quantization step size provided from the multiplier 220 is represented with 13 bits. In addition, the bit appending block 232 provides three 28-bit data to a multiplexor 234, by appending 2 zero bits next to an LSB, 1 bit next to an LSB and 1 bit in front of an MSB, and 2 bits in front of an MSB, respectively, of the 26-bit data provided from the multiplier 230. At the multiplexor 234, one of the three 28-bit data is selected in response to a selection signal provided from the quantizer.sub.-- scale providing block 210.

At the divider 240, the 28-bit data is divided by 2.sup.5, to thereby provide the 23-bit inverse quantized transform coefficient F"›V!›U!. By using the 5-bit modified quantizer.sub.-- scale instead of the 7-bit quantizer.sub.-- scale, the two multipliers 220 and 230 can be implemented with a 5-bit by 8-bit multiplier and a 13-bit by 13-bit multiplier, respectively, which can be more easily constructed than those shown in FIG. 1 or 2A.

In a similar manner, it is possible to modify the structure of the inverse quantizer so that a 4-bit modified quantizer.sub.-- scale may be used by classifying Table 1 into 4 cases.

Referring to FIG. 3, there is shown a block diagram of an inverse quantizer 400 in accordance with a second embodiment of the present invention. In this embodiment, Eq. (1) is modified as follows: ##EQU4## The inverse quantizer 400 includes a quantizer.sub.-- scale providing block 310, two multipliers 320 and 330 and a division block 340, wherein the two multipliers 320 and 330 may be implemented as a 6-bit by 8-bit multiplier and a 14-bit by 13-bit multiplier, respectively.

The quantizer.sub.-- scale providing block 310 provides a 6 bit modified quantizer.sub.-- scale (quantizer.sub.-- scale' in Eqs. (4A) and (4B)) to the multiplier 320 in response to the quantizer.sub.-- scale.sub.-- code and the q.sub.-- scale.sub.-- type. It also provides a selection signal to the division block 340 which is identical to the selection signal shown in FIG. 2A.

Then, the 6-bit modified quantizer.sub.-- scale is multiplied with 8-bit W›V!›U! at the multiplier 320, to thereby provide a 14-bit quantization step size to the multiplier 330. The 13-bit "2QF›V!›U!+K" is inputted to the multiplier 330 and multiplied with the 14-bit quantization step size therein, to thereby provide 27-bit data to the division block 340.

At the division block 340, the 27-bit data is divided by either 2.sup.5 or 2.sup.4 in response to the selection signal provided from the quantizer.sub.-- scale providing block 310, to thereby provide the 23-bit inverse quantized data F"›V!›U!. Specifically, for case 1, the 27-bit data is divided by 2.sup.5 to form a 22-bit data and a zero bit is appended in front of an MSB thereof, to form the 23-bit inverse quantized data F"›V!›U!; and for case 2, the 27-bit data is divided by 2.sup.4 to form the 23-bit inverse quantized data F"›V!›U!.

Similar to the first embodiment, it is possible to modify the structure of the inverse quantizer 400 so that a 5 or 4-bit modified quantizer.sub.-- scale may be used by classifying Table 1 into 3 or 4 cases.

As described above, by modifying the equation for the inverse quantization, the inverse quantizer may be constructed by using less complicated multipliers, to thereby reduce the overall cost of production.

While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the spirit and scope of the present invention as set forth in the following claims.