Low Power Low Voltage Level Shifter

This invention relates to semiconductor devices, and more particularly, to a clock generator circuit.

Clock generator circuits for timing various logic circuits are well known in the art. A clock generator generally includes an oscillating signal source and a voltage level shifter. In many clock generator circuits, a crystal oscillator is used as the oscillating signal source and an inverter is used as the voltage level shifter. The crystal oscillator generates a sine wave type of oscillating signal which is connected to the input of the inverter. Based on the oscillating signal, the inverter in the clock circuit shifts or switches between a logic zero and logic one. One disadvantage of this method, however, is that because the oscillating signal rises and falls at a relatively slow rate, the switching time of the inverter is very long. A further disadvantage is that the slow switching time of the clock circuit propagates throughout the logic circuits being driven by the clock circuit. This causes a large power dissipation in those logic circuits which is highly undesirable. Because of the large power dissipation, this type of clock generators are especially unsuitable for battery-powered portable electronic devices such as digital watches and notebook computers.

It is therefore desirable to provide a clock generator circuit with a fast switching time. It is also desirable to provide such clock generator circuit without increasing the current drain during its switching period.

According to the principles of the present invention, a low power, low voltage level shirker is provided. The voltage level shifter includes a first switching circuit, and a second switching circuit. The first switching circuit has a first input terminal for receiving a first oscillating signal. Based on the first oscillating signal, the first switching circuit switches its output between a first voltage level and a second voltage level. The second switching circuit has a second input terminal connected to the output terminal of the first switching circuit. The second switching circuit also has a third input terminal for receiving a second oscillating signal which is out of phase with the first oscillating signal.

In a preferred embodiment, the first switching circuit is an inverter circuit having a pair of transistors connected in series. Each transistor is biased to a threshold voltage and is coupled to a capacitor. The biasing means and the capacitor shifts the first oscillating signal to a predetermined DC voltage at the control terminal of each transistor. The second switching circuit includes an inside pair of transistors and an outside pair of transistors all of which are connected in series. Each of the outside pair of transistors is biased to a threshold voltage and is coupled to a capacitor. The biasing means and the capacitor shifts the second oscillating signal to a predetermined DC voltage at the control terminal of each of the outside pair of transistors. The output of the first switching circuit is connected to the control terminals of the inside pair of transistors. Based on the input signals received, the second switching circuit generates an output signal that switches between a third voltage level and a fourth voltage level at a selected rate and frequency.

FIG. 1 is a schematic circuit diagram of an AC coupled inverter circuit according to the prior art.

FIG. 2 is a graph of voltage levels over time of various nodes on the inverter circuit of FIG. 1.

FIG. 3 is a block diagram of a two stage voltage level shifter according to the present invention.

FIG. 4 is a detailed circuit schematic of one preferred embodiment of the two stage voltage level shifter of FIG. 3.

FIG. 5 is a graph of voltage levels over time of various nodes on the voltage level shifter of FIG. 3.

FIG. 1 is a schematic circuit diagram of an AC coupled inverter circuit 10 according to the prior art. The inverter or switching circuit 10 includes a PMOS transistor 12 and NMOS transistor 14 connected in series with each other. A current mirror circuit well known in the art is used to bias the two transistors 12 and 14. The current mirror circuit includes a PMOS transistor 16 and NMOS transistor 18 connected in series, and a PMOS transistor 20 and NMOS transistor 22 also connected in series with each other. The gate and drain terminals of transistor 18 are shorted together. The gate and drain terminals of transistor 20 are also shorted together. The gate terminals of transistors 18 and 22 are connected to each other. The bias voltage V.sub.bias at the gate terminal of transistor 16 is typically slightly less than V.sub.CC -V.sub.tp (threshold voltage of a PMOS transistor) of transistor 16. For example, if V.sub.tp is equal to -1 volt, and V.sub.CC equals 3 volts, V.sub.bias is equal to approximately 1.8 volt. When properly biased, the voltage level at node b1 is V.sub.CC -V.sub.tp, which in this example is 2 volts. The voltage level at node b2 is V.sub.tn (threshold voltage of an NMOS transistor) of transistor 18 which may be approximately 0.7 volt. Impedance device R.sub.1 is connected to the gate terminal of transistor 20 and resistor R.sub.2 is connected to gate terminals of transistors 18 and 22. Both impedance devices R.sub.1 and R.sub.2 have very high resistance values, i.e., 1 giga-ohm, which are formed by lightly doped or undoped polysilicon to electrically form diodes, as is well known in the art. Other impedance devices, such as resistors are also used. A capacitor C.sub.n1 is placed between an input terminal node in and node n1, and a capacitor C.sub.n2 is placed between node in and node n2. A capacitive load of the logic circuits 24 being driven by the inverter circuit 10 is shown as C.sub.L. Hereinafter, assume that for simplicity V.sub.tp is -1 volt and V.sub.tn is 1 volt for all transistors. Further assume that V.sub.CC is 5 volts.

FIG. 2 is a graph of voltage levels over time of various nodes on the inverter circuit 10 of FIG. 1. Referring to both FIGS. 1 and 2, if properly biased, V.sub.b1 is at 4 volts and V.sub.b2 at 1 volt. As shown in FIG. 2, the voltage level at node n1 oscillates along a DC voltage of V.sub.CC -V.sub.tp due to capacitive coupling of input voltage V.sub.in with capacitor C.sub.n1. Similarly, the voltage level at node n2 oscillates along a DC voltage of V.sub.tn also due to capacitive coupling of input voltage V.sub.in with capacitor C.sub.n2. The AC-coupled inverter circuit 10 operates as follows. When V.sub.n1 is at 4.5 volts and V.sub.n2 is at 1.5 volts, transistor 12 is off since V.sub.gs of -0.5 volt is above the threshold voltage of -1 volt required to turn on transistor 12. On the other hand, transistor 14 is on since V.sub.gs of 1.5 volt is higher than the threshold voltage of 1 volt required to turn on transistor 14. Thus, V.sub.out is grounded through transistor 14 to a logic zero. As V.sub.n1 decreases and crosses the 4 volt level, transistor 12 begins to turn on while transistor 14 begins to turn off. When V.sub.n1 is at 3.5 volts and V.sub.n2 is at 0.5 volts, transistor 14 is off and transistor 12 is on. Thus, V.sub.out switches from a logic zero to logic one through transistor 12 which charges capacitive load C.sub.L to approximately 5 volts.

The problem recognized by the applicant is that because the oscillating input signal V.sub.in rises and falls at a relatively slow rate, the switching time of the inverter circuit 10 is very long. The slow switching time propagates throughout the logic circuits 24 being driven by the inverter circuit 10 and causes a large power dissipation in those logic circuits which is highly undesirable. Because of the large power dissipation, this type of clock generators 10 are especially unsuitable for battery-powered portable electronic devices such as digital watches and notebook computers.

FIG. 3 is a block diagram of a voltage level shifter according to principles of the present invention. The voltage level shifter uses a first and second stage level shifter connected in series. A second switching circuit 30 is connected to the output of a first switching circuit 10. The first stage 10 receives the oscillating voltage V.sub.in1 and outputs a level shifted voltage at terminal V.sub.01. The input voltage V.sub.in1 is an oscillating signal causing the output V.sub.01 to oscillate between logic high and logic low states. The output V.sub.01 from the first stage voltage shifter is input to control terminals of a second stage voltage shifter 30. The second stage voltage shifter 30 also receives Vin.sub.2 as an input to control terminals. The second stage voltage shifter 30 outputs a signal V.sub.02 for providing the clock signals to the various logic circuits 24 which make up the integrated circuit.

According to the present invention, the output signal V.sub.02 rapidly switches from a high state to low state providing an improved clock signal with faster rise time and fall time than the initial output signal V.sub.01. This improved performance is obtained by ensuring that the signals Vin.sub.1 and Vin.sub.2 are out of phase with each other and preferably are at exactly 180.degree. out of phase.

According to one embodiment ,of the present invention, the first stage voltage shifter 10 corresponds to the prior art voltage shifter as shown in FIG. 1. The second stage voltage shifter 30 is comprised of a voltage shifter having two input signals coupled to two respective control signals with a second oscillator input Vin.sub.2 providing the final switching signal to the output terminal V.sub.02.

FIG. 4 shows one preferred embodiment of the detailed circuits which may be used in the first stage voltage shifter and the second stage voltage shifter according to the present invention. According to this embodiment, the first stage voltage shifter 11 is constructed more simply to include impedance devices R.sub.5 and R.sub.6 that bias the gates of the respective transistors 13 and 15 to the desired level based on principles previously explained herein. The impedance devices R.sub.5 and R.sub.6 may be simple resistors or, alternatively, may be high impedance device polysilicon load resistors which electrically appear as reverse junction diodes, a MOS transistor or other acceptable high impedance devices. Of course, the back-to-back diode structure as shown in FIG. 1 for R.sub.1 and R.sub.2 may also be used.

The second switching circuit 30 includes two PMOS transistors 32 and 34 and two NMOS transistors 36 and 38 all of which are connected in series with each other as shown in FIG. 3. The drain terminals of transistors 34 and 36 define an output node V.sub.02. A capacitive load C.sub.L of the logic circuits 24 is represented by a capacitor C.sub.L which is shown as coupled between the output node V.sub.02 and ground. The output voltage V.sub.01 of the inverter circuit 10 is connected to the gate terminals of transistors 34 and 36. A second input signal in2 is coupled to the gate terminals of transistors 32 and 38 through capacitors C.sub.n3 and C.sub.n4 respectively. The voltage level V.sub.in2 is out of phase with V.sub.in1 and preferably is 180 degrees out of phase with each other. As in FIG. 1, nodes b1 and b2 are connected to the gate terminals of transistors 20 and 18, respectively. Bias resistor R.sub.3 is connected between node b1 and node n3 to provide a bias voltage of approximately 4 volts at node n3. Similarly, bias resistor R.sub.4 is connected between node b2 and node n4 to provide a bias voltage of approximately 1 volt at node n4.

FIG. 5 is a graph of voltage levels over time of various nodes on the voltage level shifter of FIG. 3. Referring to both FIGS. 3 and 4, the voltage level shifter according to the present invention operates as follows. When V.sub.in2 is at 0.5 volt, V.sub.n3 is at 4.5 volts and V.sub.n4 is at 1.5 volts due to the biasing voltages V.sub.b1 and V.sub.b2. In this state, transistor 32 is off since V.sub.gs of -0.5 volt is above the threshold voltage of transistor 32. Transistor 38, on the other hand, is on because V.sub.gs of 1.5 volts is greater than the threshold voltage of transistor 38. With V.sub.in2 at 0.5 volts, V.sub.in1 is at -0.5 volt (phase shift of 180 degrees) and output voltage V.sub.01 is at logic high or 5 volts. The 5 volt signal turns off transistor 34 and turns on transistor 36. Thus, the output V.sub.02 of the voltage level shifter circuit is at logic zero or 0 volt due to the conductive path to ground provided by transistors 36 and 38.

As V.sub.in2 begins to fall from +0.5 volt to -0.5 volt, transistors 32 and 34 turn on and transistors 36 and 38 turn off in the following sequence. As V.sub.in2 falls below zero volt, transistor 32 turns on while transistor 38 turns off. Shortly thereafter, V.sub.01 begins to fall from 5 volts to 0 volt. As V.sub.01 falls below 4 volts, transistor 34 turns on. As V.sub.01 falls further and below 1 volt, transistor 36 turns off. Once both transistors 36 and 38 are turned off and transistors 32 and 34 are turned on, V.sub.02, previously at logic low, switches to logic high through a conductive path provided by the two transistors 32 and 34 which rapidly charges the capacitive load C.sub.L.

As V.sub.in2 begins to rise from -0.5 volt to +0.5 volts, the reverse occurs. As V.sub.in2 rises above zero volt, transistor 32 turns off while transistor 38 turns on. Shortly thereafter, V.sub.01 begins to rise from 0 volt to 5 volts. As V.sub.01 rises above 1 volt, transistor 36 turns on. As V.sub.01 rises further and above 4 volts, transistor 34 turns off. Once both transistors 36 and 38 are turned on and transistors 32 and 34 are turned off, V.sub.02, previously at logic high, switches to logic low through a conductive path to ground provided by transistors 36 and 38.

Persons of ordinary skill in the art will appreciate that transistors 32 and 38 control charge/discharge of current at the output terminal node voltage V.sub.02 and the output voltage at node V.sub.01 controls the switching time. Since input voltages of transistors 34 and 36 swings from 0 to 5 volts with a relatively fast transient signal, the switching time of logic state at the output terminal node V.sub.02 is very fast. Further, because at least one transistor among the transistors 32-38 is off at any given time, switching operation of the voltage level shifter is accomplished without additional DC current or at most a very small leakage current.

While only one embodiment is shown and described, many other embodiments are possible within the spirit of the invention. For example, while the oscillating input signal is described as a sine wave type, other types including square wave types may also be used as an input to the voltage level shifter. Accordingly, the scope of the invention is not limited to the foregoing specification, but instead is given by the appended claims, along with their full range of equivalents.