Flash Memory Cell and Method of Making the Same

The present invention relates to a flash memory cell and method of making the same, more particularly to a flash memory cell and method of making the same which can prevent reduction of a coupling ratio by forming an insulating spacer of ONO (oxide-nitride-oxide) structure at the side walls of the floating gate.

In general, non-volatile memory cells such as flash EEPROM (Electrically Erasable Programmable Read Only Memory) cell, EPROM, etc., which have both functions of electrical program and erasure can be classified into a stack-gate structure or a split-gate structure.

As shown in FIG. 1A, a flash memory cell having a conventional stack-gate structure is created by sequentially forming a tunnel oxide film 5, a floating gate 6, a dielectric film 11 and a control gate 12 on a silicon substrate 1, and thereafter, forming source and drain regions, 7 and 8, in the silicon substrate 1. As shown in FIG. 1B, a flash memory cell having a conventional split-gate structure is created by sequentially forming a tunnel oxide film 5, a floating gate 6, a dielectric film 11 and a control gate 12 on a silicon substrate 1, and thereafter, forming source and drain regions, 7 and 8, in the silicon substrate 1, wherein said control gate 12 being extended to the drain region 8, and a select gate oxide film 9 being formed between said extended control gate 12 and said drain region 8. Though the two memory cells are same in function in that they perform programming and erasure operations by injecting hot electrons into the floating gate or discharge them therefrom, the flash memory cell having the split-gate structure can effectively reduce the amount of current dissipating into the drain region 8 and thereby has a high efficiency of program and a low consumption of power since it uses a source side injection method by which hot electrons generating from the source region 7 are injected into the floating gate 6. As shown in FIG. 1B, the flash memory cell employing a source side injection method is divided into a stack-gate portion A and a select-gate portion B. A channel is formed between the stack-gate portion A and the select-gate portion B. The width of the channel C is determined by the thickness of the dielectric film 11 formed at the side walls of the floating gate 6. Therefore, the thickness of the dielectric film 11 greatly affects the program characteristics and the read current levels. In addition, the thickness of the dielectric film 11 formed at the side walls of the floating gate 6 must be less than 600 .ANG.. Especially, in order to improve the read current level, the thickness of the dielectric film 11 must be thin so that the leakage of electrons between the floating gate 6 and the control gate 12 could be prevented completely. In a prior art, the dielectric film 11 is formed through the oxidation process after the floating gate 6 is formed. However, the dielectric film enlarges by a high rate of oxidation from a polysilicon into which phosphor (P) is doped, therefore, it is difficult to control the thickness thereof, resulting in low dielectric characteristics. Also, the width of the floating gate 6 is reduced as its side walls are oxidized, resulting in reduction of coupling ratio which adversely affects the program and a read characteristics.

Accordingly, the purpose of the present invention is to provide a flash memory cell and method of making the same which can overcome the above mentioned problem by forming an insulating spacer of ONO (oxide-nitride-oxide) structure at the side walls of the floating gate.

To achieve the above purpose, a flash memory cell according to the invention comprises: a floating gate and a tunnel oxide film which are formed at a selected region on a silicon substrate; an insulating film spacer formed at both sides of the floating gate; a dielectric film formed on the entire surface including the insulating film spacer; a source region formed in the silicon substrate, wherein the source region is extended to a portion of the silicon substrate under the tunnel oxide film; a drain region formed in the silicon substrate; and a control gate formed on the portion of the dielectric film which is located on the floating gate and is extended up to the portion of the dielectric film formed on the drain region.

A method of making a flash memory cell, comprises the steps of: sequentially forming a tunnel oxide film, a first polysilicon layer and an oxide film on a silicon substrate; patterning the oxide film and the first polysilicon layer to form a floating gate; forming source and drain regions in the silicon substrate; forming an insulating film on the entire surface of the silicon substrate after forming the source and drain regions; forming an insulating film spacer at the side walls of the the oxide film and floating gate film through an isotropic etching process; removing a portion of the oxide film remaining on the floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on the floating gate; and forming a second polysilicon layer on the entire surface after performing the thermal oxidation process, and patterning the second polysilicon layer to form a control gate.

For fuller understanding of the nature and objects of the invention, reference should be had to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A shows a sectional view of a flash memory cell having a conventional stack-structure;

FIG. 1B shows a sectional view of a flash memory cell having a conventional split-gate structure; and

FIG. 2A through FIG. 2G show sectional views for explaining a method of making a flash memory cell according to the present invention.

Similar reference characters refer to similar parts through the several views of the drawings.

FIG. 2A through FIG. 2G show sectional views for explaining the method of making a flash memory cell according to the first embodiment of present invention.

FIG. 2A shows a sectional view in which a tunnel oxide film 2, a first polysilicon layer 3 and an oxide film 4 are sequentially formed on the entire surface of a silicon substrate 10, with the tunnel oxide film 2 being formed 50 through 100 .ANG. in thickness, the oxide film 4 being formed 300 through 600 .ANG. in thickness and phosphor (P) being doped into the polysilicon layer 3.

FIG. 2B shows a sectional view in which, after the oxide film 4 and the first polysilicon layer 3 are patterned to form a floating gate 3A through the photolithography and etching process using a mask for the floating gate electrode, source and drain regions, 7A and 8A, respectively, are formed in the silicon substrate 10 through the ion injection process using a given mask.

FIG. 2C shows a sectional view in which, after an insulating film is formed on the entire surface after forming the source and drain regions 7A and 8A an insulating spacer 11A is formed at the side walls of the patterned oxide film 4 and the floating gate 3A by performing an isotropic etching process until the silicon substrate 10 is exposed. The insulating film is formed in an ONO (Oxide-Nitride-Oxide) structure in which an underlying oxide film, a nitride film and an upper oxide film are sequentially stacked, or in an ON (Oxide-Nitride) structure, in which an oxide film and a nitride film are sequentially stacked, wherein the underlying oxide film is formed as a thermal oxide film or a CVD (Chemical Vapor Deposition) oxide film. The width of the insulating film spacer is 50 through 100 .ANG..

FIG. 2D shows a sectional view in which the oxide film 4 remaining on the floating gate 3A is removed by a wet etching process. However, when the oxide film 4 was not formed in FIG. 2A, the wet etching process is not required.

FIG. 2E shows a sectional view in which a thermal oxidation process is performed to form a select-gate oxide film 19 on the exposed silicon substrate 10 in FIG. 2D. The oxide film also formed on the floating gate 3A can be used as the dielectric film 14.

FIG. 2F shows a sectional view in which a second polysilicon layer 22 is formed on the entire upper surface. FIG. 2G shows a sectional view in which the second polysilicon layer 22 is patterned to form a control gate 22A through a photolithography and etching process using a mask for the control gate electrode. The flash memory cell formed according to the above process has good dielectric characteristics between the floating gate 3A and the control gate 22A and the thickness of the insulating film can easily be controlled since the insulating spacer 11A of ONO or ON structure is formed at the side walls of the floating gate 3A, thereby preventing reduction of coupling ratio as the side walls of the floating gate 3A are oxidized. A method of making a flash memory cell according to the second embodiment has aspects that are similar to the first embodiment described above. An important feature of the second embodiment is that the first polysilicon layer 3 is patterned to form the floating gate 3A without a step for forming the oxide film 4 on the first polysilicon layer 3 shown in FIG. 2A.

As mentioned above, the present invention has an outstanding effect which can prevent reduction of coupling ratio by forming the insulating spacer 11A of ONO or ON structure at the side walls of the floating gate 3A.

The foregoing description, although described in its preferred embodiment with a certain degree of particularity, is only illustrative of the principle of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope and spirit of the present invention are to be encompassed as further embodiments of the present invention.