US 5,701,029 AGrant
Semiconductor Having Polycrystalline Silicon Sandwiched by Semiconductor Substrate and Metal Silicide
Issue Date:1997-12-23
•10 Claims
•11 Drawing Sheets
Abstract
In a semiconductor device including a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer, a transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.
Metadata
Assignee
- NEC Corporation
Inventor
- Masakazu Sasaki
Application Information
Application Number:US 5354005
Filing Date:1995-09-28
Priority Date:1994-09-28
Art Unit:258
Classifications
IPC:
H01L 2943H01L 2945
Field of Search:
257377;381;382;384;385;588;754;755;756;773;775;378
Patent Drawings (11 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to a silicide semiconductor device having a polycrystalline silicon layer sandwiched by a semiconductor substrate and a metal silicide layer.
2. Description of the Related Art
Generally, in a semiconductor device, a metal layer made of aluminum, for example, is deposited as an electrode on a semiconductor substrate made of silicon. In this case, when a heat process is carried out, the metal layer reacts on the semiconductor substrate to form a metal silicide layer. If a shallow PN junction is formed in the semiconductor substrate in advance, metal is immersed through the PN junction, so that the PN junction is broken down which invites electrical leakage.
In a prior art semiconductor device, in order to avoid the above-described electrical leakage caused by the breakdown of the PN junction, a polycrystalline silicon layer serving as an impurity diffusion source is interposed between the metal layer and the semiconductor substrate. That is, an insulating layer is formed on the semiconductor substrate, and an opening is perforated in the insulating layer. Then, a polycrystalline silicon layer is deposited on the semiconductor substrate through the opening of the insulating layer. In this case, impurity ions are doped into the polycrystalline silicon layer, and thereafter, a heat operation is performed upon the polycrystalline silicon layer, so that an inpurity doped region is formed in the semiconductor substrate. Thus, a shallow PN junction is formed within the semiconductor substrate.
Even in the above-described prior art semiconductor device, however, if the thickness of the insulating layer is too large, it is impossible to avoid breakdown of PN junctions due to the immersion of metal into the semiconductor substrate. This will be explained later in detail.
Summary of the Invention
It is an object of the present invention to avoid breakdown of PN junctions due to the immersion of metal into a semiconductor substrate.
According to the present invention, in a semiconductor device including a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer, a transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.
Also, in the present invention, the polycrystalline silicon layer has a larger crystal grain size at a sidewall of the insulating layer than at a bottom of the opening and at a surface of the insulating layer.
Thus, the immersion of metal into the semiconductor substrate is stopped by the thicker portion of the polycrystalline silicon or by the larger crystal grain size portion of the polycrystalline silicon layer, to avoid the breakdown of the PN junction within the semiconductor substrate.
Brief Description of the Drawings
The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:
FIGS. 1A through 1D are cross-sectional views illustrating a prior art method for manufacturing a semiconductor device;
FIGS. 2A and 2B are cross-sectional views for explaining the breakdown of a PN junction in the device of FIGS. 1A through 1D;
FIGS. 3A through 3E are cross-sectional views illustrating a first embodiment of the method for manufacturing a semiconductor device according to the present invention;
FIGS. 4A and 4B are cross-sectional views for explaining the breakdown of a PN junction in the device of FIGS. 3A through 3E;
FIGS. 5A through 5F are cross-sectional views illustrating a second embodiment of the method for manufacturing a semiconductor device according to the present invention;and
FIGS. 6A and 6B are cross-sectional views for explaining the breakdown of a PN junction in the device of FIGS. 5A through 5F.
Description of the Preferred Embodiments
Before the description of the preferred embodiments, a prior art method for manufacturing a semiconductor device having a polycrystalline silicon layer sandwiched by a semiconductor substrate and a metal silicide layer will be explained with reference to FIGS. 1A through 1D. Note that FIGS. 1A through 1D show a method for manufacturing an NPN type transistor.
First, referring to FIG. 1A, a base P-type impurity diffusion region 2 is selectively formed in an N-type silicon substrate 1. Also, an insulating layer 3 made of silicon oxide is formed on the silicon substrate 1, and an opening is perforated in the insulating layer 3. Then, a polycrystalline silicon layer 4 is deposited by a chemical vapor deposition (CVD) process, and N-type impurity ions such as arsenic ions are doped thereinto. Thus, a high concentration N-type polycrystalline silicon layer, which serves as a diffusion source for an emitter impurity diffusion region, is obtained.
Next, referring to FIG. 1B, a heating operation or an annealling operation is carried out in a nitrogen atmosphere to diffuse the arsenic from the polycrystalline silicon layer 4 into the silicon substrate 1. As a result, an emitter N-type impurity diffusion region 5 is formed in the base P-type impurity diffusion region 2. Thus, a shallow PN junction is created in the silicon substrate 1.
Next, referring to FIG. 1C, the polycrystalline silicon layer 4 is patterned by a photolithography process to obtain an emitter electrode 4a.
Finally, referring to FIG. 1D, a platinum layer is formed by a sputtering process, and a heating operation is carried out under a nitrogen atmosphere. As a result, the platinum layer reacts on the upper portion of the polycrystalline silicon layer 4 to thereby form a platinum silicide layer 6. Also, a high melting point metal layer 7 made of tungsten, titanium or molybdenum is deposited by a sputtering process thereon. Further, an insulating layer 8 is formed, and an opening is perforated therein. Then, an electrode layer 9 made of aluminum is deposited and patterned, thus completing a semiconductor device.
In the semiconductor device as illustrated in FIGS. 1A through 1D, if the insulating layer 3 is thick, for example, 500 to 700 nm thick, the shallow PN junction may be broken down.
That is, as illustrated in FIG. 2A, which is a partial enlargement of FIG. 1B, although the polycrystalline silicon layer 4 is homogeneously grown, polycrystalline silicon grown along a transverse direction collides with polycrystalline silicon grown along a longitudinal direction, so that the crystal grain size of polycrystalline silicon around the sidewall of the insulating layer 3 as indicated by X becomes smaller than the other portions thereof.
As a result, as illustrated in FIG. 2B, which is a partial enlargement of FIG. 1D, the metal, i.e., platinum of the silicide layer 6 is immersed through the smaller crystal grain size portion X into the PN junction of the silicon substrate 1. As a result, the PN junction is broken down.
Incidentally, the depth of immersed metal in the polycrystalline silicon layer 4 is about 300 to 400 nm. Therefore, if the polycrystalline silicon layer 4 is about 500 nm or more thick, the metal hardly reaches the silicon substrate 1. However, the thick polycrystalline silicon layer creates a step in the laminated configuration including the insulating layer 8 and the electrode layer 9, thus inviting disconnections of the electrode layer 9. This reduces the manufacturing yield of semiconductor devices. Thus, it is disadvantageous to thicken the polycrystalline silicon layer 4.
FIGS. 3A through 3E are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor device according to the present invention.
First, referring to FIG. 3A, in the same way as in FIG. 1A, a base P-type impurity diffusion region 2 is selectively formed in an N-type silicon substrate 1. Also, an insulating layer 3 made of silicon oxide is formed on the silicon substrate 1, and an opening is perforated in the insulating layer 3. Then, an about 500 nm thick polycrystalline silicon layer 4 is deposited by a CVD process, and N-type impurity ions such as arsenic ions are doped thereinto. Thus, a high concentration N-type polycrystalline silicon layer, which serves as a diffusion source for an emitter impurity diffusion region, is obtained.
Next, referring to FIG. 3B, in the same way as in FIG. 1B, a heating operation or an annealling operation is carried out in a nitrogen atmosphere to diffuse the arsenic from the polycrystalline silicon layer 4 into the silicon substrate 1. As a result, an emitter N-type impurity diffusion region 5 is formed in the base P-type impurity diffusion region 2. Thus, a shallow PN junction is created in the silicon substrate 1.
Next, referring to FIG. 3C, the polycrystalline silicon layer 4 is etched back by an anisotropic etching process. As a result, the thickness of the polycrystalline silicon 4 around the sidewall of the insulating layer 3 is still about 500 nm, while the thickness of the polycrystalline silicon layer 4 on the surface of the insulating layer 3 and the bottom of the opening thereof is about 200 nm.
Next, referring to FIG. 3D, in the same way as in FIG. 1C, the polycrystalline silicon layer 4 is patterned by a photolithography process to obtain an emitter electrode 4a.
Finally, referring to FIG. 3E, in the same way as in FIG. 1D, a platinum layer is formed by a sputtering process, and a heating operation is carried out at a temperature of about 400.degree. C. under a nitrogen atmosphere. As a result, the platinum layer reacts on the upper portion of the polycrystalline silicon layer 4 to thereby form a platinum silicide layer 6. Also, a high melting point metal layer 7 made of tungsten, titanium or molybdenum is deposited by a sputtering process thereon. Further, an insulating layer 8 is formed, and an opening is perforated therein. Then, an electrode layer 9 made of aluminum is deposited and patterned, thus completing a semiconductor device.
In the semiconductor device as illustrated in FIGS. 3A through 3E, if the insulating layer 3 is thick, for example, 500 to 700 nm thick, the shallow PN junction may not be broken down.
That is, as illustrated in FIG. 4A, which is a partial enlargement of FIG. 3D, although the crystal grain size of polycrystalline silicon around the sidewall of the insulating layer 3 as indicated by Y becomes smaller than the other portions thereof, the thickness of the portion of the polycrystalline silicon layer 4a as indicated by Y is still thick, for example, about 500 nm.
As a result, as illustrated in FIG. 4B, which is a partial enlargement of FIG. 3E, even when the metal, i.e., platinum of the silicide layer 6 is immersed through the smaller crystal grain size portion Y, the metal cannot reach the PN junction of the silicon substrate 1. As a result, the PN junction is not broken down.
FIGS. 5A through 5F are cross-sectional views for explaining a second embodiment of the method for manufacturing a semiconductor device according to the present invention.
First, referring to FIG. 5A, in a similar way to that shown in FIG. 1A, a base P-type impurity diffusion region 2 is selectively formed in an N-type silicon substrate 1. Also, an insulating layer 3 made of silicon oxide is formed on the silicon substrate 1, and an opening is perforated in the insulating layer 3. Then, an about 100 to 200 nm thick polycrystalline silicon layer 4' is deposited by a CVD process, and N-type impurity ions such as arsenic ions are doped thereinto.
Next, referring to FIG. 5B, the polycrystalline silicon layer 4' is etched back by an anisotropic etching process, to leave a sidewall polycrystalline silicon layer 4'a on the sidewall of the insulating layer 3. Then, a heating operation is performed upon the sidewall polycrystalline silicon layer 4'a at a temperature of about 900.degree. to 1000.degree. C. under a nitrogen atmosphere, to increase the crystal grain size of the sidewall polycrystalline silicon layer 4'a.
Next, referring to FIG. 5C, another polycrystalline silicon layer 4" is deposited by a CVD process, and N-type impurity ions such as arsenic ions are doped thereinto. In this case, note that the portion of the polycrystalline silicon layer 4" on the sidewall polycrystalline silicon layer 4'a also has a large crystal grain size, since this portion has the same crystal structure as the sidewall polycrystalline silicon layer 4'a.
Thus, a high concentration N-type polycrystalline silicon layer, which serves as a diffusion source for an emitter impurity diffusion region, is obtained.
Next, referring to FIG. 5D, in a similar way to that as shown in FIG. 1B, a heating operation or an annealling operation is carried out in a nitrogen atmosphere to diffuse the arsenic from the polycrystalline silicon layers 4'a and 4" into the silicon substrate 1. As a result, an emitter N-type impurity diffusion region 5 is formed in the base P-type impurity diffusion region 2. Thus, a shallow PN junction is created in the silicon substrate 1.
Next, referring to FIG. 5E, in a similar way to that as shown in FIG. 1C, the polycrystalline silicon layer 4" is patterned by a photolithography process to obtain an emitter electrode 4"a.
Finally, referring to FIG. 5F, in the same way as in FIG. 1D, a platinum layer is formed by a sputtering process, and a heating operation is carried out at a temperature of about 400.degree. C. under a nitrogen atmosphere. As a result, the platinum layer reacts on the upper portion of the polycrystalline silicon layer 4 to thereby form a platinum silicide layer 6. Also, a high melting point metal layer 7 made of tungsten, titanium or molybdenum is deposited by a sputtering process thereon. Further, an insulating layer 8 is formed, and an opening is perforated therein. Then, an electrode layer 9 made of aluminum is deposited and patterned, thus completing a semiconductor device.
Also, in the semiconductor device as illustrated in FIGS. 5A through 5F, if the insulating layer 3 is thick, for example, 500 to 700 nm thick, the shallow PN junction may not be broken down.
That is, as illustrated in FIG. 6A, which is a partial enlargement of FIG. 5E, even if the thickness of the polycrystalline silicon layers 4'a and 4"a around the sidewall of the insulating layer 3 as indicated by Z is less than 500 nm, the crystal grain size of polycrystalline silicon around the sidewall of the insulating layer 3 as indicated by Z is large.
As a result, as illustrated in FIG. 6B, which is a partial enlargement of FIG. 5F, the immersion of metal, i.e., platinum into the PN junction of the silicon substrate 1 is interrupted by the larger crystal grain size polycrystalline silicon as indicated by Z. As a result, the PN junction is not broken down.
Note that a titanium silicide layer or the like can be used as the metal silicide layer instead of a platinum silicide layer. Also, the present invention can be applied to devices other than bipolar transistors.
As explained hereinbefore, according to the present invention, since the immersion of metal of silicide into a semiconductor substrate is interrupted by a thick polycrystalline silicon layer or a large crystal grain size polycrystalline silicon layer, the breakdown of PN junctions in the semiconductor substrate can be avoided.
Claims
I claim:
1. A semiconductor device comprising: a semiconductor substrate; an impurity doped region formed in said semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening leading to said impurity doped region; a polycrystalline silicon layer formed on said insulating layer and said impurity doped region, a first level portion of said polycrystalline silicon layer at a bottom of said opening and a second level portion of said polycrystalline silicon layer at a surface of said insulating layer each having a thickness which is smaller than a transverse thickness of a third portion of said polycrystalline silicon layer at a sidewall of said insulating layer between said first level and second level portions; and a metal silicide layer formed on said polycrystalline silicon layer, wherein a crystal grain size of said polycrystalline silicon layer around the sidewall of said insulating layer is larger than a crystal grain size of said polycrystalline silicon layer around said impurity doped region and the surface of said insulating layer.
2. A device as set forth in claim 1, wherein said impurity doped region is formed in self-alignment with the opening of said insulating layer.
3. A device as set forth in claim 1, further comprising a metal layer formed on said polycrystalline silicon layer.
4. A device as set forth in claim 3, further comprising a high melting point metal layer between said metal silicide layer and said metal layer.
5. A device as set forth in claim 1, wherein said polycrystalline silicon layer comprises: a first polycrystalline silicon layer formed on the sidewall of said insulating layer; and a second polycrystalline silicon layer formed on the surface of said insulating layer, said first polycrystalline silicon layer and said impurity doped region.
6. A semiconductor device comprising: a semiconductor substrate; an impurity doped region formed in said semiconductor substrate; an insulating layer formed on said semiconductor substrate, said insulating layer having an opening leading to said impurity doped region; a polycrystalline silicon layer formed on said insulating layer and said impurity doped region, said polycrystalline silicon layer having a larger crystal grain size at a sidewall of said insulating layer than at a bottom of said opening and at a surface of said insulating layer; and a metal silicide layer formed on said polycrystalline silicon layer.
7. A device as set forth in claim 6, wherein said impurity doped region is formed in self-alignment with the opening of said insulating layer.
8. A device as set forth in claim 6, further comprising a metal layer formed on said polycrystalline silicon layer.
9. A device as set forth in claim 8, further comprising a high melting point metal layer between said metal silicide layer and said metal layer.
10. A device as set forth in claim 6, wherein said polycrystalline silicon layer comprises: a first polycrystalline silicon layer formed on the sidewall of said insulating layer; and a second polycrystalline silicon layer formed on the surface of said insulating layer, said first polycrystalline silicon layer and said impurity doped region.
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