Band Gap Current Reference Circuit

1. Technical Field of the Invention

This invention pertains to integrated circuits. In particular, this invention is directed to an improved current reference circuit for use in IC chips, thereby providing a more accurate current reference regardless of input frequency.

2. Background Art

Prior art CMOS current references have required external voltage sources and external resistors to provide an accurate current. The best tolerance achieved in all prior integrated current references leaves room for improvement. The present invention provides a reference of better accuracy than any other prior art current reference circuit and can be completely contained on a standard CMOS chip.

It is an object of the invention to provide a more accurate on-chip current reference circuit.

It is another object of the invention to provide a reference current with reduced sensitivity to temperature and process variations.

It is yet another object of the present invention to provide a reference current circuit including multiple selectable switch capacitor circuits for generating a constant current at different frequencies.

An on-chip current reference circuit using a frequency source to control a rate of charge transfer via a switched capacitor. This invention also comprises a technique to transfer charge via a switched capacitor between two nodes that differ in voltage by the band gap of silicon (V.sub.bg, approximately 1 V or more depending on the technology) at a rate controlled by an accurate frequency source. The output current is then proportional to V.sub.bg .times.C.sub.SW .times.F.sub.refin (wherein C.sub.SW is the switching capacitor capacitance and F.sub.refin is the frequency of the input). This technique makes good use of the two most accurate components available in state of the art CMOS processes.

Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.

FIG. 1a-b illustrates the current reference circuit of the present invention.

FIG. 1c illustrates the complementary refin frequencies (not to scale).

FIG. 2 illustrates the programmable pulse generator for selecting switching capacitors to maintain the reference current over various operating frequencies.

FIG. 3 illustrates an alternative embodiment of the current reference circuit.

With reference to FIG. 1, T0 through T3b are inputs from the pulse generator (FIG. 2 ). For simplicity the following discussion will focus on inputs T0 and T0b, however, it is noted that the other input pairs, connected in parallel with T0, operate in a manner equivalent to the following discussion. Special transistor 23 is an NFET with a P-doped gate, which displays normal NFET characteristics except that its threshold voltage is increased above the normal value by an amount equal to the band gap of silicon (V.sub.bg). It is driven by a PFET current mirror comprising transistors 19 and 20 (sometimes referred to as "legs"of the current mirror) which, in turn, is driven by an NFET current mirror comprising transistor 14 and transistor 17. Transistor 14 is a diode connected NFET with an equivalent RC integrator formed by transistor 15 and capacitor 16. The integrator, using the high channel resistance of transistor 15 and a large capacitor 16 for a long time constant, significantly reduces the drain ripple (discussed below) in transistor 14 via its gate. Capacitor 13 is the main filter capacitor, capacitor 11 is the switching capacitor and transistors 10 & 12 are the switches. Transistor 21 is a PFET diode with a very long, very narrow channel that is used when power is applied to the circuit. As the circuit is powered on, the rising voltage at node bg reduces the starting current I.sub.1 to zero for all cases except when the power supply is operated at voltages of approximately 2.7 volts or greater. Transistors 18 and 24 are cascode transistors to keep the drain voltages steady on transistors 17 and 25, respectively. The circuit is operable for processes with about 2.5 volt power supply but may be operated at greater than about 3.3 volts in some applications.

Assuming the circuit has been powered on and input T0 is switching at an appropriate rate, capacitor 11 is alternately charged to V.sub.bg +V.sub.t +V.sub.od (silicon band gap, threshold, and overdrive voltages ) of transistor 23 and discharged to V.sub.t +V.sub.od of transistor 14. If the switching rate is high with respect to the time constant formed by capacitor 13 and transistor 14, and the capacitance of capacitor 13 (Cf) is large with respect to capacitor 11, the switches 10 and 12 together with capacitor 11 can be thought of as a resistance, or impedance, (R.sub.eq) equivalent to 1/(C.sub.SW .times.F.sub.refin) that is connected between nodes bg and capacitor 13.

Notice that the two current mirrors (transistors 19 & 20, transistors 14 & 17) and R.sub.eq form a positive feedback loop which has high gain until the currents (I.sub.2, I.sub.3) turn on and then the gain is drastically reduced owing to diode connected transistor 23 and the ratio of R.sub.eq to the channel resistance of transistor 14. The gain of the NFET mirror is approximately unity and the gain of the PFET mirror about 4. This ensures that capacitor 11 will be quickly charged to the voltage at node bg when transistor 10 is switched on. Capacitor 13 ensures that the voltage change across transistor 14 will be small as transistor 12 discharges capacitor 11 into capacitor 13. The average current passing through R.sub.eq is then the same as the average current in transistor 14.

The sizes of transistor 23 and transistor 14 are chosen so that their respective overdrive voltages are about the same. Since their threshold voltages are also about the same except for the effect of complimentary gate doping on transistor 23, the voltage difference appearing across R.sub.eq is very nearly equal to V.sub.bg.

Considering T0b, which is the compliment of T0 except there is a short time between pulses when both are down (see FIG. 1C, not to scale), it is connected to a second set of switches and capacitor. When capacitor 11 is being discharged into capacitor 13 and transistor 14 (through transistor 12) capacitor 26 is being charged to the voltage at node bg. Similarly, when capacitor 11 is being charged to the voltage at node bg, capacitor 26 is being discharged into capacitor 13. This results in a doubling of the average current in transistor 14, a doubling of the ripple frequency, and a halving of the ripple voltage across capacitor 13.

For processors operable at various application frequencies, it is desirable to keep the reference current constant for all operating frequencies. This means that the product of the total capacitance and operating frequency must be kept constant. For those cases where it is desired to deactivate switching capacitors, its switching input (i.e. any of inputs T0 through T3b) is held at a DC level. The level may be either up or down but in the present case it is held up which places the switching capacitor in parallel with capacitor 13, which has no influence on the average current into transistor 14.

Useful outputs VP1 and VP2 are generated by further mirroring the reference current in transistor 14 (I.sub.4) into transistors 25 and 27. Transistor 25 drives transistor 28 through a cascode transistor 24 to provide reference voltage VP2 for cascode transistor 29 and other loads. Transistor 27 drives the reference transistor 30. Output currents I0 are then provided in transistor 31 and its cascode transistor 32 and as many similar pairs connected in parallel as may be desired. The VP1 output voltage determines the amount of current obtained from I0. Transistor 33 is connected as a MOS capacitor which further decouples switching noise and noise appearing on V.sub.dd.

Referring to FIG. 2, the pulse generator is shown with programmable inputs Tp2 and mf3 for selecting which output pairs are to be switched at the input reference (F.sub.refin) as follows:

The circuitry at the top of FIG. 2 generates lines ta and tb, which are the true and complement of refin with some space between them (see FIG. 1C, not to scale) so that output pairs are non-overlapping. This ensures that the charge on any active switching capacitor is cleanly transferred to capacitor 13 and not to another active switching capacitor. The output current is proportional to V.sub.bg .times.C.sub.SW .times.F.sub.refin, thus, the complementary switching capacitors may be selected depending on the applied operating frequency, which is not limited by the example table shown above. Any number of switching capacitor circuits may be coupled in parallel to handle any number of operating frequencies.

Alternative Embodiment

Referring to FIG. 3, whose similarities to the circuit of FIG. 1 are readily apparent, an alternative embodiment is illustrated comprising a technique to connect a precision resistor between two nodes (bg and Vn) that differ in voltage by V.sub.bg. The output current I0 is then proportional to V.sub.bg /R, wherein R is the resistance of resistor 70. Transistor 53 is an NFET with a P-doped gate, which displays normal NFET characteristics except that its threshold voltage is increased above the normal value by an amount equal to the band gap of silicon (V.sub.bg). It is driven by a PFET current mirror comprising transistors 49 and 50 which, in turn, is driven by an NFET current mirror comprising transistor 44 and transistor 47. Transistor 44 is a diode connected NFET. Transistor 51 is a PFET diode with a very long, very narrow channel that is used when power is applied to the circuit. As the circuit is powered on, the rising voltage at node bg reduces the starting current I.sub.5 to zero for all cases except when the power supply is operated at voltages of approximately 2.7 volts or greater. Transistors 48 and 54 are cascode transistors to keep the drain voltages steady on transistors 47 and 55, respectively. The circuit is operable for processes with about 2.5 volt power supply but may be operated at greater than about 3.3 volts in some applications.

Assuming the circuit has been powered on, resistor 70 is connected between nodes bg and Vn whose voltages are V.sub.bg +V.sub.t +V.sub.od of transistor 53 and V.sub.t +V.sub.od of transistor 44, respectively, thereby creating the current I.sub.6, V.sub.bg /R.

Notice that the two current mirrors (transistors 49 & 50, transistors 44 & 47) and resistor 70 form a positive feedback loop which has high gain until the currents turn on (I.sub.6, I.sub.7) and then the gain is drastically reduced owing to diode connected transistor 53 and the ratio of resistor 70 to the channel resistance of transistor 44. The gain of the NFET mirror is approximately unity and the gain of the PFET mirror about 4. This ensures that transistor 53 will have small current variations. The current in resistor 70 (I.sub.6) flows through transistor 44.

The sizes of transistor 53 and transistor 44 are chosen so that their respective overdrive voltages are about the same. Since their threshold voltages are also about the same except for the effect of complimentary gate doping on transistor 53, the voltage difference appearing across resistor 70 is very nearly equal to V.sub.bg.

Useful outputs VP1 and VP2 are generated by further mirroring the reference current in transistor 44 (I.sub.6) into transistors 55 and 57. Transistor 55 drives transistor 58 through a cascode transistor 54 to provide reference voltage VP2 for cascode transistor 59 and other loads. Transistor 57 drives the reference transistor 60. Output currents are then provided in transistor 61 and its cascode transistor 62 and as many similar pairs connected in parallel as may be desired. The VP1 output voltage determines the amount of current obtained from I0. Transistor 63 is connected as a MOS capacitor which decouples noise appearing on V.sub.dd.

The circuit embodiments described above advantageously exploit the increased threshold voltage of a complementary doped FET. It is well known in the art to selectively dope FETs via ion implantation, for example, to vary the threshold voltage. Such channel tailoring can be used to produce FETs with a lower than normal threshold voltage by, for example, an increased ion implantation of a selected impurity. Thus, the inventive circuits shown in FIGS. 1 and 3 can also be implemented by using a conventional FET for transistors 23 and 53, respectively, and replacing transistors 14 and 44 with FETs having below normal thresholds. Thereby, the difference in threshold voltage appears across R.sub.eq (FIG. 1) or resistor 70 (FIG. 3 ) to provide the reference current. Transistors 17, 25, and 27 (FIG. 1) and transistors 47, 55, and 57 (FIG. 3) would also be replaced with FETs having below normal thresholds for proper circuit performance.

The advantages of the method of the preferred embodiment of this invention include a more accurate current reference with reduced dependency on temperature and process variation. A number of complementary capacitor switching circuits is provided to be selected based on the operating frequency.

Since changes may be made in the above structure and process without departing from the scope of the invention described herein, it is intended that all the matter contained in the above description or shown in the accompanying drawings shall be interpreted in an illustrative and not in a limiting sense. For example, the polarity of the components may be replaced by equivalent components of opposite polarity, i.e. PFETs for NFETS. Thus, other alternatives and modifications will now become apparent to those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims. Accordingly, the scope of protection of this invention is limited only by the following claims and their equivalents.