Telecommunications Circuit Provisioning and Administration System

The present invention relates to telecommunications systems, and more particularly, to telecommunications circuit provisioning systems.

In the telecommunications industry, telecommunications service companies provide several types of telecommunications circuits as part of their telecommunications service. These types of circuits fall into three primary categories, and are generally not part of plain old telephone service (POTS) or local telecommunications service. The three types of circuits include special service circuits (both access and private line), trunk circuits, and facility circuits. Special service circuits, include two separate types of circuits: telephone circuits and serial circuits. As the term itself denotes, special service circuits are used to provide telecommunications service to customers having certain specialized needs. Special service orders (SSO) are received and implemented by telecommunications companies for various situations such as, for example, political or industry conventions or state-wide lotteries. In these situations, upon receiving an SSO, a telecommunications service provider designs and implements special telephone or serial circuits at the location and for the time period requested by the user. For example, if a political convention required 50 telephone lines and 20 serial lines from the arena or meeting facility hosting the convention for a period of two weeks, this service would be ordered as SSOs and designed and implemented by the telecommunications service provider.

Trunk circuits are the interface for transmission, supervision, and signaling between switching systems. Trunk circuit orders (TCO) are typically placed by telecommunications service providers who are in need of additional message circuits. A facility circuit order (FCO) involves many telecommunications circuits. As with TCOs, FCOs are typically placed by telecommunications service providers. For example, a facility planning group of a service provider responsible for monitoring user traffic will order additional facility circuits in those locations experiencing heavy user traffic.

Most telecommunications service providers use some type of facility or system for receiving and managing the various types of circuit orders discussed above. These circuit order management systems receive both "access" and "non-access" orders. Both types of orders are commonly referred to as access service requests. Access orders are those orders received from the various long distance carriers. Non-access orders are received from local operating companies and users other than long distance carriers. Typically, circuit order management systems are staffed with personnel whose function is to enter or monitor the circuit orders received from the access or non-access users. These personnel are sometimes referred to in the industry as Interexchange Customer Service Centers (ICSC). Obviously, the objective for a telecommunications company providing this type of service is to receive information sufficient to design and implement circuit orders. The design of a circuit order is embodied in what is known in the industry as a circuit layout record (CLR). A CLR contains the design parameters of circuit orders and is used by field offices to physically implement circuit orders.

There are various types of legacy systems used in the telecommunications industry for receiving and implementing circuit orders. These systems include as one component an Access Request Management System (ARMS) which receives access and non-access circuit orders as described above and inputs the orders into an intelligible format for design and implementation by other system components or personnel. Essentially, the ARMS is an order entry system. Another component is an order tracking system which is used to track important information relating to the circuit orders such as order dates, due dates, milestone dates, service dates, etc. Certain legacy systems also include a provisioning component which is a partially mechanized system that assists in the creation of CLRs. If no provisioning component is available, the CLRs are manually created by an engineer.

A significant disadvantage of the above-described systems is that circuit orders must be manually entered into each component of the system. In other words, the same circuit order must be manually entered up to three times; once each into the ARMS, the order tracking system and the provisioning component if available. As the volume of circuit orders received by these systems increases, it is evident that a significant amount of time and resources are consumed by this procedure. Also, the legacy systems have no means for automatically communicating confirmation messages to the ARMS regarding the status of circuit orders. At best, the ARMS will receive a telephone call informing ARMS whether orders were accepted or rejected. A further disadvantage of these systems is that a design layout record (DLR) must be manually entered into the ARMS. A DLR contains information similar to that contained in the CLR, i.e., design parameters of the circuit order. DLRs are communicated by ARMS back to the interexchange carrier (IC) placing the order to inform the IC of the circuit design parameters. This provides the IC the ability to interface the circuit design with their own telecommunications system.

Another known telecommunications circuit order management and provisioning system is the TIRES (Trunks Integrated Record Keeping System) developed by Bellcore. TIRKS is a computer-based system which provides circuit order control, circuit design support, inventory record maintenance, selection and assignment of components from inventory, and preparation and distribution of circuit work orders. TIRES runs on a mainframe computer system. Generally, TIRKS receives circuit orders in an order control module which controls message/trunk, special service, and carrier system orders by tracking critical dates as the order is processed through completion. The order control module communicates with a circuit provisioning system which operates in conjunction with other TIRKS components to assign facility and equipment information for circuit orders and design circuits. Under certain conditions, TIRKS provides automated design criteria for particular circuit orders. The circuit design generated by TIRKS is communicated to a plant or field for implementation, and the plant also informs the order control module of the circuit implementation for tracking purposes.

Although TIRKS is a significant development in telecommunications circuit provisioning systems, TIRKS experiences certain important limitations common to other provisioning systems known in the art. Significantly, TIRKS and other provisioning systems operate entirely on mainframe computer systems. Such computer systems are considerably more expensive than mid-range distributed computer systems. Moreover, mainframe computer systems do not possess a high degree of flexibility in relation to modifications and upgrades as computer technology advances.

In view of the foregoing, it is a general aim of the present invention to provide a telecommunications circuit provisioning and administration system which efficiently receives, processes, and designs telecommunications circuit orders.

In accomplishing that aim, it is a primary object of the present invention to provide a telecommunications circuit provisioning and administration system that communicates detailed status information to an order entry system relating to the status of circuit orders.

It is a further object of the present invention to provide a telecommunications circuit provisioning and administration system that utilizes a distributed mid-range computer system capable of efficiently and cost-effectively communicating with mainframe computer systems.

It is another object of the present invention to provide a telecommunications circuit provisioning and administration system that is capable of producing automated circuit layout design records for a substantial quantity of circuit orders received.

It is yet another object of the present invention to provide a telecommunications circuit provisioning and administration system that automatically produces design layout records and communicates the design layout records to the order entry system.

These and other objectives are accomplished by the telecommunications circuit provisioning and administration system according to the present invention. The system of the present invention includes an access request management component which receives access service requests for a plurality of different types of telecommunications circuits, processes the access service requests, and produces provisioning data packets containing information relating to the requested telecommunications circuits. Each provisioning data packet includes at least one order relating to a telecommunications circuit. An interface is connected to the access request management component for transmitting information to and from the access request management component. The interface is capable of providing communication between mainframe computer systems and mid-range distributed systems. The system of the present invention also includes a circuit administration component connected to the interface which receives the provisioning data packets from the access request management component. A processor in the circuit administration component processes the information contained in the provisioning data packets and generates order confirmation messages containing information relating to the status of the requested telecommunications service orders. These confirmation messages are communicated to the access request management component through the interface. The circuit administration component is also capable of producing automated circuit layout records for the telecommunications circuit orders contained in the provisioning data packets.

FIG. 1 is a block diagram generally illustrating the telecommunications circuit provisioning and administration system of the present invention;

FIG. 2 is a block diagram illustrating the order processing interface record flow for the system shown in FIG. 1;

FIG. 3 is a block diagram illustrating the circuit order interface flow for the system shown in FIG. 1;

FIG. 4 is a more detailed flow diagram illustrating the background order process flow for the interface flow shown in FIG. 3; and

FIG. 5 is a flow diagram illustrating the software-assisted engineering process flow for special service orders.

While the invention will be described in connection with a preferred embodiment, there is no intent to limit the invention to this embodiment. On the contrary, the intent is to cover all alternatives, modifications, and equivalents included within the spirit and scope of the invention as defined in the appended claims.

Turning now to the drawings, FIG. 1 is a block diagram of a telecommunications circuit provisioning and administration system 10 according to the present invention. In the preferred embodiment, the telecommunications circuit provisioning and administration system 10 provides telecommunications service for trunk circuits, facility circuits, and special service circuits which include both telephone circuits and serial circuits. According to the invention, system 10 includes as one component an access request management system (ARMS) denoted as block 12. The ARMS 12 receives telecommunications circuit orders (i.e., access service requests) from both access and non-access telecommunications users. The access service requests contain both provisioning data and billing information. ARMS 12 transmits the provisioning data to another component of system 10 referred to as a circuit administration system (CIRAS) 14. In accordance with the present invention, CIRAS 14 processes the provisioning data received from ARMS 12 and generates circuit order design information which is ultimately transmitted to a remote location for implementation of the circuit orders.

Referring in more detail to ARMS 12 as shown in FIG. 1, ARMS 12 operates on an IBM 3090 computer system utilizing the MVS operating system in the CICS region. As noted above, ARMS 12 receives access service requests for a plurality of different types of telecommunications circuits (TCOs, FCOs, and SSOs). ARMS 12 then processes the access service requests and generates several items of information required for implementation of the circuit orders. For example, ARMS 12 generates provisioning data packets which contain information relating to the telecommunications circuits ordered in the access service requests. These provisioning data packets are identified with a purchase order number (PON), and can include either a single record transmission relating to a single telecommunications circuit order, or a series of records relating to multiple circuit orders. As discussed in further detail below, each provisioning data packet consists of at least one header record, one data record, and one trailer record. All data transmissions are formatted in character format. Each record in a provisioning data packet contains a standard control data area (STD-CTL), a standard key (STD-KEY), and a general data area. The standard control data (STD-CTL) area is reserved for system data provided for audit and debugging purposes. The format of the standard control (STD-CTL) data area is shown in the following table:

The standard key (STD-KEY) data is reserved for fields which uniquely identify the provisioning data packets as data for a particular purchase order. The format of the standard key (STD-KEY) data is as follows:

The general data area of each record is reserved for data which changes with each interface process. The first character of the data area is always the record type. There are several different record types, including provisioning header, provisioning administrative, provisioning milestone, provisioning circuit, etc. The record type uniquely identifies the type of data to be provided with the record, as set forth in Table 3 below:

Thus, as shown in FIG. 1, provisioning data packets are transmitted to CIRAS 14 via an interface 16; specifically line 18 of interface 16. In a specific implementation of the preferred embodiment, interface 16 comprises a CICS application programming interface (API) utilized in conjunction with a TCP/IP network. Importantly, the interface of the present invention provides the capability of transmitting data in real-time between a mainframe computer system and a mid-range computer system.

In that connection, an important aspect of the present invention is that CIRAS 14 runs on a mid-range RISC 6000 computer operating on the AIX operating system. In the preferred embodiment, CIRAS 14 utilizes the Oracle software language. Oracle is a relational database management language and is advantageous for several reasons. For example, Oracle allows CIRAS 14 to run on over 80 different computer hardware platforms. In keeping with the present invention, by running in the distributed environment of the IBM RISC 6000, CIRAS 14 allows applications servers to be placed in the user areas and database operations support to reside in the data area. The distributed environment of CIRAS 14 provides additional advantages over mainframe systems. For example, mainframe systems are considerably more costly than distributed systems, both in hardware components and CPU processing time. Additionally, distributed systems provide significantly greater flexibility in system modifications and upgrades over mainframe systems as technology advances. CIRAS 14 uses Bellcore common language code sets, including Common Language Location Identifier (CLLI), Common Language Equipment Identifier (CLEI), Common Language Facility Identifier (CLFI), and Common Language Circuit Identifier (CLCI).

As shown in FIG. 1, CIRAS 14 includes two system components: CIRAS order functions denoted at block 20 and CIRAS engineering functions denoted at block 22. The order function component 20 of CIRAS 14 receives provisioning data packets via interface 16 and processes the information contained in the provisioning data packets. In general, this processing determines whether an order relating to a telecommunications circuit requests an entirely new circuit, a change to an existing circuit, or cancellation of an existing circuit. Additionally, in accordance with the present invention, CIRAS order component 20 produces engineering order confirmation (EOC) messages which are transmitted back to the ARMS 12. These EOC messages contain detailed information relating to the status of telecommunications service ordered in access service requests. For example, EOC messages indicate whether telecommunications circuit orders contained in provisioning data packets have been accepted, or whether errors are present in the provisioning data packets resulting in rejection of the circuit orders. EOC messages also provide specifics relating to the nature of errors. Further details of the EOC messages are provided below. As can be seen, EOC messages are transmitted from CIRAS 14 via line 24 of interface 16.

In keeping with the present invention, CIRAS 14 provides two options for designing and implementing the circuit orders received from ARMS 12. One option is to transmit the orders directly to a remote location for design and implementation, at which point a field engineer or other personnel will use the order information to manually design the circuit based on the requirements specified in the circuit orders. This option is designated in FIG. 1 at line 26 wherein the various types of circuit orders 28 are transmitted to a remote location 30 for manual design and implementation. These circuit orders 28 are communicated to the remote location 30 following the transmission of the EOC messages to the ARMS 12.

In accordance with a significant aspect of the present invention, the other option for implementing circuit orders is performed by the engineering function component 22 of CIRAS 14. Under this aspect of the invention, circuit order information from provisioning data packets is communicated to CIRAS engineering function component 22 which processes the information and generates automated circuit layout records 32 utilizing a software-assisted engineering process explained in detail below. The automated circuit layout record 32 is a computer-generated engineering design record which contains design parameters for a telecommunications circuit order. A significant advantage of the automated circuit layout records 32 is that CIRAS engineering function component 22 automatically performs a substantial part of the circuit engineering design and thus reduces or eliminates the manual intervention required in the manual design option explained above. Thus, the telecommunications circuit provisioning and administration system 10 of the present invention provides the capability of receiving access service requests, processing those requests to produce provisioning data packets, transmitting provisioning data packets over an interface capable of providing information exchange between mainframe and distributed computer systems, automatically generating engineering order confirmation messages relating to the status of the circuit orders, and generating automated circuit layout records containing design parameters of the circuit orders which can then be communicated to a remote location for implementation.

As can be seen in FIG. 1, SSOs, TCOs, and FCOs are transmitted from CIRAS component 20 via line 34 to a CIRAS received order files component 36. Also, SSOs are transmitted directly to CIRAS engineering component 22 via line 38 since EOC messages relating to SSOs are automatically generated without manual validation as is the case with FCOs and TCOs. Further details on this point are provided below in connection with FIG. 3. From component 36, local transport (LTR) combinations comprising SSO and FCO combinations, and TCO and FCO combinations are transmitted to CIRAS engineering component 22 via line 40.

In addition to circuit layout records 32, CIRAS 14 also generates automated design layout records 42 which contain design parameters for circuit orders similar to the parameters generated in the circuit layout records. The automated design layout records are transmitted back to ARMS 12 via line 44, which is also a part of interface 16. Importantly, the design layout records allow ARMS 12 to provide circuit design information to telecommunications customers (ICs) so that customers can interface circuit designs with their own telecommunications systems if necessary, and obtain details relating to equipment used for circuits that are not part of their own systems.

CIRAS 14 also includes a processed order files component 46 which stores processed orders relating to SSOs, TCOs, and FCOs. In addition, CIRAS 14 includes a design information input line 48 which allows a remote location to manually intervene in the design of the circuit layout records 32 if required. Also shown in FIG. 1 is a loop makeup (LMU) line 50 interconnecting the remote location 30 and the CIRAS engineering component 22 so that the remote location can provide loop makeup parameters to CIRAS engineering component 22.

FIG. 2 is a block diagram illustrating the order processing interface record flow between CIRAS 14 and ARMS 12 of the telecommunications circuit provisioning and administration system 10 shown in FIG. 1. This figure illustrates the different types of information which are transmitted between ARMS 12 and CIRAS 14. As explained above, the transmission processing is designed so that ARMS 12 initiates the introduction of a circuit order into the interface process. CIRAS 14 responds to that order information. When corrections relating to circuit order information are required, CIRAS 14 sends correction information in the form of EOC messages as a response to circuit orders. When this occurs, ARMS 12 processes the correcting data and, rather than responding to the correction itself, initiates a new cycle of provisioning data transmissions. The ARMS-initiated transactions include the provisioning data packets, milestone transactions consisting of single-record transactions containing jeopardy and/or date-change information, acceptance transactions consisting of single-record responses to CIRAS-initiated milestone transactions, and design layout record upload response transactions. Milestone transactions and acceptance transactions for a specific request can only occur after the provisioning data packet for that request is initially sent from ARMS.

The provisioning data packets, denoted at block 52 in FIG. 2, contain three types of records: a header record, application records, and a trailer record. The header record identifies the user/customer which ordered the service, the purchase order number (PON) associated with the service, a record type (REC-TYPE) and a request mode. The header record also records the total number of records in the provisioning data packet and the total number of circuit records included in the packet. One and only one header record is allowed per packet and must precede the application records. The header record has a REC-TYPE of "H".

The application records contain the provisioning data needed by CIRAS for a single access service request or Intra-LATA order. There are three types of application records: administrative records, milestone records, and circuit records. Administrative records have a REC-TYPE of "A." One and only one administrative record is sent in a provisioning data packet. The administrative record is the first application record in a packet and follows the header record. Milestone records have a REC-TYPE of "M". One and only one milestone record is sent in a provisioning data packet. The milestone record is the second application record in a packet and follows the administrative record. The circuit record has a REC-TYPE of "C". There may be one or a plurality of circuit records in a provisioning packet. Finally, the trailer record is used to indicate that the provisioning data packet is complete. One and only one trailer record is allowed per packet, and must follow the last circuit record in the packet. The trailer record has a REC-TYPE of "T".

As mentioned above, several different types of transactions are possible when a circuit order is placed by a customer. In the event that the circuit order contains a request mode (REQ-MODE) for a new circuit, this is designated as an initial transaction and identified with an "I" in the REQ-MODE field of the header record. The "I" identifies the transaction as the first time the purchase order number (PON) associated with a circuit order has been sent to CIRAS 14. In certain instances, existing circuits require correction. When a correction to a provisioning data packet is necessary, the entire packet is sent with a "C" in the REQ-MODE field of the header record. Some corrections result in changes impacting the circuit design, while others are informational only. In accordance with the present invention, CIRAS 14 is capable of processing the correction transactions to determine which corrections are informational only and which have an impact on the circuit design.

If a customer requests the cancellation of an existing circuit, a cancel transaction is necessary, wherein the provisioning data packet is sent with a "K" in the REQ-MODE field of the header record. A cancel transaction will be sent to CIRAS 14 when a cancel order is received in ARMS 12 from a customer. The cancel transaction packet contains only a header record, the administrative record, and the trailer record, in that sequence. In this circumstance, the cancel transaction is sent to cancel all circuits associated with the PON identified in the header record.

Another type of transaction is a resend transaction which indicates that certain circuit order information was previously sent to CIRAS 14 and should exist in the CIRAS database, but either ICSC or field engineers requested that the information be resent. When a resend transaction is necessary, the entire provisioning data packet is sent with an "R" in the REQ-MODE field of the header record. If the PON in the transaction packet does not exist on the CIRAS database, it will be added. If the PON does exist on the CIRAS database, no action will be taken in CIRAS.

The provisioning header record in the provisioning data packets includes such information as the transaction type of circuit order (initial send, cancel, correction, resend), the total number of records being sent in a particular packet, the number of circuits to be sent in a particular packet, and date and time information relating to the order. Table 4 below sets forth the types of data and a description of the fields contained in the provisioning header record:

The provisioning administrative record includes significantly more information than the header record, such as whether the order is an access order or a non-access order, the ARMS activity code, specifics relating to the location of the circuit order, etc. Table 5 below provides a detailed listing of the types and number of fields contained in the administrative record:

The provisioning milestone record contains information relating to target dates for completing certain aspects of the circuit order. For example, the provisioning milestone record contains information relating to the service order issue date, the plant test target date, and the due date target. Table 6 below provides details relating to the types and number of fields contained in the provisioning milestone record:

The provisioning circuit record contains considerable information relating to the design criteria and specific location of a circuit requested in a particular order. Table 7 sets forth details relating to the information contained in the provisioning circuit record:

Referring still to FIG. 2, in addition to the provisioning data packets 52, ARMS 12 also initiates milestone transactions denoted by block 54. These transactions are initiated to update milestone target dates associated with particular circuit orders. Milestone target dates may be updated in ARMS 12 to set jeopardies, to change any or all of the target dates, or to add actual dates. These updates can occur independently of other order activity and/or changes to the order. When such independent action occurs, the information is sent to CIRAS 14 from ARMS 12 in a stand-alone milestone transaction packet. In this situation, neither a header record nor a trailer record are required. In this transaction, a REQ-TYPE of "J" and the milestone record format is used.

As shown in FIG. 2, CIRAS 14 also initiates several transactions that are communicated to ARMS 12. One important transaction relative to the present invention is the engineering order confirmation (EOC) messages. In accordance with the invention, an EOC message is automatically generated by CIRAS 14 and contains detailed information relating to the status of the telecommunications service ordered by a particular customer. For example, EOC messages indicate whether the telecommunications circuit orders as transmitted in the provisioning data packets have been accepted by CIRAS, or whether errors are present in the provisioning data packets. The engineering order confirmation messages are denoted by block 56 in FIG. 2.

EOC messages are transmitted to ARMS 12 via a data transaction packet similar to the provisioning data packets transmitted from ARMS 12 to CIRAS 14. EOC transaction packets are used to communicate to ARMS 12 that a provisioning data packet was received and processed by CIRAS 14. CIRAS 14 sends a REC-TYPE "F" for every record received in the provisioning data packet except the trailer. The EOC header record data contains the initial date and time that the provisioning data packet was sent. The EOC records following the header record inform ARMS 12 if the circuit order was accepted as sent, or if the circuit identification was corrected. If the circuit identification was corrected, then the corrected circuit identification will be provided in the EOC record.

The EOC records contained in the EOC data transaction packet include a field titled F-STATUS-IND which indicates whether the provisioning data packet was accepted. An F-STATUS-IND field is included in the EOC transaction packet for each circuit order contained in a provisioning data packet sent from ARMS 12. If the first F-STATUS-IND is set to "NO" on the EOC record following the provisioning data header, this indicates that the entire provisioning data packet was rejected by CIRAS 14. Subsequent F-STATUS-IND fields may be checked, and may be found to contain "OK." This capability is provided to inform ARMS 12 of the particular records that are acceptable versus the records which failed. Only after all records in the provisioning data packet pass CIRAS validation, i.e., have a F-STATUS-IND of "OK," will the first F-STATUS-IND on the header be set to "OK."

Table 8 sets forth details relating to the information contained in the EOC transaction packets:

In addition to the EOC transaction packets, CIRAS 14 initiates several other transactions. For example, as denoted at block 58 of FIG. 2, CIRAS 14 generates acceptance transaction messages in response to milestone transactions 54 initiated by ARMS 12. Acceptance transactions 58 include an acceptance transaction record for jeopardy/date changes used to communicate to ARMS 12 that a milestone transaction was received and processed by CIRAS 14. Block 60 of FIG. 2 denotes milestone transactions that are initiated by CIRAS 14 rather than ARMS 12. Milestone transactions 60 include a milestone transaction record for jeopardy/date changes and are used to communicate to ARMS 12 that milestone information requires updating. This record is used to set jeopardies, and to add actual dates. The milestone record layout is similar to the layout for provisioning milestone record transactions referred to in Table 6 above, except that the REC-TYPE is "J" instead of "M." In response to milestone transactions 60 initiated by CIRAS 14, ARMS 12 generates acceptance transactions denoted at block 62 to indicate that milestone transactions 60 were received and processed by ARMS 12.

As mentioned above in connection with FIG. 1, CIRAS 14 generates automated design layout records containing design parameters for the telecommunications circuit orders and communicates the design layout records to ARMS 12. In FIG. 2, block 64 denotes the automated design layout records that are initiated by CIRAS 14 and transmitted to ARMS 12. In the present invention, block 64 comprises a design layout record (DLR) upload transaction. Details relating to the various fields contained in the DLR upload transaction record layout are listed below in Table 9:

In response to the DLR upload transaction 64 initiated by CIRAS 14, ARMS 12 generates DLR upload response transactions denoted at block 66 of FIG. 2. The DLR upload response transactions 66 send one response file record as a response for each DLR upload transaction file record contained in transaction 64. Each response file record contains either a message accepting the DLR upload transaction file record, or a set of error messages associated with the design layout record. For example, error messages can be sent indicating that the DLR needs to be resent to ARMS, or that the DLR was rejected. In cases of rejection, error messages are sent from ARMS 12 specifying edit errors in the DLR administration section, and the DLR design section, for example.

FIG. 3 is a block diagram illustrating the circuit order interface flow for the telecommunications circuit provisioning and administration system 10 shown in FIG. 1. In particular, FIG. 3 illustrates further details of the CIRAS order functions component 20 of CIRAS 14. As shown in FIG. 3, ARMS 12 communicates provisioning data packets identified by PONs to a receive router 68. The receive router is capable of determining which type of circuit order (SSO, TCO or FCO) has been received. Depending on the type of circuit order, the router 68 will transmit the information contained in the provisioning data packets to one of three processors. As shown in FIG. 3, CIRAS order functions component 20 includes an SSO processor 70, a TCO processor 72, and an FCO processor 74. As described in greater detail below in connection with FIG. 4, the processors 70, 72 and 74 process the information contained in the provisioning data packets and generate EOC messages of the type explained above. Generally, order processors 70, 72 and 74, among other functions, determine whether an order relating to a telecommunications circuit requests a new circuit, a change to an existing circuit, or cancellation of an existing circuit.

In connection with the processing of TCOs and FCOs, a TCO processing screen flow 76 and an FCO processing screen flow 78 are shown. These are included in FIG. 3 to indicate that a manual validation check is performed by CIRAS personnel before EOC messages for TCOs and FCOs are sent to ARMS 12. By contrast, EOC messages for SSOs do not require a manual validation check, and are thus generated immediately after receipt of circuit orders from ARMS 12. As shown in FIG. 3, the outputs of processor 70 and processing screen flow components 76 and 78 feed into a transmit router 80. The transmit router 80 transmits the EOC messages generated by CIRAS 14 to ARMS 12.

FIG. 4 is a detailed flow diagram illustrating the order process flow for the circuit order interface flow shown in FIG. 3. The process flow of FIG. 4 applies to all types of circuit orders, i.e., SSOs, TCOs and FCOs. As explained above in connection with FIG. 3, a provisioning data packet identified by a PON is received by router 68 which then routes the information to the applicable order processor. Once in an order processor, the process flow shown in FIG. 4 begins. First, the various types of PON information are validated. As shown in FIG. 4, in the first step 82, the PON header information is validated. Next, in step 84, the PON administrative information is validated, and then the PON milestone information is validated in step 86. If an error is detected in any of these validation steps 82, 84 or 86, the PON will not be accepted and appropriate error messages will be transmitted to ARMS 12.

When the validation steps are completed, the various order processors compare the current PON information with the last version of that PON previously sent by ARMS 12. In other words, ARMS 12 frequently sends provisioning data packets identified by an existing PON in order to change or update the circuit order information associated with that PON. In this situation, it is necessary for the order processors of CIRAS 14 to determine the particular changes made to circuit orders associated with an existing PON. For example, if ARMS 12 transmits a PON to CIRAS 14 at the beginning of a week, it may then send the PON to CIRAS 14 again two days later if the customer ordered changes to the circuits associated with that PON. In this instance, CIRAS 14 has two different versions of the file for that PON. CIRAS 14 must determine what changes were made to the provisioning data associated with that PON. Thus, in step 88, the current version of a PON is compared with the previous version of the PON to compare the administrative information in the provisioning data packet. Then, as shown in step 90, the current milestone information is compared with the previous milestone information associated with that PON. Finally, at step 92, the current circuit information is compared with the previous circuit information of that PON to identify what changes, if any, were made. During this comparison process, CIRAS 14 produces automated remarks that inform a remote location implementing the circuit orders of every field that was changed, and exactly what changes occurred.

An important aspect of the present invention is the ability of CIRAS 14 to keep track of the various PONs and the changes made to PONs over time. This feature is particularly important for tracking changes to circuit information. In step 92 of FIG. 4, the circuit information of a new PON version is compared with an existing version of the same PON to determine whether the new PON relates to a new circuit order, or changes to or cancellation of an existing order.

Table 10 shown below illustrates the comparison process that CIRAS 14 performs for comparing circuit information according to step 92 of FIG. 4:

In step 92, the order processors determine if existing versions of a particular PON exist. A table similar to Table 10 shown above is generated to identify the particular circuit order changes. For each circuit order associated with that PON, the data in the columns of Table 10 is updated. As can be seen, there are two components of the circuit information comparison table: one set of columns for the new version of the PON and another set of columns for the existing version of the PON. Three columns of information are generated for each PON version: a reference number column, a circuit identification column, and a Leg activity column. The PON activity can be divided into four categories: (1) a new PON and therefore all new circuit activity or an existing PON but new circuits on the PON, (2) circuit number changes, (3) updates/changes to circuit information, and (4) delete/cancel of circuits. As part of the comparison process, certain comparison rules are implemented to determine the changes that have occurred between the new version of the PON and the existing version. These comparison rules can be summarized as follows:

1. Find circuit ID matches and changed reference numbers.

2. Find reference number matches and circuit number changes.

3. Find new circuit IDs and their Leg activity requests.

4. Find missing Cancel Legs.

In the example illustrated in Table 10, the following actions are processed by the comparison circuit process step 92 of FIG. 4. First, referring to the existing PON table, existing PON leg activity "kill/cancels" are never considered for comparison. Therefore, in Table 10, Reference No. 4 in the new version table will not be considered as a "circuit number change" request. As for the actual comparison rules, the circuit IDs are first matched. Therefore, in Table 10, Reference No. 1 in the new PON version corresponding to circuit A is an update to Reference No. 1 on the old version. Reference No. 2 on the new PON version corresponding to circuit C is an update to Reference No. 3 on the old version. Under the second comparison rule, circuits already matched are excluded and reference number matches are searched. Therefore, in the example of Table 10, Reference No. 5 on the new PON version corresponding to Circuit H is a circuit number change to Reference No. 5 on the old version corresponding to Circuit E. Third, the circuit and reference number matches are excluded and implied additions (i.e., new circuit IDs) are searched. In Table 10, Reference Nos. 3 (circuit D) and 4 (circuit F) on the new PON version are new additions. Finally, the comparison process excludes circuit matches and reference number matches and searches for implied deletes (i.e., missing Cancel Legs). In the example, as can be seen, Reference Nos. 2 (circuit B) and 6 (circuit G) of the existing PON version are deletes.

Following the completion of comparison process steps 88, 90 and 92, the PON circuit information is validated as indicated in block 94 of FIG. 4. Thereafter, as indicated by decision block 96, because the validation and comparison processes have been completed, a determination is made as to whether the PON has been accepted. If the PON has not been accepted, CIRAS 14 will transmit an EOC message specifying the particular problem with the PON. This process flow is described in FIG. 4 at line 100 which connects to block 114 designating the completion of an EOC packet. If the PON has been accepted as shown by line 98, then the order processing flow continues as explained below.

First, as indicated in block 102, the order processors set up additional order actions. In other words, if a particular PON requires that certain action be taken with respect to a circuit, step 102 would set up two order actions for the circuit. For example, a particular PON may require that a circuit ID be changed for an existing circuit. Because the circuit has already been implemented under the incorrect circuit ID, two order actions will be required to change the circuit ID: (1) delete old circuit, and (2) create new circuit. These order action setups are performed at step 102.

Next, if a PON requests a new circuit, step 104 will create new circuit orders for each circuit in a PON. At step 106, existing circuit orders are canceled if that action is requested in a PON. Following this, at step 108, the process provides a circuit number change notification for specific circuits on a PON if that is part of the requested action. Thereafter, existing circuit orders are updated as required at step 110. Then, CIRAS 14 calculates critical dates as indicated in step 112 which are internal engineering deadline dates established by CIRAS 14 in relation to the milestone dates designated by ARMS 12. Finally, as shown in step 114, EOC packets are completed by generating a trailer record. The EOC messages are sent to ARMS in the manner discussed above in connection with FIGS. 1-3.

In connection with the order processing described above and as illustrated in FIG. 4, CIRAS 14 follows several rules in processing the orders. These rules can be summarized as follows:

1. If CIRAS 14 receives a new order, correction order, or a cancel order for a PON, and the transaction is rejected by the applicable order processor, then no changes will occur to any existing CIRAS data.

2. If CIRAS receives a new order with confirmation and it is determined that the PON already exists in CIRAS, then the order will be rejected with the following error messages:

a. "Initial (I) PON add was requested, but PON already exists," and

b. "Resend (R) to confirm, or send as correction (C)."

3. If CIRAS receives a new order without confirmation, and it is determined that the PON already exists in CIRAS, then the order will be accepted and processed as a correction order without confirmation.

4. If CIRAS receives a cancel order and it is determined that the PON does not exist in CIRAS, then the order will be rejected with the following error message: "Cancel (K) requested, but PON not found."

5. If CIRAS receives a cancel order with confirmation but the header record REQ-MODE is set for Correction (C), then the order will be rejected with the following error message: "SUPP 1 found on Correction (C). Resend (R) to confirm cancel."

6. If CIRAS receives a correction order with confirmation, and it is determined that the PON does not exist in CIRAS, then the order will be rejected with the following error messages:

a. "Correction (C) requested, but PON not found"; and

b. "Resend (R) to confirm new PON, or send as initial (I)."

7. If CIRAS receives a correction order without confirmation, and it is determined that the PON does not exist in CIRAS, then the order will be accepted and processed as a new order without confirmation.

8. If CIRAS receives a cancel order, then all circuit orders will be canceled for the PON, subject to the above rules.

Further details of the logistics of the error processing performed in CIRAS 14 will now be described. Under normal processing, ARMS 12 sends CIRAS 14 an order. CIRAS 14 validates the order with no errors and sends an EOC message back to ARMS indicating acceptance of the order. In a situation involving normal processing with a confirmation step, there are two possibilities. First, CIRAS 14 may have detected a change to an order indicative of some type of miscommunication between CIRAS 14 and ARMS 12. Alternatively, normal processing with a confirmation step could be indicative of a situation in which CIRAS 14 detects a change having great impact on the CIRAS circuit data, i.e., "mass change" processes. Examples of the first type of transaction requiring the confirmation step include situations similar to that mentioned above in Rules 2, 4, or 7, where ARMS 12 sends an order for a new PON but CIRAS 14 already has that PON, or where ARMS 12 sends an update for a PON that CIRAS 14 should already have but CIRAS 14 does not have it. Under both of these situations, CIRAS 14 will ultimately accept the order on a resend. However, the first attempt at processing will result in an EOC rejection posted to the ARMS error log. In the first situation, possible causes of the problem could be that the ICSC representative simply entered the wrong PON. Alternatively, it is possible that CIRAS 14 has some existing circuit orders which reference an incorrect PON, in which case an engineer should correct the circuit order in error so that the proper PON from ARMS 12 will not be combined with corrupted data in CIRAS 14. In either of these cases, ARMS 12 would be required to resend the order after error resolution, since the initial send of the order concluded with an EOC rejection.

An example of the "mass change" type of transaction requiring the confirmation step is a circuit number change request. In this situation, ARMS 12 sends an order to CIRAS 14 which CIRAS 14 validates and processes normally. Thereafter, ARMS 12 might send a correction order which references a different circuit identification for a reference number received on the previous version. CIRAS 14 is capable of making the circuit number change, but doing so will result in mass changes to all active circuit orders referencing the circuit, all existing master and special circuits for the circuit, and all facilities the circuit is positioned on. Therefore, CIRAS 14 verifies that the change was intentional, and does so by sending ARMS 12 an EOC rejection on the first receipt of a circuit number change request. Again, an ICSC representative at ARMS 12 must resend the order to confirm that a circuit number change was intended.

In the circuit number change process, it should be understood that CIRAS 14 cannot detect a circuit number change unless one order transmission from ARMS 12 has already been received and accepted. Unless this has occurred, CIRAS has nothing to compare reference numbers against, or to detect that the circuit number for a reference number has changed.

To illustrate a circuit number change process, assume ARMS 12 has an order to change an existing circuit requiring processing by CIRAS 14. An ICSC representative at ARMS 12 enters the order using the circuit numbers believed to be correct. CIRAS 14 receives the Order and determines that the circuit IDs are not on file, and thus sends ARMS an EOC rejection notice. The EOC rejection notice prompts an ICSC representative to contact CIRAS engineering personnel to determine the problem with the circuit. Engineering discovers that the circuit does exist, but by a different name than the one sent on the order. At this point, the ICSC representative must perform the following acts to accomplish a circuit number change without requiring engineering assistance: (1) send CIRAS a correction order referencing the circuits by the identification known to CIRAS; (2) send CIRAS a correction order referencing circuits by the identification desired by ARMS; and (3) resend the correction order to confirm that a circuit number change was intended. Alternatively, if ICSC is willing to coordinate with engineering, they could perform the following acts: (1) contact engineering and ask that engineering use special ICSC authority to perform a circuit number change; and (2) resend the order. In summary, it is important to note that final resolution to a problem is initiated by ARMS 12. CIRAS engineering personnel may correct a problem in CIRAS, but CIRAS does not initiate correction orders. Therefore, unless ICSC re-sends orders which appear in the ARMS error log with an EOC rejection notice, ARMS 12 will be out-of-sync with CIRAS 14, not actually knowing whether CIRAS 14 corrected the error issues.

The error processing conducted by CIRAS 14 is also capable of detecting data integrity problems. Such error processing occurs when ARMS 12 sends CIRAS 14 an order and CIRAS 14 detects data integrity problems which must be corrected before the order can be processed. The corrupted data could exist in either ARMS 12 or CIRAS 14. An example of data integrity problems requiring error processing is an order which contains a Leg activity request of "Change Leg" for a circuit ID that CIRAS does not have on file. In this case, CIRAS 14 cannot process the order until it is determined whether: (1) the circuit ID is incorrect on the order, (2) the circuit ID is correct, but not in the circuit files of CIRAS, or (3) the circuit ID is correct, but CIRAS knows the circuit by a different name. Under the first scenario, ICSC would correct the problem using ARMS 12 and then resend the order to CIRAS 14. In the second scenario, CIRAS-based engineering personnel would correct the problem using CIRAS 14, and then ICSC would resend the order to CIRAS 14. In the third scenario, the problem could be corrected by either ICSC or CIRAS engineering using either system.

As part of the error processing performed by background order processors 70, 72 and 74 shown in FIG. 3, CIRAS 14 generates several different categories of error processing messages. One category consists of informational messages sent by CIRAS 14 in the EOC packet. These informational messages have no effect on whether the provisioning data packet will be accepted or rejected as indicated in the EOC packet. However, the messages do provide certain information on the status of the circuit orders contained in a provisioning data packet. Examples of the informational messages provided by CIRAS include: (1) provisioning data packet accepted; (2) provisioning data packet rejected; (3) FCO portion of PON waiting on SSO approval (i.e., occurs when an entire PON has been rejected because SSO errors are present even though the facility portion of a PON is acceptable); (4) FCO portion of PON waiting on TCO approval; (5) secondary location not found; (6) primary location not found; (7) duplicate circuit ignored, etc. Those skilled in the art are familiar with the different types of informational messages that may exist with respect to provisioning data.

Another category of order processing errors are soft error messages. Soft error messages are actually warnings, although a provisioning data packet with a soft error message is rejected. However, the soft errors can be ignored if ARMS performs a resend of the identical provisioning data packet. An EOC message for a provisioning data packet contains this type of error message only when a PON is dispatched initially or re-dispatched (i.e., sending a change or correction to an existing PON and informing CIRAS of the change or correction for the first time). Examples of soft error messages include: (1) circuit leg already completed on SSO number, TCO number or FCO number requiring a new PON; (2) initial PON add was requested but PON already exists; (3) correction requested but PON not found; (4) resend to confirm new PON or send as initial PON; (5) circuit ID for reference number in conflict with previous version of PON; (6) reference number exists in CIRAS for this PON but was not found in this provisioning data packet, etc.

The third type of error processing messages are critical error .messages resulting in rejections. When an EOC message contains an error of this type the provisioning data packet was rejected for a reason requiring manual intervention for correction. Critical error messages require that the provisioning data packet be processed again. Examples of critical error messages include instances where the PON needs correction in ARMS, a validation table in CIRAS requires updating, various types of identification information is invalid, milestone dates are invalid, circuit type is invalid, and various additional circuit design parameters are invalid. As should be understood, many of the critical error messages are identified and generated in the validation processing steps 82, 84, 86 and 94 explained above in connection with FIG. 4.

The final type of error processing messages are system error messages. The nature of system error messages are so severe that the EOC packet cannot be built. System error messages are viewable in the batch error log in CIRAS. System errors have nothing to do with the business function or logic, but rather the system software, databases, network, and/or hardware. System error messages are process terminating, which essentially means that ARMS 12 will not see these errors. Thus, system errors must be viewed via the CIRAS exception log displays. CIRAS 14 would be prompted to search the batch error log file if ARMS informs CIRAS that a provisioning data packet was previously sent and the provisioning data packet can be found on the CIRAS receive log, but corresponding information for the provisioning data packet cannot be found on the CIRAS sent log or the sent log information is incomplete, i.e., the sent trailer is missing.

As mentioned previously, an important feature of the present invention is the ability of CIRAS 14 to generate automated circuit layout records for the telecommunications circuit orders contained in a provisioning data packet. The circuit layout records basically comprise a computer-generated engineering design record containing design parameters for a telecommunications circuit order. FIG. 5 is a flow diagram illustrating the software-assisted engineering process flow for special service circuit orders. In the following discussion, it should be understood that many of the processing steps and details relating to SSOs are common also to TCOs and FCOs. Thus, the following description of the software-assisted engineering process for SSOs generally applies to TCOs and FCOs, although certain specific details relating to TCOs and FCOs will be provided below.

In the initial step of the process flow, an order is placed in a hold area (ASR) as indicated at step 116 of FIG. 5. In this step, edits are cleared in both ARMS 12 and CIRAS 14, and CIRAS 14 accepts the order. In step 118, the circuit parameters for a circuit order are determined. In this step, both the primary and secondary network channel (NC) codes and network channel interface (NCI) codes are determined. Additionally, the system populates the loop and assignment makeup (LAM) date. In step 120, an order assignment is made. The order assignment can be automatic, an analyst can make the assignment, or an engineer can self-assign the order. Next, in step 122, CIRAS 14 receives the loop makeup. The loop makeup includes the associated loss and characteristics, and should be accomplished prior to selection of central office equipment. The loop makeup must include the common language location identifier (CLLI) code of the customer location. Following this step, the carrier facility assignment (CFA) facility code is verified in step 124. In this step, CIRAS 14 determines whether the CFA is from its own company or that of another company. The verification step also determines if the CFA matches a facility in its own system.

In step 126, additional routing is determined. In this step, CIRAS 14 will determine the most efficient routing among the following choices: direct origination point (A) to termination point (Z), A to data acquisition and control system (DACS) to Z, or A to Z with back to back. The next step in the software-assisted engineering process flow is the engineering of the circuit itself as indicated in step 128. For purposes of engineering a SSO circuit, the following information must be available: network priority code, equipment (office and customer), type (FX, FD, FA, LG, DID), network channel code, network channel interface code, secondary network channel interface code, end user customer address, far end/bridge of origination point, serving office of termination point, dates (both due and critical), loop makeup, master circuit, and expected measure of loss (EML). In accordance with the present invention, all of these parameters are automatically selected and engineered for a particular circuit order.

Once the circuit has been engineered, equipment types are determined in step 130. Here, the customer premise equipment is determined along with the office equipment. Any external requirements are also determined. In step 132, the required equipment is ordered. These requirements are identified and requisitions are issued upon the actual record issue date (ARID). The ARID is also automatically populated with the system date and time. Next, the automated circuit design is confirmed by an engineer as indicated in step 134. In this step, the circuit is either approved or rejected by an engineer. If rejected, a decision is made on the aspects of the design requiring change, and any changes are processed.

If the circuit is approved, then the process continues to generate the automated design layout record which is transmitted to ARMS 12 as indicated in step 136. The design layout record is automatically generated after ARID. Thereafter, the automated circuit layout record is generated in step 138. Distribution of the circuit layout record is determined by the office involved and the network channel codes. As the final step in the automated engineering process, the ARID dates are completed. Here, error dates are completed and material requisitions are sent.

As stated above, the automated engineering process flow discussed above also generally applies to TCOs and FCOs. With respect to TCOs, certain additional points should be noted. First, the TCO order is received with a carrier facility assignment and an ECCKT. In this step, a decision/search for channel type is made over all existing spares. The system selected is based on access; if there is not access, then the next available system is selected. In order to perform software-assisted engineering for TCOs, the following parameters are determined: location A, location Z, TSC, CSPC, quantity (trunk range), critical dates, NC/NCI, CFA, traffic use, traffic class, office class, modifier, pulsing, TCIC (if SS7), and diversity. Moreover, in certain instances CIRAS 14 will bypass software-assisted engineering for trunk circuit orders. For example, if switch A or switch Z is analog, then the circuit layout record will be manually engineered. Additionally, if the facility is analog, then the circuit will be manually engineered. Also, only trunks that are wholly-owned by the system's operating company will be designed through software-assisted engineering; otherwise, any trunk circuit design to another local exchange carrier will be manual.

For facility circuit orders, the following facility data parameters are determined in the software-assisted engineering process: location A, location Z, quantity, NC/NCI, secondary NCI, NPC-diversity, CFA (access), and customer. Certain limitations also apply for software-assisted engineering of facility circuit orders. First, software-assisted engineering will be performed only if one route is available; otherwise, manual design will be performed. Also, the system will utilize software-assisted engineering only if spare equipment is available. CIRAS 14 also provides the option of rejecting the automated facility circuit design and manually engineering the design. If there is a facility disconnect order, the circuit must be removed before the system disconnect can be completed. Also, spare channels on a disconnected system must be marked pending disconnect so they will not be selected for new assignment.

Through the above-described software-assisted engineering process, the system of the present invention provides significant advantages over existing provisioning systems. Namely, the ability to provide automated circuit layout and design layout records substantially reduces the amount of manual intervention currently required for circuit design. Consequently, these automated records are provided more efficiently and with reduced costs in both time and resources. This measured efficiency arises from the capability of the present invention to monitor and keep track of circuit components and equipment and automatically select the available components and equipment required to fulfill circuit orders.

As is evident from the foregoing description, the present invention provides a telecommunications circuit provisioning and administration system that accepts circuit orders from an order entry system operating on a mainframe computer system and generates engineering order confirmation messages from a circuit administration system which runs on a distributed platform. The engineering order confirmation messages immediately inform the order entry system whether the circuit orders were accepted as sent or if the circuit order was rejected. The present invention also is capable of producing automated circuit layout records for telecommunications circuit orders and automatically transmitting these circuit layout records to field personnel for circuit implementation. Finally, the present invention produces automated design layout records which contain information relating to the circuit design parameters. These design layout records are automatically transmitted back to the order entry system. The above information exchange is possible through the interface of the present invention, which is capable of providing real-time communications relating to circuit orders between mainframe and distributed computer systems.