US 5,680,587 AGrant

Enhanced-Performance Floppy Diskette Subsystem

Issue Date:1997-10-21

•41 Claims

•4 Drawing Sheets

Abstract

An enhanced-performance floppy diskette subsystem, which operates many times faster than a conventional floppy diskette subsystem, includes both an enhanced-performance floppy diskette drive and floppy diskette drive controller. The diskette drive rotates a floppy diskette two or more times faster than that of a conventional floppy diskette drive, and includes two separate and independent read/write ("R/W") channels. To provide enhanced-performance, the floppy diskette drive controller includes a DRAM cache that maintains an image of the data recorded on a floppy diskette present in the floppy diskette drive. Two separate and independent floppy disk drive controller channels respectively interface between the cache memory and the R/W channels included in the enhanced-performance floppy diskette drive. Operating in this way, both heads of the enhanced-performance floppy diskette drive concurrently record data from the cache onto a floppy diskette, or reproduce data from a floppy diskette for storage into the cache. To a computer program executed by a host microprocessor, the enhanced-performance floppy diskette mimics the operation of a conventional floppy diskette subsystem.

Metadata

Assignee

Computer Performance Inc.

Inventors

Martin J. Bodo
Robert A. Rosenbloom

Application Information

Application Number:US 4322398

Filing Date:1995-05-01

Priority Date:1995-05-01

Art Unit:234

Classifications

IPC:

G06F 1312

Field of Search:

395500

Patent Drawings (4 sheets)

Description

Background of the Invention

1. Field of the Invention

The present invention relates generally to the technical field of digital computer magnetic recording subsystems and, more particularly, to floppy diskette recording subsystems.

2. Description of the Prior Art

Floppy diskette subsystems included in digital computer systems store and retrieve digital data that is recorded along tracks formed on both side surfaces of a thin, circularly-shaped, double-sided floppy diskette. Presently, floppy diskette subsystems adapted for use in IBM.RTM. Personal Computers ("PC") and IBM PC clone digital computers are backward compatible with floppy diskette subsystems included in the original IBM PC model XT and model AT digital computers of the early 1980's. A combination of considerations arising from the desire to maintain backward compatibility between present floppy diskette subsystems and floppy diskette subsystems used in personal computers of ten (10) years ago has contrived to inhibit improving the performance of floppy diskette subsystems.

Referring to FIG. 1, a floppy diskette subsystem, referred to by the general reference character 10, includes a floppy diskette controller 12, which may be a card that plugs into a socket 14 of a mother board bus 16 included in an IBM PC XT or AT or IBM PC clone computer. Digital logic circuits included in the floppy diskette controller 12 provide an interface for exchanging digital command, status, and data signals between the floppy diskette controller 12 and the mother board bus 16. The digital logic circuits in the floppy diskette controller 12 also provide an interface for exchanging digital command, status, control and data signals via a ribbon cable 18 with a floppy diskette drive 22 included in a computer. Accordingly, the digital logic circuits of the floppy diskette controller 12 constitute a floppy diskette controller channel 24 for exchanging digital data between a floppy diskette drive 22 and the mother board bus 16. Presently, integrated circuits ("ICs") are commercially available which provide in a single IC package all the digital logic circuits required for interfacing a floppy diskette drive 22 to the mother board bus 16 included in an IBM PC XT or AT, or IBM PC clone computer.

All floppy diskette drives 22 regardless of type include several basic common components. Every floppy diskette drive 22 includes a mechanical spindle 32 that receives and secures a thin, annularly-shaped floppy diskette 34, shown in phantom in FIG. 1. The floppy diskette 34 when secured in the floppy diskette drive 22 is rotatable about an axis 36 disposed normal to the floppy diskette 34. Every floppy diskette drive 22 also includes a spindle motor 38 which in present floppy diskette drives 22 rotates the floppy diskette 34 at nominal rotation velocity of 300 revolutions per minute ("RPM") for either 51/4-inch or 31/2-inch diameter floppy diskettes. The 300 RPM rotation speed of a 31/2-inch HD floppy diskette drive 22 causes it to record and reproduce digital data at a fixed, 500 kilohertz ("KHz") bit rate. The 500 KHz data rate of a 31/2-inch HD floppy diskette drive 22 is the highest data rate at which IBM PC XT and AT, and IBM PC clone digital computers record and reproduce digital data using a conventional floppy diskette drive 22 regardless of whether the floppy diskette drive 22 employs a 51/4-inch or a 31/2-inch floppy diskette 34. Moreover, present floppy diskette drive 22 must be rotating at full speed before recording or reproducing digital data.

A floppy diskette drive 22 also includes two read/write heads 42, one head for each surface 44 of a floppy diskette 34. Each read/write head 42 is used both for recording and for reproducing digital data on its respective surface 44 of the floppy diskette 34. Both heads 42 are mechanically secured to a head positioning assembly 46 which moves each read/write head 42 laterally across a surface 44 of a floppy diskette 34 in a direction that is normal to the axis 36 about which the floppy diskette 34 rotates. Electrical pulses applied to a stepper motor, not illustrated separately in FIG. 1, energize movement of the head positioning assembly 46. Such movement of the read/write heads 42 across the surfaces 44 of a floppy diskette 34 provides no feedback regarding the position of the read/write heads 42 in relation to tracks of data recorded on the floppy diskette 34. Consequently, after energizing the stepper motor to move the read/write heads 42 across the surfaces 44, present floppy diskette subsystems 10 insure that the read/write heads 42 are properly positioned in relationship to the tracks on the floppy diskette 34 by merely waiting for a sufficiently long interval of time before recording or reproducing data.

The floppy diskette drive 22 also includes a read/write channel 52 that exchanges data and control signals via the ribbon cable 18 with the floppy diskette controller channel 24. A head switch 54, also included in the floppy diskette drive 22, selectively couples the read/write channel 52 either to one or the other of the read/write heads 42 depending upon which surface of the floppy diskette 34 is presently being used for recording or reproducing digital data. Thus in recording digital data on or in reproducing digital data from the floppy diskette 34, without moving the read/write heads 42 the floppy diskette subsystem 10 first records or reproduces digital data on one surface 44 of the floppy diskette 34, and then on the other surface 44 of the floppy diskette 34. Only after digital data has been recorded or reproduced along a track on both surfaces 44 of the floppy diskette 34 does the floppy diskette controller channel 24 included in the floppy diskette controller 12 cause the head positioning assembly 46 to step the read/write heads 42 to an adjacent track to continue recording or reproducing digital data. Similar to the floppy diskette controller channel 24, presently ICs are commercially available which provide in a single IC package all the electronic circuits required for the read/write channel 52.

The IBM PC XT and AT digital computers did not insulate a computer program which reads and writes data on a floppy diskette 34 from the operating characteristics of the floppy diskette drive 22. Thus, even today there exist computer programs that were written years ago to operate properly with the operating characteristics of the then existing floppy diskette subsystems 10, that are still essential for some personal computer uses. Over the years, such computer programs have not been re-written to make them independent of the performance characteristics of the floppy diskette subsystem 10. Consequently, such computer programs could not execute properly using a floppy diskette subsystem 10 designed in the conventional way if it provided performance which differs markedly from that of the original IBM PC XT and AT computers.

In addition to the conventional floppy diskette subsystem 10 depicted in FIG. 1, special purpose, higher performance floppy disk subsystems have been developed which are particularly adapted for use in computer software publishing for only recording digital data repetitively onto a sequence of floppy diskettes. FIG. 2 illustrates such a floppy disk writer subsystem 60. Those elements of the floppy disk writer subsystem 60 depicted in FIG. 2 that are common to the floppy diskette subsystem 10 depicted in FIG. 1 carry the same reference numeral distinguished by a prime ("'") designation. To increase the clarity of FIG. 2, the head positioning assembly 46 has been omitted from the floppy diskette drive 22' illustrated in FIG. 2 although the floppy diskette drive 22' does, in fact, include a head positioning assembly.

The floppy diskette controller 12' included in the floppy disk writer subsystem 60 depicted in FIG. 2 differs from the floppy diskette controller 12 included in the floppy diskette subsystem 10 depicted in FIG. 1 by including two (2) separate and independent floppy diskette controller channels 24a' and 24b'. Each of the floppy diskette controller channels 24a' and 24b' of the floppy diskette controller 12' are respectively coupled, via the ribbon cable 18', to one of a pair of separate and independent read/write channels 52a' or 52b' included in the floppy diskette drive 22'. Rather than being coupled to the read/write heads 42' via a head switch 54, the read/write channels 52a' and 52b' included in the floppy diskette drive 22' are respectively coupled directly to one of the read/write heads 42'. Coupled in this way, the combined floppy diskette controller channels 24a' and 24b', read/write channels 52a' and 52b', and the read/write heads 42', operating in conjunction with a special computer program for writing the floppy diskette 34', concurrently write both surfaces 44' of a floppy diskette 34 rather than alternating back and forth between the surfaces 44 as does the floppy diskette subsystem 10 depicted in FIG. 1.

While the floppy disk writer subsystem 60 offers higher performance in recording and reproducing digital data, the floppy disk writer subsystem 60 is a special purpose unit which is incompatible with the industry standard personal computer architecture. Consequently, only computer programs that repetitively record the same digital data over and over onto a sequence of floppy diskettes have been specifically written for use with the floppy disk writer subsystem 60. That is, conventional computer programs, such as spread sheet or word processing computer programs, cannot record data directly onto or reproduce data directly from a floppy diskette present in a floppy disk writer subsystem 60.

Summary of the Invention

An object of the present invention is to provide an enhanced-performance floppy diskette subsystem.

Another object of the present invention is to provide an enhanced-performance floppy diskette subsystem which is functionally equivalent to a conventional floppy diskette subsystem.

Another object of the present invention is to provide an enhanced-performance floppy diskette subsystem which is compatible with computer programs written for execution on a personal computer which conforms to the industry standard personal computer architecture.

Another object of the present invention is to provide a floppy diskette subsystem which, without host processor intervention, pre-fetches and caches digital data reproduced from a floppy diskette in anticipation of a request from a computer program to access such data.

Another object of the present invention is to provide a floppy diskette subsystem which is capable of reproducing or recording digital data while the floppy diskette accelerates up to its nominal operating speed.

Another object of the present invention is to provide a floppy diskette subsystem which records or reproduces digital data while rotating a floppy diskette at a rate which is faster than that of a conventional floppy diskette subsystem.

Another object of the present invention is to provide a floppy diskette subsystem which commences reproducing or recording data immediately after sensing that a floppy diskette drive's read/write heads are positioned properly in relationship to a track recorded on a floppy diskette.

Another object of the present invention is to provide a floppy diskette subsystem which, without host processor intervention, caches digital data prior to recording that data on a floppy diskette.

Another object of the present invention is to provide an enhanced-performance floppy diskette subsystem which prevents ejecting a floppy diskette until all data cached in the floppy diskette subsystem has been recorded on the floppy diskette.

Yet another object of the present invention is to provide an enhanced-performance floppy diskette subsystem which detects floppy diskette access by a computer program which requires conventional floppy diskette subsystem performance, and which for compatibility with such a computer program reduces the apparent performance of the floppy diskette subsystem to that of a conventional floppy diskette subsystem.

Briefly, an enhanced-performance floppy diskette subsystem in accordance with the present invention includes both an enhanced-performance floppy diskette drive and an enhanced-performance floppy diskette drive controller. The diskette drive motor of the enhanced-performance floppy diskette drive rotates a floppy diskette secured therein at a nominal rotation velocity which is significantly faster than that of a conventional floppy diskette drive. The enhanced-performance floppy diskette drive also includes two separate and independent read/write ("R/W") channels which are respectively electronically coupled to each of the floppy diskette drive's two (2) read/write heads.

The enhanced-performance floppy diskette drive controller exchanges digital command, status, and data signals with a bus of the host computer system via floppy diskette drive controller register emulation logic. The floppy diskette drive controller register emulation logic receives and transmits digital command, status, and data signals which cause the floppy diskette subsystem to provide responses identical to those of a conventional floppy diskette subsystem. The enhanced-performance floppy diskette drive controller also includes a cache memory, which is coupled to the floppy diskette drive controller emulation logic, and which both exchanges digital data with the floppy diskette drive controller emulation logic, and stores exchanged digital data. A microcontroller, included in the enhanced-performance floppy diskette drive controller, is coupled both to the floppy diskette drive controller emulation logic and to the cache memory. The microcontroller exchanges digital data between the floppy diskette drive controller emulation logic and the cache memory so the floppy diskette drive controller emulation logic mimics operation of a conventional floppy diskette drive. The floppy diskette drive controller also exchanges digital command, status, control, and data signals with a head positioning assembly included in the enhanced-performance floppy diskette drive and with the diskette drive motor. Two separate and independent floppy disk drive controller channels, included in the enhanced-performance floppy diskette drive controller, respectively interface between the cache memory and one of the R/W channels included in the enhanced-performance floppy diskette drive. Each floppy disk drive controller channel exchanges digital data with the cache memory while concurrently exchanging digital command, status, control, and data signals with the particular R/W channel of the floppy diskette drive that is coupled to the floppy disk drive controller channel. Operating in this way, both heads of the enhanced-performance floppy diskette drive concurrently record data onto, or reproduce data from a floppy diskette.

These and other features, objects and advantages will be understood or apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiment as illustrated in the various drawing figures.

Brief Description of the Drawings

FIG. 1 is a functional-type block diagram depicting a conventional, prior art floppy diskette drive subsystem including a floppy diskette drive controller and a floppy diskette drive;

FIG. 2 is a functional-type block diagram depicting a special purpose, prior art floppy diskette drive subsystem, including a floppy diskette drive controller and a floppy diskette drive, that is used for software publishing;

FIG. 3 is a functional-type block diagram depicting an enhanced-performance floppy diskette drive subsystem in accordance with the present invention illustrating both an enhanced-performance floppy diskette drive controller and an enhanced-performance floppy diskette drive including the drive's read/write channel;

FIG. 4 is a functional-type block diagram depicting signal lines included in a ribbon cable coupling the conventional floppy diskette drive controller illustrated in FIG. 1 to the conventional floppy diskette drive illustrated in FIG. 1;

FIG. 5, is a functional-type block diagram depicting signal lines included in a ribbon cable coupling the enhanced-performance floppy diskette drive controller depicted in FIG. 3 to the enhanced-performance floppy diskette drive depicted in FIG. 3;

FIG. 6, is a functional-type block diagram depicting a read/write channel included in the enhanced-performance floppy diskette drive illustrated in FIG. 3;

FIG. 7a is an elevational view depicting a portion of a read/write head positioning assembly included in the conventional floppy diskette drive illustrated in FIG. 1;

FIG. 7b is an elevational view depicting a portion of a modified read/write head positioning assembly included in the enhanced-performance floppy diskette drive illustrated in FIG. 3;

FIG. 8 is a functional type block diagram illustrating a FDC register emulation logic included in the enhanced-performance floppy diskette drive depicted in FIG. 3; and

FIG. 9 is a computer memory allocation diagram depicting the address space in which a computer program executed by a host microprocessor accesses the enhanced-performance floppy diskette drive controller illustrated in FIG. 3.

Detailed Description of the Preferred Embodiments

Referring now to FIG. 3, depicted there is a functional-type block diagram of an enhanced-performance floppy diskette drive subsystem in accordance with the present invention referred to by the general reference character 70. Those elements of the enhanced-performance floppy diskette subsystem 70 depicted in FIG. 3 that are similar to elements of the floppy diskette subsystem 10 depicted in FIG. 1 and/or the floppy disk writer subsystem 60 depicted in FIG. 2 carry the same reference numeral distinguished by a double prime (""") designation. Similar to FIG. 2, to increase the clarity of FIG. 3, the head positioning assembly 46 depicted in FIG. 1 has been omitted from the floppy diskette drive 22" illustrated in FIG. 3 although the floppy diskette drive 22" does, in fact, include a head positioning assembly.

The enhanced-performance floppy diskette subsystem 70 includes an enhanced-performance floppy diskette drive 22" and an enhanced-performance floppy diskette controller 12". The floppy diskette controller 12" includes dual separate and independent floppy diskette controller channels 24a" and 24b" which preferably are either a PC8477B (SuperFDC.TM.) Advanced Floppy Disk Controller IC manufactured by National Semiconductor Corporation of Santa Clara, Calif., or an 82078 CHMOS Single-Chip Floppy Disk Controller IC manufactured by Intel Corporation of Santa Clara, Calif. Within the floppy diskette controller 12", operating autonomously through the use of direct memory access ("DMA"), each floppy diskette controller channel 24a" and 24b" fetches digital data to be recorded onto a floppy diskette 34 from a cache memory 72 via a FDC bus 74. Correspondingly, each floppy diskette controller channel 24a" and 24b" stores data reproduced from the floppy diskette 34 into the cache memory 72 via the FDC bus 74 using DMA. The cache memory 72 is preferably a 1.5 mega-byte ("Mbyte") dynamic random access memory ("DRAM").

As described in greater detail in Intel Corporation and National Semiconductor Corporation literature respectively describing the 82078 CHMOS Single-Chip Floppy Disk Controller IC or the PC8477B (SuperFDC.TM.) Advanced Floppy Disk Controller IC, each IC respectively includes a phase locked loop ("PLL") data separator which effects the reproduction of recorded data from the floppy diskette 34. Also, either a crystal (usually either a 24 megaHertz ("MHz") or a 48 MHz crystal) must be directly connected to the floppy diskette controller channel IC to permit generation internally within the IC of a clock signal that is required for the IC's proper operation, or the IC must be supplied with an appropriate clock signal from an external source. Internally, the floppy diskette controller channels 24a" and 24b" respectively use either the 24 MHz or 48 MHz clock signal in establishing an operating mode for the PLL which permits reproducing data read from the floppy diskette 34 either at 250 kilo-bits per second ("kb/s") or at 500 kb/s.

The FDC bus 74 included in the floppy diskette controller 12" also couples the cache memory 72 to FDC register emulation logic 76, which is also coupled, via the socket 14", to the mother board bus 16" included in a host IBM PC XT or AT, or IBM PC clone computer system. Accordingly, the FDC register emulation logic 76 exchanges digital data to be recorded on the floppy diskette 34 or reproduced from the floppy diskette 34 both with the mother board bus 16" and with the cache memory 72. For receiving data to be recorded onto the floppy diskette 34, the combined cache memory 72 and FDC register emulation logic 76 operate at a data rate limited solely by the speed of the mother board bus 16". The combined cache memory 72 and FDC register emulation logic 76 also operate at that same data rate in supplying data reproduced from the floppy diskette 34 if such data is already present in the cache memory 72.

A microcontroller 82 is also coupled to the cache memory 72 via the FDC bus 74, to the FDC register emulation logic 76 via a FDC register emulation control bus 84, and to the floppy diskette controller channels 24a" and 24b" via a controller channels control bus 86. Exchanges of digital data between the microcontroller 82 and the FDC register emulation logic 76 permit the floppy diskette controller 12" to mimic the operation of the conventional floppy diskette subsystem 10. The microcontroller 82 preferably includes a 80C188 manufactured by Intel Corporation, and a 32 kilo-byte ("kbyte") read only memory ("ROM") for storing a computer program executed by the 80C188. The computer program executed by the microcontroller 82 is a real-time executive program which provides timely response to events occurring in the floppy diskette controller channels 24a" and 24b", and in the FDC register emulation logic 76 so digital data is supplied to or received from the floppy diskette drive 22" via the independent floppy diskette controller channels 24a" and 24b" and the read/write channels 52a" and 52b" at the fastest rate practicable.

To facilitate detecting an attempt to access the enhanced-performance floppy diskette subsystem 70 by a computer program that requires conventional floppy diskette subsystem performance for its successful execution, the floppy diskette controller 12" preferably includes a 16 kbyte read only memory ("ROM") basic input/output system ("BIOS") 92. The ROM BIOS 92 stores an input/output routine that is executed by a host microprocessor in facilitating an application computer program's, also executed by the host microprocessor, access to the floppy diskette drive 22". For host IBM PC XT or AT, or IBM PC clone computer systems, such an application computer program attempting to record data on the floppy diskette 34 or to reproduce data from the floppy diskette 34 generally issues a software interrupt 13, also identified as Int 13h. The ROM BIOS 92 stores a software interrupt 13 I/O routine which the host microprocessor executes if an application computer program executed by the host microprocessor issues software interrupt 13 to access the floppy diskette drive 22". If a computer program executed by the host microprocessor accesses the enhanced-performance floppy diskette subsystem 70 through the software interrupt 13 I/O routine stored in the ROM BIOS 92, then the enhanced-performance floppy diskette subsystem 70 operates its high performance operating mode. If, however, a computer program accesses the FDC register emulation logic 76 other than through the software interrupt 13 I/O routine stored in the ROM BIOS 92, the computer program executed by the microcontroller 82 emulates the reduced performance of the conventional floppy diskette subsystem 10.

Similar to the floppy diskette drive 22' depicted in FIG. 2, the enhanced-performance floppy diskette drive 22" depicted in FIG. 3 includes two (2) separate and independent read/write channels 52a" and 52b". However, as will be explained in greater detail below, the read/write channels 52a" and 52b" differ markedly from the read/write channels 52a' and 52b' included in the floppy diskette drive 22' depicted in FIG. 2.

The floppy diskette drive 22" illustrated in FIG. 3 also includes a solenoid 94 which is not present in the floppy diskette drive 22 or 22' respectively depicted in FIGS. 1 and 2. Upon being energized in response to a signal transmitted from the floppy diskette controller 12" to the floppy diskette drive 22" over either a Coil 1 or a Coil 2 signal line included in the ribbon cable 18", the solenoid 94 extends a pin 96 into a mating aperture formed in a diskette eject button 98" which is present in each of the floppy diskette drives 22, 22' and 22". Extension of the pin 96 into the diskette eject button 98" during writing of a floppy diskette 34 locks the button 98" to prevent ejection of the floppy diskette 34 from the floppy diskette drive 22" while data to be recorded on the floppy diskette 34 remains in the cache memory 72.

FIG. 4 depicts signal lines included in the ribbon cable 18 which couples the floppy diskette controller 12, depicted in FIG. 1, to up to four (4) of the floppy diskette drives 22 also illustrated in FIG. 1. The ribbon cable 18 includes a floppy diskette controller connector 102 at one end, and one (1) or more floppy diskette drive connectors 104 distributed along the length of and at the other end of the ribbon cable 18. The most significant difference between the signal lines and connectors 102 and 104 included in the ribbon cable 18 depicted in FIG. 4 and those depicted in FIG. 5 for the ribbon cable 18" which couples the floppy diskette controller 12" to the floppy diskette drive 22" are:

1. that the ribbon cable 18" is adapted for coupling the floppy diskette controller 12" to no more than two (2) floppy diskette drives 22" because the ribbon cable 18" includes only Drive Select 0 and Drive Select 1 signal lines;

2. a Motor On signal line in the ribbon cable 18, which extends from the floppy diskette controller connector 102 depicted in FIG. 4 in parallel to all of the floppy diskette drives 22 respectively connected to the floppy diskette drive connectors 104, is replaced in the ribbon cable 18" by a pair of Motor Select signal lines which respectively supply a motor select signal from the floppy diskette controller 12" to only one (1) of up to two (2) floppy diskette drives 22";

3. a single ended Write Data signal line in the ribbon cable 18, which extends from the floppy diskette controller connector 102 depicted in FIG. 4 in parallel to all of the floppy diskette drives 22 respectively connected to the floppy diskette drive connectors 104, is replaced in the ribbon cable 18" by pairs of differential Write Data- and Write Data+ signal lines which respectively exchange data to be recorded on a floppy diskette 34 between the floppy diskette controller 12" and one or the other of the read/write channels 52a" and 52b" include in each floppy diskette drive 22";

4. a Write Gate signal line in the ribbon cable 18, which extends from the floppy diskette controller connector 102 depicted in FIG. 4 in parallel to all of the floppy diskette drives 22 respectively connected to the floppy diskette drive connectors 104, is replaced in the ribbon cable 18" by a pair of Write Gate signal lines which respectively supply a Write Gate signal from the floppy diskette controller 12" to one or the other of the read/write channels 52a" and 52b" include in each floppy diskette drive 22";

5. a single ended Read Data signal line in the ribbon cable 18, which extends from the floppy diskette controller connector 102 depicted in FIG. 4 in parallel to all of the floppy diskette drives 22 respectively connected to the floppy diskette drive connectors 104, is replaced in the ribbon cable 18" by pairs of differential Read Data- and Read Data+ signal lines respectively for exchanging data reproduced from a floppy diskette 34 between the floppy diskette controller 12" and one or the other of the read/write channels 52a" and 52b" include in each floppy diskette drive 22";

6. a Side 1 Select signal line included in the ribbon cable 18 depicted in FIG. 4 is omitted from the ribbon cable 18" depicted in FIG. 5; and

7. the ribbon cable 18" depicted in FIG. 5 adds the following signal lines to those depicted in FIG. 4 for the ribbon cable 18:

a. an optional Motor Clock signal line; and

b. Coil 1 and Coil 2 signal lines.

While the ribbon cable 18 and the ribbon cable 18" both include a Diskette Change signal line, transmission of a signal over the Diskette Change signal line in the ribbon cable 18" from the floppy diskette drive 22" to the floppy diskette controller 12" operates distinctly differently from transmission of a signal over the Diskette Change signal line in the ribbon cable 18 from the floppy diskette drive 22 to the floppy diskette controller 12. In the floppy diskette subsystem 10, a signal is transmitted from the floppy diskette drive 22 to the floppy diskette controller 12 over the Diskette Change signal line only if a floppy diskette 34 is removed from the floppy diskette drive 22, and if the floppy diskette controller 12 energizes the spindle motor 38. That is, when a floppy diskette 34 is removed from the floppy diskette drive 22 the floppy diskette drive 22 merely stores data recording that event, but does not report the event to the floppy diskette controller 12 until the floppy diskette controller 12 attempts to access a floppy diskette 34 in the floppy diskette drive 22 by energizing the spindle motor 38. Conversely, in the enhanced-performance floppy diskette subsystem 70 the floppy diskette drive 22" transmits a signal to the floppy diskette controller 12" over the Diskette Change signal line immediately upon ejection of a floppy diskette 34 from the floppy diskette drive 22".

The enhanced-performance floppy diskette subsystem 70 must employ this interrupt, as opposed to polling, mode of operation for the Diskette Change signal line because, in most instances, an attempt by a computer program executed by the host microprocessor to retrieve data present on a floppy diskette 34 in the floppy diskette drive 22" does not cause the spindle motor 38" to be energized. Rather, because under most circumstances such data is present in the cache memory 72, the computer program executed by the microcontroller 82 will, in general, provide the computer program executed by the host microprocessor with requested data directly from the cache memory 72 without energizing the spindle motor 38". However, after removal of the floppy diskette 34 from the floppy diskette drive 22" the computer program executed by the microcontroller 82 must not provide data from the cache memory 72 to a computer program executed by the host microprocessor because such data is no longer valid. Accordingly, in the enhanced-performance floppy diskette subsystem 70, a signal transmitted from the floppy diskette drive 22" to the floppy diskette controller 12" over the Diskette Change signal line truly constitutes a "cache flush" signal which directs the computer program executed by the microcontroller 82 to flush all data from the cache memory 72.

Referring now to FIG. 6, depicted there is the read/write channel 52a" or 52b" included in the floppy diskette drive 22". A pair of write data leads 112 respectively couple Write Data+ and Write Data- signals from the floppy diskette drive connector 104" to a differential to single ended signal conversion IC 114. An output signal from the conversion IC 114 is supplied to a clock input 116 of a flip-flop 118. Bipolar output signals from the flip-flop 118 are supplied respectively to inputs 122 respectively of write amplifiers 124a and 124b. Output signals from the write amplifiers 124a and 124b are coupled to the read/write head 42" by a pair of read/write head leads 126". If a signal present on a write gate signal line 128, which is coupled to either one or the other of the Write Gate signal lines included in the ribbon cable 18", enables transmission of an output signal from the write amplifiers 124a and 124b, then the write amplifiers 124 transmit a data writing current through the read/write heads 42". A signal present on a Reduced Write signal line in the ribbon cable 18" is also supplied, via a writing current control signal line 130, to the write amplifiers 124a and 124b. A signal present on the writing current control signal line 130 permits the floppy diskette controller 12 to select between two different writing current levels that may be supplied by the write amplifiers 124a and 124b to the read/write heads 42. The signal transmitted on this line by the floppy diskette controller 12" causes the floppy diskette drive 22" to supply a current which is 70% higher when recording on the inner ten (10) tracks of a floppy diskette 34 than that supplied when recording on the remaining outer tracks of the floppy diskette 34.

The read/write channel 52a" or 52b", as illustrated in FIG. 6, also includes a sense amplifier 132 which has bipolar inputs that are respectively coupled by 0.1 micro-Farad (".mu.F") capacitors 134 to the read/write head leads 126". Accordingly, any electrical signal which varies with time is coupled via the capacitors 134 from the read/write head leads 126" to the inputs of the sense amplifier 132. The sense amplifier 132 supplies bipolar output signals to bipolar inputs of a pulse detector IC 136 via 2200 picofarad ("pF") capacitors 138. The pulse detector IC 136 is preferably a DP8464B Disk Pulse Detector IC manufactured by National Semiconductor Corporation of Santa Clara, Calif. The DP8464B Disk Pulse Detector IC, which is intended for use in hard disk drives, is used in the enhanced-performance floppy diskette drive 22" to accommodate the higher data rates which result from rotation of the floppy diskette 34 by the floppy diskette drive 22" at a maximum speed which is two (2) to three (3) times faster than the 300 RPM maximum speed of the conventional 31/2" floppy diskette drive 22.

As described in greater detail in National Semiconductor Corporation literature describing the DP8464B Disk Pulse Detector IC, proper operation of the DP8464B requires that a filter circuit be connected between bipolar outputs 142 of a gain controlled amplifier, included in the DP8464B. and bipolar time channel and gate channel inputs 144 of the DP8464B. Accordingly, each read/write channel 52a" or 52b" illustrated in FIG. 6 includes a pair of 220 ohm (".OMEGA.") resistors 146 one terminal of which is respectively connected to one of the outputs 142. Connected between the other terminals of the resistors 146 is a 150 pF capacitor 148. Connected to each juncture between the terminals of the capacitor 148 with the terminals of the resistors 146 are terminals of 47 micro-Henry (".mu.H") inductors 152. Connected in parallel between the other terminals of the inductors 152 are a 1000 pF capacitor 154 and a 560 .OMEGA. resistor 156. A pair of 0.01 .mu.F capacitors 158 are respectively coupled between the bipolar time channel and gate channel inputs 144 and the junctures of the terminals of the capacitor 154 and the resistor 156 with the terminals of the inductors 152. Experimental tests indicate that the preceding filter connected between the outputs 142 and the inputs 144 provides optimal results at a data rate of 1.0 MHz while a 31/2" floppy diskette 34 rotates at nominal speed of 600 RPM.

A 100 kilo-Ohm ("k.OMEGA.") resistor 162 connected in parallel with a 0.1 .mu.F capacitor 164 are coupled between an automatic gain control circuit input 166 of the pulse detector IC 136 and circuit ground. The resistor 162 connected in parallel with the capacitor 164 establishes a 10 millisecond time constant for an automatic gain control circuit included in the pulse detector IC 136.

In addition to receiving the output signals from the sense amplifier 132, a not-read/write input 168 of the pulse detector IC 136 also receives the signal present on the write gate signal line 128. When the signal present on the write gate signal line 128 enables the write amplifiers 124a and 124b for transmitting a write current to the read/write head 42", that same signal applied to the not-read/write input 168 also reduces the sensitivity of the gain controlled amplifier included in the pulse detector IC 136, suppresses any output signal from the outputs 142, and freezes the current gain of the automatic gain control circuit included in the pulse detector IC 136.

An encoded data output 172 of the pulse detector IC 136 supplies an output signal to a single ended to differential conversion IC 174. Output signals from the conversion IC 174 are respectively coupled via a pair of read data leads 176 and the floppy diskette drive connector 104" to one of the pairs of Read Data+ and Read Data- signal lines included in the ribbon cable 18".

In addition to the electronic and electro-mechanical differences described thus far between the enhanced-performance floppy diskette drive 22" and the floppy diskette drive 22 and 22', in one embodiment of the present invention a slight modification is also made to the spindle motor 38" of the floppy diskette drive 22" to increase its nominal rotation speed from 300 RPM to 600 RPM, and even to 900 RPM. The conventional floppy diskette drive 22 includes an electronic circuit for energizing the spindle motor 38. This conventional electronic circuit includes a resonant element, either a crystal or a piezoelectric device, for generating an approximately 4.0 MHz motor drive clock signal. Consequently, the nominal speed at which the spindle motor 38" spins the floppy diskette 34 may be increased from 300 RPM to 600 RPM merely by doubling the frequency of this resonant element from 4.0 MHz to 8.0 MHz, and by reducing to approximately one-half, i.e. from 0.47 to 0.22, the capacitance of a feed-back capacitor included in the motor drive electronic circuit. Analogously, the nominal speed at which the spindle motor 38" spins the floppy diskette 34 may be increased to 900 RPM by increasing the frequency of this resonant element to 12.0 MHz, and by reducing to one-third the capacitance of the feed-back capacitor.

Moreover, proper operation of the floppy diskette drive 22" at higher floppy diskette rotation speeds also requires increasing the force which the read/write heads 42" apply to the surfaces 44 of the floppy diskette 34. To operate the floppy diskette drive 22" at a floppy diskette rotation rate of 600, the force which the read/write heads 42" apply to the surfaces 44 is preferably increased from 30 grams to 45 grams. FIG. 7a illustrates pair of mechanical beams 182a and 182b included in the head positioning assembly 46 of a conventional floppy diskette drive 22 manufactured by Teac Corporation to which the read/write heads 42 are secured. The beams 182a and 182b are secured together by a pin 184 for rotation with respect to each other as indicated by curved arrows 186a and 186b. A coil spring 192, which encircles a portion of the pin 184, includes arms 194a and 194b which respectively extend along the beams 182a and 182b away from the pin 184 toward the read/write heads 42. Ends of the arms 194a and 194b furthest from the pin 184 are formed with hooks 196a and 196b which respectively engage the beams 182a and 182b to apply a force to the beams 182a and 182b that urges the read/write heads 42 toward each other. As illustrated in FIG. 7b, in the floppy diskette drive 22" the force applied to the beams 182a" and 182b" by the coil spring 192" is increased by disposing a 0.063 inch thick block 198 between the beam 182a" and the hook 196a" of the coil spring 192", and fastening the block 198 to the beam 182a" with Krazy Glue.RTM..

FIG. 8 is a block diagram illustrating in greater detail the FDC register emulation logic 76 depicted in FIG. 3. The FDC register emulation logic 76 includes an address decode logic 202 which is coupled by a host computer bus 204 through the socket 14 to the mother board bus 16. The address decode logic 202 responds to address and control signals present on the mother board bus 16 to transmit selection signals either to the ROM BIOS 92 via a ROM BIOS selection line 206, to a dual port static random access memory ("RAM") 212 via a RAM selection line 214, or to status registers 216 via a status register selection line 218.

Base address selection switches, not depicted in any of the FIGs., are included in the address decode logic 202 to permit selecting a base address for the floppy diskette controller 12" on the mother board bus 16 within the address space of the host microprocessor of either C000.sub.H, C400.sub.H, D000.sub.H, D400.sub.H, or D800.sub.H. The addresses for accessing the ROM BIOS 92, the dual port static RAM 212, and the status registers 216 are all related to the selected base address. FIG. 9 is a memory address space diagram which depicts the respective address spaces on the mother board bus 16 of the ROM BIOS 92, of the dual port static RAM 212, and of the status registers 216 in relationship to the selected base address. Addresses on the mother board bus 16 that lie between the base address and the base address plus 1FFF.sub.H access the ROM BIOS 92. Addresses on the mother board bus 16 that lie between the base address plus 2000.sub.H and the base address plus 3FEF.sub.H access the dual port static RAM 212. Addresses on the mother board bus 16 that lie between the base address plus 3FF0.sub.H and the base address plus 3FFF.sub.H access the status registers 216.

In addition to being coupled to the host computer bus 204, both the dual port static RAM 212 and the status registers 216 are also coupled via the FDC register emulation control bus 84 to the microcontroller 82. Consequently, both the dual port static RAM 212 and the status registers 216 may be accessed independently both by the computer program executed by the host microprocessor and by the computer program executed by the microcontroller 82. Accordingly, the computer program stored in the ROM BIOS 92 and the computer program executed by the microcontroller 82 exchange, via the dual port static RAM 212, data, and command and status information pertinent to storing data onto the floppy diskette 34 and retrieving recorded data from the floppy diskette 34. Alternatively, the computer program stored in the ROM BIOS 92, by writing up to four (4) bits of status information into a register located in the status registers 216 that may be read by the microcontroller 82, provides such status information to the computer program executed by the microcontroller 82. For example, when the interrupt 13 routine in the ROM BIOS 92 is invoked by a computer program executed by the host microprocessor to access the floppy diskette drive 22", the interrupt 13 routine sets a bit in the status registers 216 which indicates to the computer program executed by the microcontroller 82 that the enhanced-performance floppy diskette subsystem 70 is to operate in its high performance mode. If after the interrupt 13 routine completes its execution a computer program executed by the host microprocessor attempts to directly access the 76, the computer program executed by the microcontroller 82 detects such an event and immediately commences operating in a manner identical to that of a conventional floppy diskette subsystem 10. Analogously, the computer program executed in the microcontroller 82, by writing up to four (4) bits of status information into a register located in the status registers 216 that may be read by any computer program executed by the host microprocessor including the computer program stored in the ROM BIOS 92, provides such status information for use by the computer program stored in the ROM BIOS 92.

As described thus far, the enhanced-performance floppy diskette subsystem 70, by concurrently processing both surface 44 of the floppy diskette 34 and by spinning the floppy diskette 34 at a higher rotation speed, is capable of recording data onto the floppy diskette 34, and of reproducing recorded data from the floppy diskette 34 several times faster than that of the conventional floppy diskette subsystem 10. However, certain operating features of the computer program executed by the microcontroller 82 further increase the performance of the enhanced-performance floppy diskette subsystem 70 over that of the conventional floppy diskette subsystem 10. For example, when moving the read/write heads 42 from track to track across the surfaces 44 of the floppy diskette 34, the conventional floppy diskette subsystem 10 waits 15 milliseconds before attempting to record data onto or reproduce data from the floppy diskette 34. Conversely, in the enhanced-performance floppy diskette subsystem 70 the computer program continuously monitors status information present in the floppy diskette controller channels 24a" and 24b", and immediately begins reproducing data from or recording data onto the floppy diskette 34 upon observing that the floppy diskette controller channels 24a" and 24b" no longer report cyclic redundancy check ("CRC") errors in the data being received from the floppy diskette drive 22". By observing the absence of a CRC error in the data which the floppy diskette controller 12" receives from the floppy diskette drive 22", the computer program executed by the microcontroller 82 senses that the read/write heads 42" are properly positioned in relationship to the track on the surface 44 of the floppy diskette 34. In general, this permits accessing the floppy diskette 34 only 5 milliseconds after stepping from one track to the next track rather than waiting the conventional interval of 15 milliseconds.

Similarly, much of the time the spindle motor 38 of a floppy diskette drive 22 is unenergized and the floppy diskette 34 is motionless. The spindle motor 38 is energized only if a computer program executed by the host microprocessor attempts to reproduce data from or record data onto the floppy diskette 34. Upon energizing the spindle motor 38, the conventional floppy diskette subsystem 10 waits approximately 1.2 seconds before attempting to access the floppy diskette 34 for recording or reproducing data. Conversely, the enhanced-performance floppy diskette subsystem 70, again by continuously monitoring status information present in the floppy diskette controller channels 24a" and 24b", is able to begin accessing the floppy diskette 34 approximately 0.5 seconds after first energizing the spindle motor 38".

To permit the enhanced-performance floppy diskette subsystem 70 to swiftly provide data to the microprocessor in the host IBM PC XT or AT, or IBM PC clone computer system, immediately upon insertion of the floppy diskette 34 into the floppy diskette drive 22" in the absence of a request from the computer program executed by the host microprocessor to access the floppy diskette 34, the computer program executed by the microcontroller 82 reads the entire floppy diskette 34 and stores a copy of the data in the cache memory 72. Thus, if a computer program executed by the host microprocessor subsequently requests reproduction of data from the floppy diskette 34, the floppy diskette controller 12" immediately provides such data directly from the cache memory 72. Analogously, if the computer program executed by the host microprocessor requests recording data onto the floppy diskette 34, the computer program executed by the microcontroller 82 immediately stores all the data to be written onto the floppy diskette 34 into the cache memory 72. After such data has been first stored in the cache memory 72, the floppy diskette controller 12" then transfers the data from the cache memory 72 to the floppy diskette drive 22" for recording on the floppy diskette 34.

The preceding features by which the computer program senses when the floppy diskette controller 12 may safely access the floppy diskette 34 in combination both with the higher rotation speed of the floppy diskette 34 and with concurrently processing both surfaces 44 of the floppy diskette 34 permits the enhanced-performance floppy diskette subsystem 70 either to reproduce all the data contained on a 1.44 Mbyte floppy diskette 34 or completely record an entire 1.44 Mbyte floppy diskette 34 in approximately six seconds compared with 30 seconds for the conventional floppy diskette subsystem 10. However, inclusion in an alternative embodiment of the floppy diskette controller 12" of a synthesized generation variable frequency oscillator ("VFO") 222, as depicted in FIG. 3, permits the enhanced-performance floppy diskette subsystem 70 to achieve even greater performance. The VFO 222 is coupled to the microcontroller 82 by a VFO control bus 224 to permit transmission by the computer program executed by the microcontroller 82 of digital data to the VFO 222 which specifies the frequency of a clock signal produced by the VFO 222. In this alternative embodiment of the floppy diskette controller 12, the crystal(s) used in generating the clock signal required for operation of the floppy diskette controller channels 24a" and 24b" are omitted from the floppy diskette controller 12", and the VFO 222 supplies, via a VFO clock output signal line 226, a variable frequency clock signal to both the floppy diskette controller channels 24a" and 24b". Moreover, this same variable frequency clock signal is also supplied via the VFO clock output signal line 226 to a divider 228 which reduces the clock signal to one-sixth (1/6) of that transmitted by the VFO 222. The divider 228 transmits the divided clock signal, via a divided clock signal output line 232, to an alternative embodiment enhanced performance floppy diskette drive 22" via a motor clock signal line optionally included in the ribbon cable 18". Within the floppy diskette drive 22", the divided clock signal replaces the signal provided by the resonant element which is removed from the electronic circuit of the spindle motor 38" of the alternative embodiment floppy diskette drive 22".

With the output signal coupled in this way from the VFO 222 to the floppy diskette controller channels 24a" and 24b" and to the spindle motor 38", upon starting the spindle motor 38 control data transmitted from the microcontroller 82 to the VFO 222 causes the VFO 222 to progressively increase the frequency of the clock signal present on the status register selection line 218. The increasing frequency clock signal from the VFO 222 concurrently supplies the floppy diskette controller channels 24a" and 24b" and the spindle motor 38" with clock signals having a fixed frequency and phase relationship, i.e. one-sixth (6:1). In this way the clock signal produced by the VFO 222 regulates the operation of the floppy diskette controller channels 24a" and 24b" and of the spindle motor 38". Moreover, the VFO 222 by supplying the floppy diskette controller channels 24a" and 24b" with an increasing frequency clock signal automatically compensates the PLLs included in the floppy diskette controller channels 24a" and 24b" for the changing rate at which data signals are reproduced from the floppy diskette 34 as the spindle motor 38" accelerates the floppy diskette 34 up to its maximum speed. Because the PLLs included in the floppy diskette controller channels 24a" and 24b" and the data reproduced from the floppy diskette 34 are both kept in phase, the floppy diskette controller channels 24a" and 24b" operate over a speed range for the floppy diskette 34 which is limited primarily by the strength of the electrical signal generated in the read/write heads 42" due to rotation of the floppy diskette 34. Consequently, upon starting the spindle motor 38 this alternative embodiment of the floppy diskette controller 12" begins accessing the floppy diskette 34 in the alternative embodiment floppy diskette drive 22" sooner than a floppy diskette controller 12" which employs only a fixed frequency clock signal for the floppy diskette controller channels 24a" and 24b" and for the spindle motor 38".

It should be apparent that while including the ROM BIOS 92 in the floppy diskette controller 12" is helpful, a functional enhanced-performance floppy diskette subsystem 70 may be assembled which omits the ROM BIOS 92. In such an enhanced-performance floppy diskette subsystem 70, the computer program executed by the microcontroller 82 must periodically interrogate the FDC register emulation logic 76 to determine when a computer program executed by the host microprocessor attempts to access the floppy diskette drive 22". Analogously, whenever the computer program executed by the microcontroller 82 is occupied servicing the floppy diskette controller channels 24a" and 24b", that computer program must first store data into the FDC register emulation logic 76 emulating a busy condition for the floppy diskette controller channel 24 included in the floppy diskette controller 12. Correspondingly, when the computer program executed by the microcontroller 82 is no longer occupied servicing the floppy diskette controller channels 24a" and 24b", that computer program then must store data into the FDC register emulation logic 76 which clears the previously established busy condition.

The floppy diskette drive 22" preferably employs the solenoid 94 and the pin 96 which lock the diskette eject button 98 to prevent ejection of the floppy diskette 34 before all data present in the cache memory 72 has been recorded on the floppy diskette 34 because in the event of a power failure in the host computer the floppy diskette 34 may still be easily removed from the floppy diskette drive 22". However, an alternative technique is to replace the diskette eject button 98 and the solenoid 94 with an electrically energized mechanism for ejecting the floppy diskette 34 from the floppy diskette drive 22". For a floppy diskette drive 22" employing such an alternative technique for ejecting the floppy diskette 34, the computer program executed by the microcontroller 82 blocks energization of the mechanism for ejecting the floppy diskette 34 while data to be recorded on the floppy diskette 34 remains in the cache memory 72.

While the floppy diskette controller 12' has been disclosed as being assembled from several ICs, it is readily apparent that the floppy diskette controller channels 24a" and 24b", the FDC register emulation logic 76, the microcontroller 82, and the ROM BIOS 92 could be incorporated into an application specific integrated circuit ("ASIC"). Similarly, the VFO 222 and the divider 228 could also be incorporated into such an ASIC. Analogously, the two read/write channels 52a" and 52b" included in the floppy diskette drive 22" could also be incorporated into a single ASIC.

Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is purely illustrative and is not to be interpreted as limiting. Consequently, without departing from the spirit and scope of the invention, various alterations, modifications, and/or alternative applications of the invention will, no doubt, be suggested to those skilled in the art after having read the preceding disclosure. Accordingly, it is intended that the following claims be interpreted as encompassing all alterations, modifications, or alternative applications as fall within the true spirit and scope of the invention. ##SPC1##

Claims

What is claimed is:

1. A floppy diskette subsystem adapted for inclusion in a host computer system and for recording digital data along tracks formed on both side surfaces of a thin, circularly-shaped, double-sided floppy diskette, said floppy diskette subsystem comprising: an enhanced-performance floppy diskette drive adapted for receiving and securing a floppy diskette so the floppy diskette is rotatable about a rotation axis disposed normal to the floppy diskette, said floppy diskette drive including: a diskette drive motor which upon being energized rotates a floppy diskette secured in the floppy diskette drive about the rotation axis at a nominal rotation speed; two read/write heads that are respectively adapted for recording and reproducing digital data from a single side surface of a floppy diskette; a diskette head positioning assembly to which the read/write heads are mechanically secured, the diskette head positioning assembly being adapted for moving each of the read/write heads laterally across a side surface of a floppy diskette in a direction that is normal to the rotation axis of a floppy diskette; and two separate and independent read/write ("R/W") channels which are respectively electronically coupled to one of the read/write heads, each of the R/W channels exchanging electrical signals with the read/write head to which the R/W channel is coupled for recording digital data on a side surface of a floppy diskette, and for reproducing previously recorded digital data from that same side surface of a floppy diskette; and an enhanced-performance floppy diskette controller adapted for exchanging digital command, status, and data signals with a bus of a host computer system, said floppy diskette controller also being adapted for exchanging digital command, status, control, and data signals with the diskette head positioning assembly, with the diskette drive motor, and with the R/W channels of said floppy diskette drive, said floppy diskette controller including: floppy diskette controller register emulation logic adapted for being coupled to a bus of a host computer system for exchanging digital command, status, and data signals therewith, the floppy diskette controller register emulation logic receiving and transmitting digital command, status, and data signals which permit the floppy diskette controller to mimic a conventional floppy diskette subsystem; a cache memory coupled to the floppy diskette controller register emulation logic for exchanging digital data with the floppy diskette controller register emulation logic, and for storing exchanged digital data; a microcontroller coupled both to the floppy diskette controller register emulation logic and to the cache memory for exchanging digital data between the floppy diskette controller register emulation logic and the cache memory so the floppy diskette controller mimics operation of a conventional floppy diskette subsystem; and two separate and independent floppy disk drive controller channels respectively coupled between the cache memory and one of the R/W channels included in said enhanced-performance floppy diskette drive, each floppy disk drive controller channel concurrently exchanging digital data with the cache memory and exchanging digital command, status, control, and data signals with the R/W channel of said floppy diskette drive that is coupled to the floppy disk drive controller channel.

2. The floppy diskette subsystem of claim 1 wherein said floppy diskette controller pre-fetches digital data from a floppy diskette, that is present in said floppy diskette drive and upon which such digital data has been previously recorded, before a computer program executed by a host microprocessor included in a host computer system attempts to access such digital data, said floppy diskette controller storing such pre-fetched digital data into said cache memory.

3. The floppy diskette subsystem of claim 1 wherein if said floppy diskette controller receives digital data from a host computer system for recording onto a floppy diskette that is present in said floppy diskette drive, said floppy diskette controller first stores such digital data into said cache memory before transmitting such digital data to the R/W channels of said floppy diskette drive for recording onto the floppy diskette.

4. The floppy diskette subsystem of claim 3 wherein the floppy diskette cannot be removed from said floppy diskette drive if any digital data to be recorded onto the floppy diskette remains in said cache memory.

5. The floppy diskette subsystem of claim 4 wherein upon energization of a solenoid included in the floppy diskette drive a pin extends from said solenoid to engage and lock a diskette eject button included in the floppy diskette drive to prevent removal the floppy diskette from said floppy diskette drive while any digital data to be recorded onto the floppy diskette remains in said cache memory.

6. The floppy diskette subsystem of claim 1 wherein the floppy diskette controller further comprises a variable frequency oscillator for producing a clock signal having a frequency which is specified by digital data that said variable frequency oscillator receives from said microcontroller, the clock signal produced by said variable frequency oscillator regulating operation of the floppy disk drive controller channels, and the rotation speed of the diskette drive motor.

7. The floppy diskette subsystem of claim 1 wherein digital data is recorded on a floppy diskette that is present in said floppy diskette drive while said diskette drive motor accelerates the floppy diskette up to the nominal rotation speed.

8. The floppy diskette subsystem of claim 7 wherein the nominal rotation speed of the floppy diskette exceeds 550 revolutions per minute ("RPM").

9. The floppy diskette subsystem of claim 8 wherein the nominal rotation speed of the floppy diskette exceeds 850 RPM.

10. The floppy diskette subsystem of claim 1 wherein digital data is reproduced from a floppy diskette, that is present in said floppy diskette drive and upon which such digital data has been previously recorded, while said diskette drive motor accelerates the floppy diskette up to the nominal rotation speed.

11. The floppy diskette subsystem of claim 10 wherein the nominal rotation speed of the floppy diskette exceeds 550 RPM.

12. The floppy diskette subsystem of claim 10 wherein the nominal rotation speed of the floppy diskette exceeds 850 RPM.

13. The floppy diskette subsystem of claim 1 wherein the floppy diskette drive transmits an interrupt signal to said floppy diskette controller immediately upon ejection of a floppy diskette from the floppy diskette drive.

14. The floppy diskette subsystem of claim 1 wherein the nominal rotation speed of the floppy diskette exceeds 550 RPM.

15. The floppy diskette subsystem of claim 1 wherein the nominal rotation speed of the floppy diskette exceeds 850 RPM.

16. The floppy diskette subsystem of claim 1 wherein upon said diskette head positioning assembly moving said read/write heads from a first track to a second track laterally across side surfaces of a floppy diskette that is present in said floppy diskette drive and upon which digital data has been previously recorded, said floppy diskette subsystem begins reproducing digital data immediately upon said floppy diskette controller sensing that said read/write heads are properly positioned in relationship to the second track.

17. The floppy diskette subsystem of claim 1 wherein upon said diskette head positioning assembly moving said read/write heads from a first track to a second track laterally across side surfaces of a floppy diskette that is present in said floppy diskette drive and upon which digital data has been previously recorded, said floppy diskette subsystem begins recording digital data immediately upon said floppy diskette controller sensing that said read/write heads are properly positioned in relationship to the second track.

18. The floppy diskette subsystem of claim 1 wherein if said floppy diskette controller detects accesses to a floppy diskette that is present in said floppy diskette drive by a computer program executed by a host microprocessor included in a host computer system which requires conventional performance from said floppy diskette subsystem for proper execution of the computer program, said floppy diskette subsystem reduces performance to that of a conventional floppy diskette subsystem.

19. The floppy diskette subsystem of claim 18 wherein said floppy diskette controller further comprises a basic input-output system ("BIOS") for detecting if a computer program executed by the host microprocessor requires conventional performance from said floppy diskette subsystem.

20. An enhanced-performance floppy diskette controller adapted for inclusion in a host computer system and for exchanging digital command, status, and data signals with a bus of the host computer system, said floppy diskette controller also being adapted for use with an enhanced-performance floppy diskette drive to form a floppy diskette subsystem, the enhanced-performance floppy diskette drive being adapted for receiving and securing a thin, circularly-shaped, double-sided floppy diskette so the floppy diskette is rotatable about a rotation axis disposed normal to the floppy diskette, and for recording digital data along tracks formed on two side surfaces of the floppy diskette, the floppy diskette drive including: a diskette drive motor which upon being energized rotates a floppy diskette secured in the floppy diskette drive about the rotation axis at a nominal rotation speed; two read/write heads that are respectively adapted for recording and reproducing digital data from a single side surface of a floppy diskette; a diskette head positioning assembly to which the read/write heads are mechanically secured, the diskette head positioning assembly being adapted for moving each of the read/write heads laterally across a side surface of a floppy diskette in a direction that is normal to the rotation axis of a floppy diskette; and two separate and independent R/W channels which are respectively electronically coupled to one of the read/write heads, each of the R/W channels exchanging electrical signals with the read/write head to which the R/W channel is coupled for recording digital data on a side surface of a floppy diskette, and for reproducing previously recorded digital data from that same side surface of a floppy diskette; and said enhanced-performance floppy diskette controller being adapted for exchanging digital command, status, control, and data signals with the diskette head positioning assembly, with the diskette drive motor, and with the R/W channels of the floppy diskette drive, said floppy diskette controller comprising: floppy diskette controller register emulation logic adapted for being coupled to a bus of a host computer system for exchanging digital command, status, and data signals therewith, the floppy diskette controller register emulation logic receiving and transmitting digital command, status, and data signals which permit the floppy diskette controller to mimic a conventional floppy diskette subsystem; a cache memory coupled to the floppy diskette controller register emulation logic for exchanging digital data with the floppy diskette controller register emulation logic, and for storing exchanged digital data; a microcontroller coupled both to the floppy diskette controller register emulation logic and to the cache memory for exchanging digital data between the floppy diskette controller register emulation logic and the cache memory so the floppy diskette controller mimics operation of a conventional floppy diskette subsystem; and two separate and independent floppy disk drive controller channels respectively coupled between the cache memory and one of the R/W channels included in the enhanced-performance floppy diskette drive, each floppy disk drive controller channel concurrently exchanging digital data with the cache memory and exchanging digital command, status, control, and data signals with the R/W channel of the floppy diskette drive that is coupled to the floppy disk drive controller channel.

21. The floppy diskette controller of claim 20 wherein said floppy diskette controller pre-fetches digital data from a floppy diskette that is present in the floppy diskette drive before a computer program executed by a host microprocessor included in a host computer system attempts to access such digital data, said floppy diskette controller storing such pre-fetched digital data into said cache memory.

22. The floppy diskette controller of claim 20 wherein if said floppy diskette controller receives digital data from a host computer system for recording onto a floppy diskette that is present in the floppy diskette drive, said floppy diskette controller first stores such digital data into said cache memory before transmitting such digital data to the R/W channels of the floppy diskette drive for recording onto the floppy diskette.

23. The floppy diskette controller of claim 20 wherein the floppy diskette controller further comprises a variable frequency oscillator for producing a clock signal having a frequency which is specified by digital data that said variable frequency oscillator receives from said microcontroller, the clock signal produced by said variable frequency oscillator regulating operation of the floppy disk drive controller channels, and the rotation speed of the diskette drive motor in the floppy diskette drive.

24. The floppy diskette controller of claim 20 wherein said floppy diskette controller transmits digital data to the floppy diskette drive for recording on a floppy diskette that is present in the floppy diskette drive while the diskette drive motor of the floppy diskette drive accelerates the floppy diskette up to the nominal rotation speed.

25. The floppy diskette controller of claim 20 wherein said floppy diskette controller stores digital data into said cache memory which has been reproduced from a floppy diskette that is present in the floppy diskette drive while the diskette drive motor of the floppy diskette drive accelerates the floppy diskette up to the nominal rotation speed.

26. The floppy diskette controller of claim 20 wherein upon the diskette head positioning assembly of the floppy diskette drive moving said read/write heads of the floppy diskette drive from a first track to a second track laterally across side surfaces of a floppy diskette that is present in the floppy diskette drive and upon which digital data has been previously recorded, the floppy diskette controller begins storing into said cache memory digital data reproduced from the floppy diskette present in the floppy diskette drive immediately upon said floppy diskette controller sensing that the read/write heads are properly positioned in relationship to the second track.

27. The floppy diskette controller of claim 20 wherein upon the diskette head positioning assembly of the floppy diskette drive moving said read/write heads of the floppy diskette drive from a first track to a second track laterally across side surfaces of a floppy diskette that is present in the floppy diskette drive and upon which digital data has been previously recorded, the floppy diskette controller begins transmitting digital data from said cache memory to the R/W channels of the floppy diskette drive for recording onto the floppy diskette immediately upon said floppy diskette controller sensing that the read/write heads are properly positioned in relationship to the second track.

28. The floppy diskette controller of claim 20 wherein if said floppy diskette controller detects accesses to a floppy diskette that is present in the floppy diskette drive by a computer program executed by a host microprocessor included in a host computer system which requires conventional performance from the floppy diskette subsystem for proper execution of the computer program, said floppy diskette controller reduces the performance of the floppy diskette subsystem to that of a conventional floppy diskette subsystem.

29. The floppy diskette controller of claim 28 wherein said floppy diskette controller further comprises a BIOS for detecting if a computer program executed by the host microprocessor requires conventional performance from the floppy diskette subsystem.

30. An enhanced-performance floppy diskette drive adapted for use with an enhanced-performance floppy diskette controller to form a floppy diskette subsystem adapted for inclusion in a host computer system, the enhanced-performance floppy diskette controller being adapted for exchanging digital command, status, and data signals with a bus of a host computer system, the floppy diskette controller also being adapted for exchanging digital command, status, control, and data signals with said floppy diskette drive, the floppy diskette controller including: floppy diskette controller register emulation logic adapted for being coupled to a bus of a host computer system for exchanging digital command, status, and data signals therewith, the floppy diskette controller register emulation logic receiving and transmitting digital command, status, and data signals which permit the floppy diskette controller to mimic a conventional floppy diskette subsystem; a cache memory coupled to the floppy diskette controller register emulation logic for exchanging digital data with the floppy diskette controller register emulation logic, and for storing exchanged digital data; a microcontroller coupled both to the floppy diskette controller register emulation logic and to the cache memory for exchanging digital data between the floppy diskette controller register emulation logic and the cache memory so the floppy diskette controller mimics operation of a conventional floppy diskette subsystem; and two separate and independent floppy disk drive controller channels respectively coupled to the cache memory and also being adapted to be coupled to said enhanced performance floppy diskette drive, each floppy disk drive controller channel concurrently exchanging digital data with the cache memory and being adapted for exchanging digital command, status, control, and data signals with said floppy diskette drive; and said floppy diskette drive being adapted for receiving and securing a thin, circularly-shaped, double-sided floppy diskette so the floppy diskette is rotatable about a rotation axis disposed normal to the floppy diskette, and for recording digital data along tracks formed on both side surfaces of the floppy diskette, said floppy diskette drive comprising: a diskette drive motor which upon being energized rotates a floppy diskette secured in the floppy diskette drive about the rotation axis; two read/write heads that are respectively adapted for recording and reproducing digital data from a single side surface of a floppy diskette; a diskette head positioning assembly to which the read/write heads are mechanically secured, the diskette head positioning assembly being adapted for moving each of the read/write heads laterally across a side surface of a floppy diskette in a direction that is normal to the rotation axis of a floppy diskette; two separate and independent R/W channels which are respectively electronically coupled to one of the read/write heads, each R/W channel concurrently exchanging digital command, status, control, and data signals with one of the floppy disk drive controller channels included in the floppy diskette controller to which the R/W channel is coupled, each of the R/W channels also concurrently exchanging electrical signals with the read/write head to which the R/W channel is coupled for recording digital data on a side surface of a floppy diskette, and for reproducing previously recorded digital data from that same side surface of a floppy diskette; and floppy diskette ejection means which upon being activated ejects from said floppy diskette drive a floppy diskette which is present in said floppy diskette drive, said floppy diskette drive transmitting an interrupt signal to said floppy diskette controller immediately upon ejection of a floppy diskette from the floppy diskette drive.

31. The floppy diskette drive of claim 30 wherein the floppy diskette cannot be removed from said floppy diskette drive if any digital data to be recorded onto the floppy diskette remains in the cache memory of the floppy diskette controller.

32. The floppy diskette drive of claim 31 wherein upon energization of a solenoid included in the floppy diskette drive a pin extends from said solenoid to engage and lock a diskette eject button included in the floppy diskette drive to prevent removal the floppy diskette from said floppy diskette drive while any digital data to be recorded onto the floppy diskette remains in the cache memory of the floppy diskette controller.

33. The floppy diskette drive of claim 30 wherein said diskette drive motor responds to a variable frequency clock signal produced in the floppy diskette controller for regulating the rotation speed of the diskette drive motor.

34. The floppy diskette drive of claim 30 wherein digital data is recorded on a floppy diskette that is present in said floppy diskette drive while said diskette drive motor accelerates the floppy diskette up to the nominal rotation speed.

35. The floppy diskette drive of claim 34 wherein the nominal rotation speed of the floppy diskette exceeds 550 RPM.

36. The floppy diskette drive of claim 34 wherein the nominal rotation speed of the floppy diskette exceeds 850 RPM.

37. The floppy diskette drive of claim 30 wherein digital data is reproduced from a floppy diskette, that is present in said floppy diskette drive and upon which such digital data has been previously recorded, while said diskette drive motor accelerates the floppy diskette up to the nominal rotation speed.

38. The floppy diskette drive of claim 37 wherein the nominal rotation speed of the floppy diskette exceeds 550 RPM.

39. The floppy diskette drive of claim 37 wherein the nominal rotation speed of the floppy diskette exceeds 850 RPM.

40. The floppy diskette drive of claim 30 wherein the nominal rotation speed of the floppy diskette exceeds 550 RPM.

41. The floppy diskette drive of claim 30 wherein the nominal rotation speed of the floppy diskette exceeds 850 RPM.

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Abstract

Description