Method of Fabricating a Resistor in an Integrated Circuit

The present invention relates to a method of fabricating multi-valued resistors in an integrated circuit.

Multi-valued linear resistors are required in integrated circuits like static random access memories (SRAMs) or programmable read only memories (PROMs). FIG. 1 shows a cross sectional view of a conventional resistor in an integrated circuit. A polysilicon layer 14 is doped and patterned over a field oxide 12 and a silicon substrate 10. Two ion implants with different amounts of dopants are performed on the polysilicon layer 14 to provide a resistive portion 18 having a desired resistance, and two heavily-doped end regions 16 as contact electrodes. Separate photoengraving and masking steps are therefore required for each ion implant. Moreover, in order to fabricate multi-valued linear resistors on an integrated circuit, multiple photoengraving and masking steps are required to provide different resistance in the resistive portion of each resistor.

U.S. Pat. No. 5,352,923 entitled "Trench Resistors for Integrated Circuits" to Boyd et. al. discloses a method for forming multi-valued linear resistors for an integrated circuit using a single mask. FIGS. 2A to 2B show cross sectional views illustrating two steps of a process for forming a resistor according to the '923 patent. Referring to FIG. 2A, a conformal oxide layer 22 lines sidewalls and a bottom of a trench formed in a substrate 20. Next, a conformal undoped polysilicon layer 24 is formed on the oxide layer 22. A heavily-doped thick polysilicon layer 26 is deposited to fill the undoped- polysilicon-lined trench.

Subsequently, referring to FIG. 2B, a chemical-mechanical polishing method is applied to etch back portions of the heavily-doped thick polysilicon layer 26, the undoped polysilicon layer 24, and the oxide layer 22 until a silicon nitride layer 28 is reached. However, in the etching back process mentioned above, it is practically difficult to control the polishing due to the different materials encountered to achieve the desired structure of FIG. 2B. Furthermore, the polishing process incurs substantial damage to the surface of the structure shown in FIG. 2B, which further requires some corrective measures.

Another way to achieve the structure of FIG. 2B is the use of a conventional etch method. Unfortunately, this type of etch method usually results in a structure as shown in FIG. 2C, where the surface of the structure is not flat due to the different etching rate for the heavily doped thick polysilicon layer 26 and the undoped polysilicon layer 24.

A method of fabricating a resistor in an integrated circuit is disclosed. The method comprises the steps of forming a pad oxide layer on the substrate; forming a silicon oxide layer on said pad oxide layer; forming a silicon nitride layer on said silicon oxide layer; forming a photoresist layer on the silicon nitride layer, said photoresist layer defining a trench area on said silicon nitride layer; removing portions of said pad oxide layer, said silicon oxide layer, said silicon nitride layer and the substrate using said photoresist layer as a mask, thereby forming a trench in the substrate; conformally forming an isolation oxide layer on the silicon nitride layer, the sidewalls of the trench, and a bottom of the trench; conformally forming an undoped polysilicon layer on said isolation oxide layer; forming a doped polysilicon layer over said undoped polysilicon layer, thereby filling the trench; etching hack said doped polysilicon layer using etchant SF.sub.6, said undoped polysilicon layer being an etch stop; etching hack said doped polysilicon layer and said undoped polysilicon layer using etchant CF.sub.x, thereby forming a plug comprising said doped polysilicon layer and said undoped polysilicon layer, said plug having a flat surface, and the etchant CF.sub.x having the same etch rate to both said undoped polysilicon layer and said doped polysilicon layer; and annealing said undoped polysilicon and said doped polysilicon layer, thereby diffusing dopants of said doped polysilicon layer into said undoped polysilicon layer.

FIG. 1 shows a cross sectional view of a conventional resistor in an integrated circuit;

FIGS. 2A to 2C show cross sectional views illustrating two steps of a prior art process for forming a resistor in an integrated circuit;

FIGS. 3 to 9 show cross-sectional views illustrative of various stages in the fabrication of a resistor in an integrated circuit in accordance with one embodiment of the present invention;

FIGS. 10A and 10B show the plan views of the surface of two resistor structures in accordance with the present invention; and

FIGS. 11 to 17 show cross-sectional views illustrative of various stages in the fabrication of a resistor in an integrated circuit in accordance with another embodiment of the present invention.

Referring to FIG. 3, a pad oxide layer 32 is conventionally formed on a substrate 30. This pad oxide layer 32 is formed using a thermal oxidation process at a temperature of about 900.degree..about.1100.degree. C. The pad oxide layer 32 can be alternatively formed by a chemical vapor deposition method, typically to a thickness of about 200 to 600 angstroms. A composite layer 35 is then subsequently formed on the pad oxide layer 32, and the thickness of the composite layer 35 is about 800.about.3000 angstroms.

This composite layer 35 can be provided by a single silicon oxide layer 33 and a coating of a silicon nitride layer 34. In this embodiment, a CVD process is used to form the silicon oxide layer 33 to a thickness of about 500.about.2000 angstroms, and a CVD process is used to deposit the silicon nitride layer 34 to a thickness of about 300.about.1000 angstroms. The pad oxide layer 32, the silicon oxide layer 33, and the silicon nitride layer 34 mentioned above together serve as a masking layer 36 in forming a trench, which will be described below. It is appreciated that the masking layer 36 may include only a single silicon oxide layer 33 or only a composite layer 35.

Next, conventional photolithography techniques are then used to define a trench area on the silicon nitride layer 34 using a photoresist 38. The composite layer 35, the pad oxide layer 32, and the substrate 30 are then anistropically etched using the composite layer 35 as an etching mask, forming a deep, steep-sided trench 40 in the substrate 30 as shown in FIG. 4. In this embodiment, a MERIE process with a HBr/CL.sub.2 etchant is used to form this trench 40.

Referring to FIG. 5, a conformal and undoped oxide layer 42 is deposited to line the silicon nitride layer 34, the sidewalls of the trench 40, and the bottom of the trench 40. In this embodiment, the oxide layer 42 is preferably formed using a conventional chemical vapor deposition process, to a thickness of about 500.about.2000 angstroms. The oxide layer 42 acts as an isolation layer between the substrate 30 and a resistive portion inside the trench 40. Next, a conformal and undoped polysilicon layer 44 is deposited on the oxide layer 42, lining the trench 40 in the oxide-lined substrate 30. In this embodiment, a low pressure chemical vapor deposition process is used to form the undoped polysilicon layer 44 by reacting silane (SiH.sub.4) and nitrogen (N.sub.2) at about 575.degree. C. The thickness of the undoped polysilicon layer 44 can be between 500 to 2000 angstroms. Next, a heavily-doped polysilicon layer 46 is subsequently deposited over the undoped polysilicon layer 44, thereby filling the trench 40. In this embodiment, the heavily-doped polysilicon layer 46 is formed by a conventional method of polysilicon chemical vapor deposition with in situ doping of phosphorus (P) or arsenic (As) dopants at a concentration of about 5E20.about.1E21 atoms/cm.sup.2 by reacting PH.sub.3, silane, and nitrogen at about 575.degree. C.

The structure of FIG. 5 is then subject to a first etch back process using the undoped polysilicon layer 44 as an etching stop, resulting in the structure shown in FIG. 6. In this embodiment, a reactive ion etch method with etchant SF.sub.6 is preferably used owing to the large selectivity of the heavily-doped polysilicon layer 46 to the undoped polysilicon layer 44 for the etchant SF.sub.6.

Next, a second etch back process is performed to etch portions of the undoped polysilicon layer 44 and the heavily-doped polysilicon layer 46 to form a flat plug 45, which includes the heavily-doped polysilicon layer 46 and the undoped polysilicon layer 44. The etchant used in this second etch back process is specifically chosen so that the heavily-doped polysilicon layer 46 and the undoped polysilicon layer 44 have the same etch rate. In this embodiment, a reactive ion etch method with etchant CF.sub.x (for example CF.sub.4) is preferably used. It is noted that two etch back steps are required instead of using CF.sub.x in a single step because CF.sub.x is not a very fast etchant of polysilicon. Therefore, it would take too long to etch away the relative thick doped polysilicon 46 (FIG. 5) if only one etch step with etchant CF.sub.x is used.

The structure of FIG. 7 is thereafter subjected to an annealing process to diffuse dopants from the doped polysilicon layer 46 into the undoped polysilicon layer 44, resulting in the resistive portion 48 as shown in FIG. 8. In this embodiment, annealing is carried out at about 800.degree..about.1000.degree. C.

The resistivity of the resistive portion 48 is related to the mount of dopants in the doped polysilicon layer 46 (FIG. 7) and to the width of the plug 45 (FIG. 7). The wider the plug 45, the lower the resistance of the resistive portion 48. Thus, the process allows for simultaneously forming resistors of different values, using only one mask to define the trenches of different dimensions. The requirements for multiple photoengraving and implantation steps to conventionally form multi-valued resistors on an integrated circuit as described in connection with FIG. 1 is avoided. The non-flat surface of the conventional plug in connection with FIG. 2C is also avoided.

Finally, portions of the oxide layer 42, the composite layer 35, and the pad oxide layer 32 are removed, for example, using conventional plasma or wet etching process, resulting in the resistive portion 48 surrounded by the isolation oxide layer 42 as shown in FIG. 9. A plan view of the surface of the resistor structure is shown in FIG. 10A, where the resistor includes an elongated resistive portion 48, and two conductive contact portions 50. FIGS. 3 to 9 show cross sectional views in the along axis 52.

FIG. 10B shows the plan view of another resistor, which has lower resistance than the resistor of FIG. 10A due to its wider lateral dimension. The resistor includes an elongated resistive portion 148, and two conductive contact portions 150. Cross sectional views in the axis 152 are shown in FIG. 11 to 17, and will be briefly described below.

Referring to FIG. 11, a pad oxide layer 132 is conventionally formed on a substrate 130 using a thermal oxidation process or a chemical vapor deposition method, typically to a thickness of about 200 to 600 angstroms. A composite layer 135 is subsequently formed on the pad oxide layer 132. This composite layer 135 can be provided by a single silicon oxide layer 133 and a coating of a silicon nitride layer 134. The pad oxide layer 132, the silicon oxide layer 133, and the silicon nitride layer 134 mentioned above together serve as a masking layer 136 in forming a trench, which will be described below. It is appreciated that the masking layer 136 may include only a single silicon oxide layer 133 or only a composite layer 135.

Next, conventional photolithography techniques are then used to define a trench area on the silicon nitride layer 134 using a photoresist 138. The composite layer 135, the pad oxide layer 132, and the substrate 130 are then anistropically etched using the composite layer 135 as an etch mask, forming a deep, steep-sided trench 140 in the substrate 130 as shown in FIG. 12.

Referring to FIG. 13, a conformal and undoped oxide layer 142 is deposited to line the silicon nitride layer 134, the sidewalls of the trench 140, and the bottom of the trench 140. The oxide layer 142 acts as an isolation layer between the substrate 130 and a resistive portion inside the trench 140. Next, a conformal and undoped polysilicon layer 144 is deposited on the oxide layer 142, lining the trench 140 in the oxide-lined substrate 130. A heavily-doped polysilicon layer 146 is subsequently deposited over the undoped polysilicon layer 144, thereby filling the trench 140.

The structure of FIG. 13 is then subject to a first etch back process using the undoped polysilicon layer 144 as an etching stop, resulting in the structure shown in FIG. 14. In this embodiment, a reactive ion etch method with etchant SF.sub.6 is preferably used owing to the large selectivity of the heavily-doped polysilicon layer 146 to the undoped polysilicon layer 144 for the etchant SF.sub.6.

Next, a second etch back process is performed to etch portions of the undoped polysilicon layer 144 and the heavily-doped polysilicon layer 146 to form a flat plug 145, which includes the heavily-doped polysilicon layer 146 and the undoped polysilicon layer 144. The etchant used in this second etch back process is specifically chosen so that the heavily-doped polysilicon layer 146 and the undoped polysilicon layer 144 have the same etch rate. In this embodiment, a reactive ion etch method with etchant CF.sub.x (for example CF.sub.4) is preferably used.

The structure of FIG. 15 is thereafter subject to an annealing process to diffuse dopants from the doped polysilicon layer 146 into the undoped polysilicon layer 144, resulting in the resistive portion 148 as shown in FIG. 16. The resistivity of the resistive portion 148 is related to the mount of dopants in the doped polysilicon layer 146 (FIG. 15) and to the width of the plug 145 (FIG. 15). The wider the plug 145, the lower the resistance of the resistive portion 148. Thus, the process allows for the simultaneous forming of resistors of different values, using only one mask to define the trenches of different dimensions. The requirements for multiple photoengraving and implantation steps to conventionally form multi-valued resistors on an integrated circuit as described in connection with FIG. 1 is avoided. The non-flat surface of the conventional plug in connection with FIG. 2C is also avoided.

Finally, portions of the oxide layer 142, the composite layer 135, and the pad oxide layer 132 are removed, for example, using a conventional MERIE process, resulting in the resistive portion 148 surrounded by the isolation oxide layer 142 as shown in FIG. 17.

Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from the spirit which is intended to be limited solely by the appended claims.