Method for Forming a Semiconductor Device Having a Shallow Junction and a Low Sheet Resistance

1. Field of the Invention

The present invention relates to a method for forming a semiconductor device having a shallow junction and a low sheet resistance, and more particularly to a method for fabricating a MOSFET capable of preventing a junction breakdown and an increase in the junction leakage current.

2. Description of the Prior Art

Generally, a junction in a MOS transistor is commonly formed between a silicon substrate and an active region such as source/drain regions.

In a conventional MOSFET, a titanium silicide layer is commonly used to form a device having a low sheet resistance. After implanting impurity ions into the silicon substrate, the junction is formed therein by the first thermal treatment. Next, a titanium layer is formed on the ion implantation area and the titanium silicide layer is formed by the second thermal treatment.

However, impurity ions, which are doped into the substrate, are re-diffused into the titanium silicide layer at the time of processing the second thermal treatment, and then impurity concentration at the interface of titanium silicide layer and silicon substrate is extremely reduced, resulting in schottky junction. Thus, there are some problems in the decrease in the junction breakdown voltage and the increase in the junction leakage current.

Furthermore, since the junction depth becomes shallower with the higher integration of the semiconductor devices, the sheet resistance increases making it more difficult to develop high speed devices.

An object of the present invention is to provide a method for forming semiconductor devices having simultaneously a shallow junction and a low sheet resistance without the consumption of the silicon layer.

In accordance with an aspect of the present invention, there is provided a method for forming a junction of a low sheet resistance on a silicon substrate, comprising the steps of forming an amorphous silicon layer on said silicon substrate; implanting impurity ions into said amorphous silicon layer; implanting transition metal ions into said amorphous silicon layer; and thermally treating said amorphous silicon layer and silicon substrate such that said transition metal ions diffuse to the surface of said silicon substrate and said impurity ions diffuse into said silicon substrate.

Other objects and aspects of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings, in which:

FIGS. 1A to 1D are cross-sectional views illustrating a method for forming a MOSFET in accordance with an embodiment of the present invention.

Referring to FIGS. 1A to 1D, an embodiment of the present invention will be described below in detail.

First, as shown in FIG. 1A, there are a gate oxide layer 10, a gate electrode 11, and a sidewall oxide layer 12 to form a universal MOSFET on a silicon substrate 1, and they are well-known to a person having ordinary skill in the art to which the subject matter pertains. Before forming the sidewall oxide layer 12, impurity ions can be implanted into the silicon substrate 1 to form the LDD (Lightly Doped Drain) structure, using the sidewall oxide layer 12 and an insulating layer (not shown) on the gate electrode 11 as a implanting barrier layer. An amorphous silicon layer 13 is deposited in a thickness of "T" i.e. 200-300 .ANG., on the exposed silicon substrate 1 in which the source/drain regions are formed.

Next, as shown in FIG. 1B, boron ions 14 are positioned by implanting BF.sub.2 ions into the amorphous silicon layer 13. In the case where the boron ions 14 are implanted into the silicon substrate 1, the channeling of the boron ions 14 is severely generated because of small size of boron ions. Accordingly, it is very difficult to form the shallow junction when the boron ions 14 are implanted into the silicon substrate 1. Referring again to FIG. 1A, the amorphous silicon layer 13 has an effect on the shallow junction, by preventing the boron ions 14 from penetrating into the silicon substrate 1 by means of the channeling thereof. Also, the energy of the boron ions 14 to-be-accelerated must be controlled lest they should penetrate into the interface of the silicon substrate 1 and the amorphous silicon layer 13. In a preferred embodiment, the projected range of the boron ions 14 is set at half the thickness of the amorphous silicon layer 13, i.e., the projected depth of the boron ions 14 is 0.5T.

As shown in FIG. 1C, in order to form a thin silicide layer without consumption of the silicon substrate 1, tungsten ions 15 must be implanted into the amorphous silicon layer 13 with a smaller energy than that of the boron ions 14. Of course, ions of transition metal, such as titanium or cobalt, can be substituted for the tungsten ions 15. Particularly, it is necessary to control the energy for the tungsten ions 15 so as not to be implanted into the silicon substrate 1. In the preferred embodiment, the projected range of the tungsten ions 15 is set at half the thickness of the amorphous silicon layer 13.

Finally, after implanting the boron and tungsten ions 15 into the amorphous silicon layer 13, as shown in FIG. 1D, the wafer is treated with a rapid thermal process such that the tungsten and boron ions 14 and 15 in the amorphous silicon layer 13 diffuse toward the silicon substrate 1. Since the diffusion coefficient of the boron ions 14 is higher than that of the tungsten ions 15, the source/drain regions 16 are formed in the silicon substrate 1, and the tungsten silicide layers 17 are formed on the source/drain regions 16.

As apparent from the above description, the present invention provides a superior effect capable of improving the speed of the devices by forming the shallow junction having a low sheet resistance.

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.