Method and System for Interleaving and Deinterleaving SDH Frames

1. Field of the Invention

The field of the invention is that of methods for interleaving and deinterleaving SDH (Synchronous Digital Hierarchy) frames and the invention is more particularly concerned with a method of this kind that makes parity control bytes of such frames transparent to the interleaving operation. The invention also concerns an interleaving and deinterleaving system using a method of this kind.

2. Description of the Prior Art

FIG. 1 shows a basic frame transmitted in an SDH network. This STM-1 frame transports a VC-4 virtual container and contains 2 430 bytes divided into nine rows each of 270 bytes. It comprises three areas:

a section overhead (SOH) area;

an area PT including pointers;

a payload area essentially containing the data to be transmitted.

STM-1 frames provide a transmission bit rate of 155 Mbit/s.

The section overhead SOH is contained in bytes 1 through 9 of rows 1 through 3 and 5 through 9. The pointer area PT occupies bytes 1 through 9 of the fourth row of the STM-1 frame. The payload area occupies bytes 9 through 270 of rows 1 through 9. All these bytes are read from left to right and from top to bottom.

The function of the pointers is to indicate the position of the various tributary signals in the payload area to enable frame alignment problems to be solved without using buffer memory.

FIG. 2 shows the structure of the SOH. The SOH is made up of a regenerator section overhead (RSOH) and a multiplexing section overhead (MSOH).

The RSOH is accessible at all repeaters and comprises:

frame alignment bytes A1 (11110110) and A2 (00101000) constituting a frame alignment word;

an identification byte C1 for identifying the position of a demultiplexed signal (extraction of one byte in N) in the STM-N frame (high bit rate frame at N times 155 Mbit/s);

an 8th bit interleaving parity calculation byte B1 used for error location within a regeneration section;

bytes E1 and F1 respectively reserved for an order wire and a user channel;

bytes D1 through D3 which form a 192 kbit/s data channel.

The MSOH is accessible at the terminations of a multiplexing section and comprises:

bytes B2.1, B2.2, B2.3 used to measure the quality of the multiplexing section;

bytes K1 and K2 used for administration of automatic section protection;

bytes D4 through D12 forming a 576 kbit/s data channel;

reserved bytes Z1 and Z2;

a byte E2 forming a 64 kbit/s order wire.

Bytes marked with an X are reserved for international use and bytes B1, B2.1, B2.2 and B2.3 of a given frame i constitute parity control bytes of the frame i-1 preceding frame i. To be more precise, a parity control byte in frame i is the sum of the bytes in frame i-1, including the corresponding parity control byte in frame i-1.

FIG. 3 shows the multiplexing structure of an STM-1 frame in accordance with CCITT Recommendation G.709. This multiplexing structure includes a plurality of plesiochronous tributaries at different bit rates each linked to a C-i container constituting envelopes of digital signals transported. These containers are connected to virtual containers VC-i each made up of a container and an overhead. The virtual containers VC-i cooperate with tributary units TU-i comprising a lower order virtual container and its associated pointer. The TUG-i are tributary unit groups which represent a virtual structure of the frame enabling multiplexing of TU-i of different sizes. The AU-i are administrative units which are multiplexed to constitute an STM-1 frame. N interleaved STM-1 frames constitute an STM-N frame which is transmitted to a receiver over a microwave link or a physical line (cable, optical fiber, etc).

When digital information is transmitted using error correcting codes, as in the SDH system, errors that cannot be corrected sometimes cause the formation of error packets with lengths exceeding a few tens of bits. Accordingly, an error packet can form in the pointer area, preventing access to the tributary whose position in the frame is indicated by the pointer.

Japanese patent application n.degree. 5-344089 in the name of NEC describes a method of interleaving the pointer of the VC-4 virtual container. This pointer comprises three bytes H1, H2, H3 divided between a group of nine consecutive bytes at the start of the fourth row of the STM-1 frame. The objective of interleaving as proposed in this patent application is to dilute the pointer bits. This interleaving is associated with an error correcting code generating extra-bits. This method has a number of drawbacks:

it uses for the extra-bits SOH locations that are not standardized at present but which may be standardized in the future; future standardization action could therefore render this method inapplicable;

it does not allow for any pointers that may be present in the payload area. These pointers are used, among other things, to indicate the position of the VC-31 and VC-32 virtual containers in the AU-4 and AU-31 administrative units. They are disposed in columns of bytes so that there is only one byte per row. To be more precise, these three bytes are consecutive and written into columns 11, 12, 13 and 14 of the STM-1 frame, starting from the first row, to transport four VC-31 virtual containers and also consecutive and written into columns 13, 14 and 15 of the STM-1 frame from the first row to transport three VC-32 virtual containers.

Furthermore, in the case of multiframe transport, the pointers occupy only one byte per frame.

One object of the invention is to provide an SDH frame interleaving method and system (implemented at a transmitter) and an SDH frame deinterleaving method and system (implemented at a receiver) that do not suffer from the aforementioned drawbacks.

To be more precise, one object of the invention is to interleave an SDH frame in such a way that no loss of pointer occurs if an error packet having a length less than a predefined length Lmax is produced at the location of that pointer. In accordance with a predefined specification, it must be possible to reconstitute the pointer at the receiver even if an error packet having a length of less than Lmax=80 bits is produced.

Another object of the invention is to achieve this interleaving without corrupting the value of the parity control byte B1 or the value of the 24-tuplet B2.1, B2.2, B2.3.

The above objects, and others that emerge below, are achieved by a method of interleaving and deinterleaving STM-1 and STM-N SDH frame pointers transmitted between a transmitter and a receiver, each frame comprising three areas:

a section overhead area;

a pointer area;

a payload area including the data to be transmitted,

in which method, at said transmitter, said interleaving consists in interleaving the bits of said pointer area and those of said payload area according to an interleaving law retaining the position modulo 24 in the interleaved bits, said interleaving producing an interleaved frame transmitted to said receiver at which said interleaved frame is deinterleaved using a law that is the reciprocal of said interleaving law.

In this way the bits of all the pointers in an STM-1 or STM-N frame are interleaved without corrupting the value of the parity control bytes.

In one advantageous embodiment of the method of the invention, the interleaving is associated with compacting of said pointer area in accordance with a compacting law by modifying the position of at least two bytes of said pointer area so that after interleaving and compacting each pair of bits of said pointer is separated by at least the length of an error packet that the transmission can withstand without any pointer errors, said interleaving being associated with decompacting in accordance with a law that is the reciprocal of the compacting law.

This allows for a specific disposition of the pointer bytes in the pointer area.

Note that a pointer error occurs if more than one bit is invalid. If a single bit of the pointer received is invalid, the majority coding imposed by the SDH standard enables its correct value to be found.

The method of the invention advantageously includes a step of correcting the 24-tuplet B2 after compacting and interleaving and after decompacting and deinterleaving to remedy corruption of that byte due to compacting.

The invention also consists in an SDH frame pointer interleaving and deinterleaving system using the above method and a corresponding transmitter and receiver.

Other features and advantages of the invention will emerge from a reading of the following description of one advantageous embodiment of the invention given by way of non-limiting illustrative example only with reference to the appended drawings.

FIG. 1 shows a basic frame transmitted in an SDH network and transporting a VC-4 virtual container.

FIG. 2 shows the structure of the SOH of the basic frame.

FIG. 3 shows the multiplexing structure of an STM-1 frame in accordance with CCITT Recommendation G.709.

FIG. 4 shows an STM-1 frame in which the areas interleaved by the method of the invention are emphasized.

FIGS. 5 and 6 are tables showing the natural order of the bits to be interleaved when placed in tables of 24 columns and 87 and 90 rows, respectively, for specific interleaving of the 4th row of the STM-1 frame.

FIG. 7 shows the order in which the table from FIG. 5 is read in one preferred embodiment of the method of the invention.

FIGS. 8 and 9 show parts of tables resulting from interleaving in accordance with the invention.

FIGS. 10A through 12B show various arrangements of the pointer area PT.

FIG. 13 is a block schematic of part of a transmitter of the invention.

FIG. 14 is a block schematic of part of a receiver of the invention.

FIGS. 1 through 3 have already been described in relation to the prior art.

In FIG. 4, the area of an STM-1 frame that is interleaved by the invention is shaded. This area comprises rows 1 through 3 and 5 through 9 of the payload area and all of row 4 of the STM-1 frame. Interleaving all these bits necessarily enables interleaving those of all pointers in this frame.

The problem arising from interleaving is that it must not corrupt the parity control bytes B1 and B2.1, B2.2 and B2.3. Accordingly, interleaving must respect the position of the bits modulo 24 in the interleaving frame such that the 24-tuplet B2.1, B2.2 and B2.3 is not corrupted. Respecting the position of the bits modulo 24 necessarily respects the position of the bits modulo 8 and so interleaving that does not corrupt this 24-tuplet does not corrupt the byte B1 either.

In a preferred embodiment of the method of the invention, and as shown in FIG. 4, interleaving is effected row by row. In this way, the 2 088 bits of each of rows 1 through 3 and 5 through 9 are interleaved independently and likewise the 2 160 bits of row 4.

The tables in FIGS. 5 and 6 show the natural order of the bits to be interleaved when placed in tables of 24 columns by 87 and 90 rows, respectively. The FIG. 5 table contains 2 088 bits and the FIG. 6 table contains 2 160 bits.

After placing the bits of each row to be interleaved in these tables, interleaving in accordance with the invention can simply entail reading the tables in the manner shown in FIG. 7.

FIG. 7 shows the order of reading the FIG. 5 table. This reading is diagonal, i.e. the first bit read is that of the 1st row in the 1st column, the second bit read is that of the 2nd row in the 2nd column, and so on up to the 24th row in the 24th column. Reading then continues from the 26th row in the 1st column, rather than the 25th row, to respect a gap of 24 bits between bits 576 (24.times.24) and 577. On reaching the 87th row (to read the 84th bit), reading continues from the 1st row of the 13th column.

FIG. 8 shows part of the table resulting from such interleaving. It shows eight of 24 columns and 40 of 87 rows.

This table is then read row by row to place the corresponding bits into a frame constituting the interleaved frame.

Note that the location of the bits modulo 24 is respected: for example, column 1 of the FIG. 8 table includes all bits at position 1 modulo 24 up to bit 1 489. These bits also appear in column 1 of the FIG. 5 table.

A table corresponding to that of FIG. 6 is read in the same order as that of FIG. 7, except that the table has 90 rows instead of 87, because of the presence of the 72 bits of the pointer PT. FIG. 9 shows part of the table resulting from such interleaving. It shows eight of 24 columns and 40 of 90 rows. This table is then read row by row to place the corresponding bits in the interleaved frame. As previously, column 1 of the FIG. 9 table includes all the bits at position 1 modulo 24 up to bit 2 160. These bits also appear in column 1 of the FIG. 6 table.

As the bits are interleaved with their position modulo 24 in the frame preserved, the parity control bytes are not corrupted.

The embodiment of the invention described above ensures that 83 bits (86 bits in the case of the 4th row) in the interleaved block are at least 25 bits apart in the deinterleaved block. This complies with a specification requiring that an error packet 80 bits long (Lmax) shall not prevent the recognition of a pointer.

Special processing can also be applied to ensure dispersion of the bits of pointers of the administrative unit AU-4 and the administrative units AU-32: the latter appear in the 4th row of the STM-1 frame, as shown in FIGS. 10A and 10B.

FIG. 10A shows the structure of the pointer PT of the administrative unit AU-4. It comprises nine bytes of which only the bytes H1, H2 and H3 form the pointer. Referring to FIG. 9, if the interleaving method described above is used, the bits of H1, H2 and H3 are assembled in groups of three by the interleaving operation. As one object of the invention is to disperse these bits, it is necessary before (or after) interleaving to carry out an operation on these bytes such that the bits are not grouped. The same problem arises with the pointer PT of the administrative unit AU-32 shown in FIG. 10B. The present invention therefore compacts the pointer area by modifying the position of at least two bytes of the pointer area so that after interleaving and compacting each pair of bits of the pointer is separated by at least Lmax, where Lmax is the length of an error packet that the transmission can withstand without any pointer errors. One example of compacting is described with reference to FIGS. 11A and 11B.

FIG. 11A shows the PT area of an STM-1 frame, the nine bytes of this part of the 4th row being labeled 4.1 through 4.9.

The invention compacts these bytes so that the interleaving operation disperses their bits in the interleaved frame. In a preferred embodiment of the invention this area has the structure shown in FIG. 11B after the compacting operation. Bytes 4.1, 4.5 and 4.9 remain at their previous location, bytes 4.2 and 4.4, 4.3 and 4.7, 4.6 and 4.8 being interchanged.

The result of this compacting of the PT areas in FIGS. 10A and 10B is shown in FIGS. 12A and 12B, respectively. The effect of subsequent interleaving will be to disperse the pointer bits, which is the required outcome.

Another problem then arises, however: the compacting operation modifies the positions of the bits at location modulo 24 with the result that the 24-tuplet B2 is corrupted. To be more precise, the byte B2.1 normally relates to bytes 4.1, 4.4 and 4.7 but after compacting these bytes are respectively 4.1, 4.2 and 4.3. Likewise, B2.2 and B2.4 normally relate to bytes 4.2, 4.5, 4.8 and 4.3, 4.6, 4.9, respectively, whereas the compacting operation replaces them with 4.4, 4.5, 4.6 and 4.7, 4.8, 4.9, respectively. This is why the method of the invention proposes to correct this 24-tuplet after the compacting operation by replacing the bytes B2.1, B2.2 and B2.3 with the bytes B2.1', B2.2' and B2.3', respectively, these bytes having the value:

B2.1'=B2.1-4.2-4.3+4.4+4.7

B2.2'=B2.2-4.4-4.6+4.2+4.8

B2.3'=B2.3-4.7-4.8+4.3+4.6

The corrections are written in logical form:

B2.1'=B2.1.sym.4.2.sym.4.3.sym.4.4.sym.4.7

B2.2'=B2.2.sym.4.4.sym.4.2.sym.4.6.sym.4.8

B2.3'=B2.3.sym.4.7.sym.4.3.sym.4.8.sym.4.6

where .sym. is the exclusive-OR operator.

Correcting the 24-tuplet B2 before it is transmitted means that the parity control computation method implemented in the receiver can remain as defined by the standard.

The present invention also concerns a system for interleaving and deinterleaving STM-1 or STM-N SDH frame pointers transmitted between a transmitter and a receiver.

FIG. 13 is a block schematic of part of a transmitter implementing the method of the invention.

The processor means shown in FIG. 13 include an input E for a frame to be interleaved and a frame alignment word extractor and synchronization device 135. A demultiplexed stream of STM-1 or STM-4 frames at 155/4 Mbit/s can be applied to the input E, for example. A compactor module 130 receives the signal E and compacts the bytes of the area PT. Compacting usually employs a compacting law whereby the position of at least two bytes of the pointer area is modified so that after interleaving and compacting each pair of bits of the pointer is separated by at least Lmax where Lmax is the length of an error packet that the transmission can withstand without any pointer errors. This compacting can advantageously be effected in the manner shown in FIG. 11B.

An interleaver module 131 receives the output signal from the compactor module 130 and interleaves bits of the pointer area and bits of the payload area in accordance with an interleaving law preserving the position modulo 24 of the interleaved bits, in accordance with the invention. Because of the compacting, and to avoid modifying the rule for calculating the parity control bytes, means 132, 133, 134 are provided for correcting the 24-tuplet B2 of the interleaved frame supplied by the module 131. These means include a module 133 for extracting the pointer in the area PT, a module 134 for calculating the corrected 24-tuplet B2 and a module 132 in which the 24-tuplet B2 present in the interleaved signal is replaced by the corrected 24-tuplet. The output signal S of the module 132 is the signal transmitted to the receiver of FIG. 14.

The transmission system can be a repeatered microwave link, for example, or a cable or optical fiber.

The FIG. 14 receiver includes means 140 for deinterleaving the signal SR which deinterleaves the interleaved frame received according to a law that is the reciprocal of the interleaving law. The object of this deinterleaving is therefore to regroup the bits that were dispersed by the interleaving. The deinterleaved frame is applied to a decompactor module 141 which decompacts the pointer area using a law that is the reciprocal of the compacting law.

Note that the compacting law described above also constitutes a decompacting law. Accordingly, the module 141 can be identical to the module 130.

The receiver also includes means for correcting the 24-tuplet B2 of the deinterleaved frame from the module 141. These means comprise a module 143 for extracting the pointer in the area PT of the deinterleaved frame (constituting the output signal S), a module 144 for calculating the corrected 24-tuplet B2 and a module 142 in which the 24-tuplet B2 in the deinterleaved signal is replaced by the corrected 24-tuplet. The receiver further includes a frame alignment word extractor and synchronization device 145.

The interleaving operation can evidently precede the compacting operation and the decompacting operation can evidently precede the deinterleaving operation. In practise, these operations are simultaneous.

The above description is not limiting in respect of the number of rows involved in the interleaving operations: it is possible to interleave two or more rows rather than treating only one row at a time, for example. Likewise, it is possible to interleave some of the data present in the section overhead SOH to the exclusion of the bytes B1 and B2.2, B2.2 and B2.3. However, interleaving bits of the RSOH then entails deinterleaving at each repeater between the transmitter and the receiver (terminations).