Method of Defining a Line Width

This invention relates, in general, to a method of fabricating a semiconductor component, and more particularly, to a method of defining a line width.

With the ever increasing demand for smaller and more compact semiconductor components, designers are shrinking the size of gate lengths, line widths, and the like. However, it is difficult to manufacture a precise line width for submicron geometries because conventional photolithographic techniques are not sufficient. Alternative methods for forming a submicron line width include using phase shifting technology, electron beam lithography, ion beam lithography, and X-ray lithography. While phase shifting technology can define 0.35 micron line widths, it is also expensive and complicated. Electron beam lithography, ion beam lithography, and X-ray lithography are capable of defining 0.1 micron line widths, but these non-standard techniques are even more expensive and complicated than phase shifting technology.

Another existing method for defining small line widths includes etching an opening having a larger line width and forming spacers along sidewalls of the opening to reduce the size of the opening and to reduce the size of the final line width. However, this technique is still limited by the photolithographic capability that defines the original opening.

Accordingly, a need exists for a low cost method of defining a line width, especially when the line width is less than one micron. The method should be manufacturable and should not significantly increase the cycle time of manufacturing a semiconductor component.

FIGS. 1-5 illustrate cross-sectional views of a method of defining a line width in accordance with the present invention;

FIGS. 6-7 portray cross-sectional views of an alternative method of defining a line width in accordance with the present invention;

FIGS. 8-13 represent cross-sectional views of another alternative method of defining a line width in accordance with the present invention; and

FIGS. 14-16 depict cross-sectional views of yet another alternative method of defining a line width in accordance with the present invention.

Turning to the figures for a detailed description, FIGS. 1-5 illustrate cross-sectional views of a method of defining a line width in accordance with the present invention. In particular, FIG. 1 depicts a portion of a semiconductor device or a semiconductor component 10 having a substrate 11. While substrate 11 can comprise a myriad of suitable materials over which or in which a submicron feature is formed, substrate 11 preferably comprises a semiconductor material such as, for example, single crystal silicon or gallium arsenide. Accordingly, substrate 11 is hereinafter referred to as semiconductor substrate 11. Although not depicted in FIG. 1, semiconductor substrate 11 can support a plurality of semiconductor devices or components, which are coupled together to form an integrated circuit. Preferably, semiconductor component 10 is a gallium arsenide metal-semiconductor field effect transistor (MESFET).

In a preferred embodiment, an etch stop layer 12 is provided over semiconductor substrate 11. Although etch stop layer 12 is not required, etch stop layer 12 helps to protect semiconductor substrate 11 during the formation of a spacer 14 as described below. Etch stop layer 12 preferably comprises aluminum nitride. However, other suitable etch stop materials can also be used for etch stop layer 12. In a preferred embodiment, the aluminum nitride of etch stop layer 12 is deposited at room temperature by sputtering an aluminum target in a nitrogen ambient.

As portrayed in FIG. 1, a temporary structure 13 is formed over etch stop layer 12 and semiconductor substrate 11. Temporary structure 13 comprises a dielectric material including, but not limited to, nitride or oxide. In a preferred embodiment, temporary structure 13 comprises silicon oxide. As an example of how temporary structure 13 is formed, a silicon oxide layer is deposited over etch stop layer 12 in a plasma enhanced chemical vapor deposition (PECVD) process using a reaction of silane and oxygen gases at a temperature between approximately 200.degree. and 500.degree. degrees Celsius (.degree.C.). Subsequently, a patterned photoresist layer (not shown) is used as an etch mask while creating or etching an edge 55 of temporary structure 13 out of the deposited silicon oxide layer. While an anisotropic or isotropic etch can be used, temporary structure 13 is preferably etched in a reactive ion etch (RIE) chamber using a fluorine based plasma. Temporary structure 13 does not need to have submicron geometries, and therefore, its formation is not limited to using expensive submicron patterning techniques.

Spacer 14 is subsequently formed along or adjacent to edge 55 of temporary structure 13 by first disposing a dielectric layer over temporary structure 13 and etch stop layer 12 and then etching the dielectric layer. No photoresist pattern is required to form spacer 14. The dielectric layer of spacer 14 can be comprised of, for example, silicon oxide but is preferably comprised of silicon nitride. In a preferred embodiment, the silicon nitride is conformally deposited in a PECVD process using a reaction of silane and ammonia at 200.degree.-500.degree. C. and is anisotropically etched in a RIE process using a fluorine based plasma.

The position of edge 55 defines the location of spacer 14. Because spacer 14 is used to define the position of a gate electrode as described below and because the position of a gate electrode is an important consideration for a semiconductor transistor, the position of edge 55 of temporary structure 13 should be precisely located. Accordingly, an anisotropic etch is preferably used to etch edge 55 of temporary structure 13 as described above.

Spacer 14 has a width 17 as indicated in FIG. 1. Width 17 is mainly determined by three factors: the height of temporary structure 13, the thickness of the silicon nitride that is deposited to form spacer 14, and the amount of silicon nitride that is etched away to form spacer 14. While these three factors may be changed independently of one another, the formation of a taller temporary structure 13, the deposition of a thicker silicon nitride, or the etching away of less silicon nitride can produce a larger width 17 for spacer 14. Similarly, the formation of a shorter temporary structure 13, the deposition of a thinner silicon nitride layer, or the etching away of more silicon nitride can produce a smaller width 17 for spacer 14. Accordingly, width 17 can be as large as a few microns and can also be in the submicron range.

Continuing with FIG. 2, another partial cross-sectional view of semiconductor component 10 illustrates a removal of temporary structure 13 and a deposition of an electrically insulating layer 15 over spacer 14, etch stop layer 12, and semiconductor substrate 11. Temporary structure 13 is removed using an etch process that does not substantially etch spacer 14. In a preferred embodiment, where temporary structure 13 comprises silicon oxide and where spacer 14 comprises silicon nitride, a hydrofluoric (HF) acid is used to selectively remove temporary structure 13 while leaving spacer 14 over etch stop layer 12. Alternatively, when temporary structure 13 comprises silicon nitride and when spacer 14 comprises silicon oxide, a fluorine based plasma which selectively etches silicon nitride versus silicon oxide can also be used to remove temporary structure 13. In another alternative embodiment, temporary structure 13 is not removed at this step of the process, and electrically insulating layer 15 is deposited over temporary structure 13.

Electrically insulating layer 15 preferably comprises a dielectric layer including, but not limited, to aluminum nitride, silicon nitride, or silicon oxide and is herein referred to as dielectric layer 15. The composition of dielectric layer 15 should be different from that of spacer 14 such that spacer 14 can be selectively etched over dielectric layer 15. Accordingly, when spacer 14 comprises silicon nitride, dielectric layer 15 preferably comprises silicon oxide and can be disposed over semiconductor substrate 11 in a technique similar to that of the previously described preferred embodiment of temporary structure 13 in FIG. 1.

Referring now to FIG. 3, a partial cross-sectional view of semiconductor component 10 illustrates dielectric layer 15 after being planarized to expose a portion of spacer 14. In a preferred embodiment, a chemical-mechanical polish is used to planarize dielectric layer 15 and removes a portion of spacer 14 as depicted in FIG. 3. However, other planarizing techniques known in the art can also be used to planarize dielectric layer 15. These techniques include, but are not limited to, a resist etch back process. Alternatively, a patterned photoresist process can be used along with an etch process to expose a portion of spacer 14.

Next, spacer 14 is removed as illustrated in FIG. 4. Spacer 14 is etched away without substantially etching dielectric layer 15 such that opening 19 has a width substantially equal to width 17 of spacer 14. Spacer 14 can be etched by an isotropic or anisotropic etchant but is preferably etched in an RIE chamber having a fluorine based plasma. Because spacer 14 is not a permanent part of semiconductor component 10, spacer 14 is also referred to as temporary structure 50.

Etch stop layer 12 prevents the echant, which removes spacer 14, from etching or damaging semiconductor substrate 11 located beneath spacer 14. After the removal of spacer 14, the exposed portion of etch stop layer 12 in opening 19 is also removed as portrayed in FIG. 4. When etch stop layer 12 is aluminum nitride, etch stop layer 12 is preferably etched with ammonium hydroxide (NH.sub.4 OH) or phosphoric acid. If spacer 14 and temporary structure 13 can be etched without damaging semiconductor substrate 11, etch stop layer 12 is not required in accordance with the present invention.

In an alternative embodiment, etch stop layer 12 is a dielectric layer that is not removed from opening 19. In this alternative embodiment, etch stop layer 12 is used as a gate insulator in an insulated gate field effect transistor such as, for example, a metal-oxide field effect transistor (MOSFET).

Continuing with FIG. 5, an electrically conductive layer 16 is disposed over dielectric layer 15 and is disposed in opening 19. Where semiconductor substrate comprises gallium arsenide, electrically conductive layer 16 is preferably comprised of a refractory metal such as, for example, tungsten nitride, titanium tungsten nitride, or the like. Electrically conductive layer 16 is used to form a gate electrode 18 and is herein referred to as gate layer 16. Gate layer 16 is preferably etched in a RIE etch using a fluorine based plasma to form gate electrode 18. Gate electrode 18 has a gate length substantially equal to width 17 of spacer 14. Width 17, hereinafter referred to as gate length 17, is preferably less than 1.0 micron but can, in the alternative, be greater than 1.0 micron.

FIGS. 6 and 7 portray cross-sectional views of an alternative method of defining a line width in accordance with the present invention. A partial view of a semiconductor component 20 in FIG. 6 depicts a substrate 21 supporting an etch stop layer 22, a temporary structure 23, a spacer 24, a dielectric layer 25, and a patterned photoresist layer 26. FIG. 6 can be compared to FIG. 2, which was described earlier. Accordingly, semiconductor component 20 of FIG. 6 is similar to semiconductor component 10 of FIG. 2. Likewise, substrate 21, etch stop layer 22, temporary structure 23, spacer 24, and dielectric layer 25 of FIG. 6 are similar to semiconductor substrate 11, etch stop layer 12, temporary structure 13, spacer 14, and dielectric layer 15, respectively, of FIG. 2.

Etch stop layer 22 of FIG. 6 is deposited in several stages. First, a layer of etch stop material is deposited prior to the formation of temporary structure 23 such that it is located between temporary structure 23 and substrate 21. After the formation of temporary structure 23, another layer of the etch stop material is deposited over temporary structure 23. Then, following the formation of spacer 24, the deposition of etch stop layer 22 is completed after a third layer of the etch stop material is deposited over spacer 24.

Patterned photoresist layer 26 is used to mask a portion of dielectric layer 25 during a planarization process as portrayed in FIG. 7. In the illustrated embodiment, patterned photoresist layer 26 is a reverse image of the photoresist layer used to form temporary structure 23. Therefore, in this illustrated embodiment, an extra photolithographic plate does not need to be manufactured.

In a preferred embodiment, an isotropic etchant such as, for example, a fluorine plasma is used to planarize or etch dielectric layer 25. Accordingly, dielectric layer 25 will be undercut to expose a portion of a temporary structure 51. Temporary structure 51 of FIG. 7 is similar to temporary structure 50 of FIG. 3 and has a width 27. In a preferred embodiment, temporary structure 51 comprises spacer 24 and portions 52 and 53 of etch stop layer 22.

Temporary structure 51 is removed to form an opening in which a gate layer can be deposited. The portion of etch stop layer 22 that covers spacer 24 is removed to expose spacer 24 using etch techniques that are similar to those previously described above for etching etch stop layer 12 in FIG. 4. The technique used to remove spacer 24 and to deposit the gate layer in FIG. 7 can be similar to the techniques previously described in FIGS. 4 and 5 to remove temporary structure 50. The opening created by removing temporary structure 51 of FIG. 7 has a width substantially equal to width 27 of temporary structure 51, and the gate electrode formed in the opening will have a gate length substantially equal to width 27 of temporary structure 51.

As known in the art, spacer 24 will be formed along all of the vertical sidewalls of temporary structure 23. If a gate electrode is only desired along certain portions of temporary structure 23, then only certain portions of temporary structure 51 are removed prior to the deposition of the gate layer. Accordingly, patterned photoresist layer 26 can alternatively be defined such that etching dielectric layer 25 exposes only certain portions of temporary structure 51. Therefore, when removing temporary structure 51, only the exposed portions of temporary structure 51 will be removed.

Turning to FIGS. 8-13, cross-sectional views of another alternative method of defining a line width are illustrated in accordance with the present invention. A partial cross-sectional view of a semiconductor component 30 in FIG. 8 depicts a substrate 31, etch stop layers 32 and 34, a dielectric layer 33, a temporary structure 35, and a spacer 36. Semiconductor component 30 of FIG. 8 is similar to semiconductor component 10 of FIG. 1, and etch stop layers 32 and 34 of FIG. 8 are both similar to etch stop layer 12 of FIG. 1. Analogously, substrate 31, temporary structure 35, and spacer 36 of FIG. 8 are preferably similar to semiconductor substrate 11, temporary structure 13, and spacer 14, respectively, of FIG. 1. In a preferred embodiment, dielectric layer 33 is similar in composition to temporary structure 35, and both dielectric layer 33 and temporary structure 35 are different in composition to spacer 36.

As an example of how to fabricate semiconductor component 30 as portrayed in FIG. 8, etch stop layer 32 is first deposited over substrate 31. Then, dielectric layer 33 is provided over etch stop layer 32, and etch stop layer 34 is disposed over dielectric layer 33. Temporary structure 35 is formed over etch stop layer 34, and spacer 36 is formed adjacent to temporary structure 35. Spacer 36 has a width 39.

Subsequently, as depicted in FIG. 9, temporary structure 35 is removed, and etch stop layer 34 is etched using spacer 36 as an etch mask. Etch stop layer 34 now has width 39 of spacer 36. In an alternative embodiment, the present invention can omit the use of etch stop layer 34 if temporary structure 35 and spacer 36 can be formed without substantially etching dielectric layer 33 and if spacer 36 can be used as an etch mask for dielectric layer 33 as explained below.

Continuing with FIG. 10, spacer 36 is removed, and etch stop layer 34 is used as an etch mask 56 to etch dielectric layer 33 to create a temporary structure 28. Therefore, in effect, width 39 of spacer 36 has been transferred into temporary structure 28. Although not depicted in FIG. 10, etch mask 56 can be comprised of both spacer 36 and etch stop layer 34 in an alternative embodiment. In either case, spacer 36 is preferably removed prior to the deposition of a dielectric layer 37 as represented in FIG. 11. Dielectric layer 37 can be similar in composition to spacer 36 and is similar in function to dielectric layer 15 of FIG. 2.

As discussed above, temporary structure 28 comprises the etched dielectric layer 33 and the etched etch stop layer 34. However, in an alternative embodiment, etch stop layer 34 can be removed prior to the deposition of dielectric layer 37, in which case temporary structure 28 would be comprised of dielectric layer 33.

Dielectric layer 37 is planarized to expose a portion of temporary structure 28, which is subsequently removed to create an opening 54 over substrate 31 and in dielectric layer 37 as depicted in FIG. 12. Opening 54 has width 39 of spacer 36 and temporary structure 28. After removal of the exposed portion of etch stop layer 32 in opening 54, an electrically conductive layer 38 is deposited over dielectric layer 37 and fills opening 54 as portrayed in FIG. 13. Electrically conductive layer 38 is similar to gate layer 16 of FIG. 5 and is etched to form gate electrode 29, which has a gate length substantially equal to width 39.

Referring now to the subsequent figures, FIGS. 14-16 depict cross-sectional views of yet another alternative method of defining a line width in accordance with the present invention. In FIG. 14, a partial cross-sectional view of a semiconductor component 40 depicts a substrate 41, which is similar to semiconductor substrate 11 of FIG. 1, an etch stop layer 43, which is similar to etch stop layer 12 of FIG. 1, a temporary structure 44, which is similar to temporary structure 13 of FIG. 1, and a spacer 45, which is similar to spacer 14 of FIG. 1. Electrically conductive layer or gate layer 42 is similar to in composition to both gate layer 16 of FIG. 1 and electrically conductive layer 38 of FIG. 13. Accordingly, semiconductor component 40 is similar to semiconductor component 10 of FIG. 1.

Semiconductor component 40 of FIG. 14 is formed by first depositing gate layer 42 over substrate 41, and then depositing etch stop layer 43 over gate layer 42. Afterwards, temporary structure 44 is formed over etch stop layer 43, and then spacer 45 is formed adjacent to temporary structure 44 and over etch stop layer 43. Spacer 45 has a width 47 as illustrated in FIG. 14.

Next, in FIG. 15, temporary structure 44 is removed, and then etch stop layer 43 is etched using spacer 45 as an etch mask. Subsequently, gate layer 42 is etched while using etch stop layer 43 and spacer 45 as an etch mask 57. Although not depicted in FIG. 15, spacer 45 can be removed after etching etch stop layer 43, and etch mask 57 can consist solely of etch stop layer 43 in an alternative embodiment. However, in either embodiment, width 47 of spacer 45 is used to define a gate length for gate layer 42.

Finally, in FIG. 16, etch stop layer 43 and spacer 45 are removed, and semiconductor component 40 is left with a gate electrode 46 comprised of gate layer 42. Width 47 of spacer 45 defines the gate length for gate electrode 46. Therefore, width 47 is also referred to as gate length 47 or line width 47.

Similar to previous embodiments of the present invention, etch stop layer 43 is not required to form semiconductor component 40. Etch stop layer 43 can be omitted from the illustrated embodiment of FIGS. 14-16 if the formation of temporary structure 44 and spacer 45 does not significantly affect gate layer 42 and if spacer 45 can be used as an etch mask to form gate electrode 46.

In an alternative embodiment, the processes described in FIGS. 14-16 are used to fabricate an insulated gate field effect transistor such as, for example, a MOSFET. In this alternative embodiment, a gate insulator layer (not shown) is provided between gate layer 42 and substrate 41.

While the invention has been particularly shown and described with reference to preferred embodiments, it will be understood by those skilled in the art that changes in form and detail may be made without departing from the spirit and scope of the invention. For instance, the spacers, temporary structures, dielectric layers, and etch stops of the various embodiments in FIGS. 1-16 can be formed of materials other than dielectrics as long as the etch selectivity requirements mentioned previously are satisfied. These other materials include, for example, polysilicon. Moreover, features including, but not limited to, spacers 14, 36, and 45, temporary structures 13, 28, 35, and 44, and etch stop layers 34, and 43 can even be comprised of electrically conducting materials. Furthermore, while the present invention has been described to fabricate gate electrodes, it is understood that a similar method can be used to define line widths of other structures such as interconnect lines, vias, or the like.

Therefore, in accordance with the present invention, it is apparent there has been provided an improved method of defining a line width that overcomes the disadvantages of the prior art, especially when the line width is less than one micron. The present invention eliminates the expensive and complicated procedures of phase shifting, and X-ray, electron beam, and ion beam lithography. As described above, the present invention is manufacturable, cost-efficient, and does not significantly increase the cycle time for manufacturing a semiconductor component.