Semiconductor Integrated Circuit Applicable to Data Read Circuit From Memory

1. A semiconductor integrated circuit for reading data in memory cells comprising: a memory cell matrix having a dynamic random access memory (DRAM) cells arranged in a plurality of rows and a plurality of columns along two directions which are at right angles to each other; a plurality of word lines each arranged at one row of said plurality of rows of said cell matrix; a plurality of bit line pairs which have a pair of bit lines arranged at each column of said plurality of bit line pairs of said cell matrix, and each pair of which has a first and a second bit line for reading said data; a plurality of bit line differential amplifier circuits, each of which is provided for each pair of the plurality of said bit line pairs and amplifies a potential difference between said first and second bit lines; a pair of data lines having a first data line coupled to the plurality of said first bit lines and a second data line coupled to the plurality of said second bit lines; a first switch circuit, provided between the plurality of said bit line differential amplifier circuits of each pair of the plurality of pairs of said bit lines and said pair of data lines, for turning on and off a charge transmission from each of said bit line pairs to said data line pair; a data line differential amplifier circuit for amplifying the potential difference between said data line pair; and an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor which has a source electrode directly connected to one of said first and second data lines, a drain electrode directly connected to the other of said first and second data lines, and a gate electrode having a gate potential set such that the NMOS transistor is conductive when the potential difference between said first and second data lines becomes a predetermined regulated value while the data line differential amplifier circuit is activated, thereby limiting an amplitude between said first and second data lines to less than said predetermined regulated value by conduction of said transistor, wherein the gate potential of the NMOS transistor is set such that the NMOS transistor is conductive at least during part of a time period when the first and second data lines are not being precharged to and equalized at a precharge potential.

2. The semiconductor integrated circuit according to claim 1, wherein particular connecting points between said amplitude limiting circuit and said first and second data lines are respectively connected to first and second write control circuits which respectively supply first and second write data to said first and second data lines.

3. The semiconductor integrated circuit according to claim 1, further comprising: a main equalizing circuit which equalizes said first and second data lines by charging the first and second data lines to a power source potential in response to a first control signal; and a secondary equalizing circuit, operative for a predetermined period of time, which charges said first and second data lines.

4. The semiconductor integrated circuit according to claim 3, wherein said secondary equalizing circuit comprises first and second P channel MOS transistors which have drain electrodes each connected to said first and second data lines, source electrodes each connected to the power source potential, and gate electrodes which are connected with each other, and continuously assist equalizing operation of said main equalizing circuit by supplying a second control signal so as to start charging of said first and second data lines.

5. The semiconductor integrated circuit according to claim 1, wherein said first and second data lines are respectively connected to third and fourth data lines through a second switch circuit for performing ON/OFF operation on the basis of a third control signal; and said third and fourth data lines comprise: a second equalizing circuit for equalizing a potential of said third and fourth data lines by charging the third and fourth data lines to a power source potential, and a second data line differential amplifier circuit for amplifying a potential difference between said third and fourth data lines.

6. The semiconductor integrated circuit according to claim 1, further comprising: a fourth switch circuit provided between said amplitude limiting circuit and said data line differential amplifier circuit.

7. The semiconductor integrated circuit according to claim 1, wherein said first and second data lines are respectively connected to third and fourth data lines through connecting terminals; said third and fourth data lines comprise a second data line differential amplifier circuit for amplifying a potential difference between said third and fourth data lines; and said second data line differential amplifier circuit comprises a current mirror type differential amplifier circuit which functions as a switch circuit for respectively switching over a connection of said first and third data lines and a connection of second and fourth data lines, said second data line differential amplifier circuit comprising a pair of transistors coupled to receive output signals at gate electrodes of the transistors.

8. A semiconductor integrated circuit for reading data in memory cells comprising: a memory cell matrix having memory cells arranged in a plurality of rows and a plurality of columns along two directions which are at right angles to each other; a plurality of word lines each arranged at one row of said cell matrix; a plurality of bit line pairs which have a pair of bit lines arranged at each column of said cell matrix, and each pair of which has a first and a second bit line for reading said data; a plurality of bit line differential amplifier circuits, each of which is provided for each pair of the plurality of said bit line pairs and amplifies a potential difference between said first and second bit lines; a pair of data lines having a first data line connected to the plurality of said first bit lines and a second data line connected to the plurality of said second bit lines; a first switch circuit, provided between the plurality of said bit line differential amplifier circuits of each pair of the plurality of pairs of said bit lines and said pair of data lines; a data line differential amplifier circuit for amplifying the potential difference between said data line pair and for generating complimentary signals having a first signal and a second signal; and an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor which has a source electrode directly connected to one of said first and second data lines, a drain electrode directly connected to the other of said first and second data lines, and a gate electrode having a gate potential set such that the NMOS transistor is conductive when the potential difference between said first and second data line becomes a predetermined regulated value while the data line differential amplifier circuit is activated, said amplitude limiting circuit limiting an amplitude between said first and second data lines to less than said predetermined regulated value, said predetermined regulated value being smaller than a voltage difference between said first and second signals, wherein the gate potential of the NMOS transistor is set such that the NMOS transistor is conductive at least during part of a time period when the first and second data lines are not being precharged to and equalized at a precharge potential.

9. The semiconductor integrated circuit according to claim 8, further comprising a second switch circuit provided between said amplitude limiting circuit and said data line differential amplifier circuit.

10. The semiconductor integrated circuit according to claim 8, wherein said first and second data lines are respectively connected to third and fourth data lines through connecting terminals; said third and fourth data lines comprise a second data line differential amplifier circuit for amplifying a potential difference between said third and fourth data lines; and said second data line differential amplifier circuit comprises a current mirror type differential amplifier circuit which functions as a switch circuit for respectively switching over a connection of said first and third data lines and a connection of second and fourth data lines, said second data line differential amplifier circuit comprising a pair of transistors coupled to receive output signals at gate electrodes of the transistors.

11. A semiconductor integrated circuit comprising: at least one memory cell having a first transistor of a first conductive type having a gate, a source and a drain, the memory cell further having a capacitor connected between the source of the first transistor and a power source; a word line connected to the gate of the first transistor; at least one bit line pair, the pair having a first and a second bit line, the first bit line connected to the drain of the first transistor; a first and second data line; at least one first pair of transistors of the first conductive type connected in series to each other and connected to the bit lines; at least one first pair of transistors of a second conductive type connected in series to each other and connected to the bit lines and to the first transistor pair of the first conductive type to form a bit line differential amplifier that amplifies a potential difference between the bit lines; at least one second pair of transistors of the first conductive type, one of the transistors in the second transistor pair of the first conductive type having a source connected to the first bit line and a drain connected to the first data line, the other of the transistors in the second transistor pair of the first conductive type having a source connected to the second bit line and a drain connected to the second data line, the second transistor pair of the first conductive type having gates connected to each other to which a first control signal is applied, the second transistor pair of the first conductive type, in response to the first control signal, transferring the potential difference between the bit lines amplified by the differential amplifier to the data lines; a second transistor of the first conductive type having a drain connected to the first data line, a source connected to the second data line and a gate to which a second control signal is applied, wherein the second transistor of the first conductive type forms an amplitude limiting circuit, and in response to the second control signal, maintains the potential difference between the data lines at a threshold level of the second transistor or more; and a second pair of transistors of the second conductive type having sources connected to the power source, a drain of one of the second pair of transistors of the second conductive type being connected to the first data line and a drain of the other of the second transistor pair of the second conductive type being connected to the second data line, and gates of the second transistor pair of the second conductive type being supplied a third control signal, wherein the second transistor pair of the second conductive type, in response to the third control signal, equalizes the data lines by charging the data lines to a predetermined potential, wherein the second control signal is set such that the second transistor of the first conductive type maintains the potential difference between the data lines at least during part of a time period when the second pair of transistors of the second conductive type is turned off to prevent the equalizing of the data lines.

12. A semiconductor integrated circuit according to claim 11, wherein the first and second transistors of the first conductive type and the first and second pair of transistors of the first conductive type are N channel metal oxide semiconductor (NMOS) transistors, and the first and second pair of transistors of the second conductive type are P channel metal oxide semiconductor (PMOS) transistors.

13. A semiconductor integrated circuit according to claim 11 further comprising a first and a second inverter connected to the drain and the source of the second transistor, wherein first and second write data are applied via the first and second inverters to the first and second data lines, respectively.

14. A semiconductor integrated circuit according to claim 11 further comprising a third pair of transistors of the second conductive type having sources connected to the power source, a drain of one of the third transistor pair of the second conductive type being connected to the first data line and another drain of the other of the third transistor pair of the second conductive type being connected to the second data line, and gates of the third transistor pair of the second conductive type being supplied with a fourth control signal, the third transistor pair of the second conductive type being operative for a predetermined time period in response to the fourth control signal to shorten a charging operation of the first and second data lines.

15. A semiconductor integrated circuit according to claim 11 further comprising: a third pair of transistors having one transistor of the first conductive type and one transistor of the second conductive type connected in series to each other and to the first data line at a series connection point of the third transistor pair; and a fourth pair of transistors having one transistor of the first conductive type and one transistor of the second conductive type connected in series to each other and to the second line at a series connection point of the fourth transistor pair, wherein the third and fourth transistor pairs form a data line differential amplifier that amplifies the potential difference between the data lines.

16. A semiconductor integrated circuit according to claim 15 further comprising a fourth pair of transistors of the second conductive type, the first transistor pair of the first and second conductive types connected to the first data line via one of the fourth transistor pair, the second transistor pair of the first and second conductive types connected to the second data line via the other of the fourth transistor pair, the fourth transistor pair transferring the potential difference of the data to the data line differential amplifier in response to a fourth control signal.

17. A semiconductor integrated circuit comprising: a memory cell array having a plurality of memory cells operating at a power source potential; a plurality of bit line pairs, each having a first and a second bit line and connected to one of the memory cells; a first and a second data line connected to the first and second bit lines, respectively, via a differential amplifier; a limiting circuit consisting of one metal oxide semiconductor (MOS) transistor, responsive to a first control signal, for keeping a potential difference between the data lines induced by the differential amplifier at a threshold level of the MOS transistor or more but lower than the power source potential, the limiting circuit operating while the differential amplifier is activated; and means, responsive to a second control signal, for equalizing the data lines by charging the data lines to a predetermined potential, wherein the limiting circuit operates to limit the potential difference between the data lines at least during part of a time period when the means for equalizing is turned off to prevent the equalizing of the data lines.

18. A semiconductor integrated circuit comprising: at least one memory cell operating at a power source potential; at least one bit line differential amplifier connected to the memory cell via a bit line pair, the bit line differential amplifier generating a first potential difference by amplifying a first potential difference on the bit line pair; a first switch connected to the differential amplifier via the bit line pair, the first switch transferring the amplified first potential difference to a data line pair; a limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor having a source directly connected to one of the data line pair, a drain directly connected to the other of the data line pair, and a gate to which a control signal is applied, said limiting circuit limiting a second potential difference (V.sub.2) between the data line pair to a threshold level (V.sub.th) of the NMOS transistor or more but lower than the power source potential (V.sub.th .ltoreq.V.sub.2 <V.sub.cc); a second switch connected to the limiting circuit via the data line pair, the second potential difference being transferred via the second switch; and an equalizer connected to the second switch via the data line pair, the equalizer equalizing the data line pair, wherein the limiting circuit operates to limit the second potential difference between the data line pair at least during part of a time period when the equalizer is turned off to prevent the equalizing of the data line pair.

19. A dynamic random access memory having a plurality of memory cells, data stored in one of the memory cells being amplified and transferred from a bit line pair to a data line pair, the dynamic random access memory comprising: an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor having a source directly connected to one of the data line pair, a drain directly connected to the other of the data line pair and a gate to which a first control signal is applied, the NMOS transistor keeping a potential difference between the data lines at a threshold level of the NMOS transistor or more in response to the first control signal; and a pair of P channel metal oxide semiconductor (PMOS) transistors having sources connected to a power source, a drain of one of the PMOS transistors being connected to one of the data line pair, a drain of the other of the PMOS transistors being connected to the other of the data line pair, the pair of PMOS transistors equalizing the data line pair by charging to a potential supplied by the power source the data line pair whose potential difference remains at the threshold level of the NMOS transistor or more, wherein the first control signal is set such that the amplitude limiting circuit operates to limit the potential difference between the data lines during at least part of an active operating cycle of the dynamic random access memory, and during at least part of a time period when the pair of PMOS transistors is turned off to prevent the equalizing of the data line pair.

20. In a semiconductor memory device of the type having: a plurality of memory cells, a plurality of bit line pairs, each having a first and a second bit line, either the first or the second bit line, or both the first and second bit lines being connected to one of the memory cells, a plurality of differential amplifiers connected between the first and second bit lines, a first and a second data line selectively coupled to the first and second bit lines via coupling means, and equalizing means, responsive to a first control signal, for equalizing the data lines by charging the data lines to a predetermined potential, the improvement which comprises: an amplitude limiting circuit consisting of one transistor having a current path and a control electrode, the current path of the transistor being directly connected between the first and second data lines, and the control electrode of the transistor receiving a second control signal, for limiting a potential difference between the first and second data lines to a threshold level of the transistor or more in response to the second control signal. wherein the second control signal is set such that the amplitude limiting circuit operates to limit the potential difference between the first and second data lines at least during part of a time period when the equalizing means is turned off to prevent the equalizing of the data lines.

21. The semiconductor memory device according to claim 20, wherein the second control signal activates the amplitude limiting circuit to limit the potential difference between the first and second data lines during at least substantially all of an active operating cycle of the semiconductor memory device.

22. The semiconductor memory device according to claim 20, wherein said one transistor consists of an N-channel MOS (NMOS) transistor.

23. The semiconductor memory device according to claim 20, wherein said one transistor consists of a P-channel MOS (PMOS) transistor.

24. A semiconductor memory device comprising: a memory cell matrix having: a plurality of memory cells arranged in matrix; a plurality of word lines, each word line being connected to a row of memory cells in the memory cell matrix; and a plurality of bit line pairs each having a first bit line and a second bit line, each bit line pair being connected to a column of memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the first bit lines of the bit line pairs being selectively coupled to the first data line and the second bit lines of the bit line pairs being selectively coupled to the second data line; a first means for precharging the first and the second data lines to a first potential (V); a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth) and including a gate electrode; and a second means for supplying a second potential to the gate electrode of the first NFET for making the first NFET conductive at least during part of a time period when the first means is turned off to prevent the precharging of the first and the second data lines, the second potential being a maximum voltage level (.phi.1.sub.max) that is less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth).

25. A semiconductor memory device comprising: a memory cell matrix having: a plurality of memory cells arranged in matrix; a plurality of word lines, each word line being connected to a row of memory cells in the memory cell matrix; and a plurality of bit line pairs each having a first bit line and a second bit line, each bit line pair being connected to a column of memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the first bit lines of the bit line pairs being selectively coupled to the first data line and the second bit lines of the bit line pairs being selectively coupled to the second data line; a first means for precharging the first and the second data lines to a first potential (V); a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth) and including a gate electrode; and a second means for supplying a second potential to the gate electrode of the first NFET for making the first NFET conductive at least while the first data line pair is being sensed, the second potential being a maximum voltage level (.phi.1.sub.max) that is less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth), wherein in a first predetermined period, the first means precharges the first and the second data lines to the first potential and the second means supplies the second potential to the gate electrode of the first NFET, and in a second predetermined period that follows the first predetermined period, the first means is turned off to discontinue the precharging of the first and the second data lines, while the second means continues to supply the second potential to the gate electrode of the first NFET.

26. The semiconductor memory device as defined in claim 25, wherein the first means includes: a first P channel field effect transistor (PFET) connected between the first and the second data lines; a second PFET connected between the first data line and a power supply terminal, the power supply terminal supplying the first potential to the second PFET; and a third PFET connected between the second data line and the power supply terminal, the power supply terminal supplying the first potential to the third PFET, wherein gate electrodes of the first, the second, and the third PFETs are connected together.

27. The semiconductor memory device as defined in claim 25, wherein the first and the second potentials are equal.

28. The semiconductor memory device as defined in claim 25, further comprising an amplifier for amplifying a potential difference between the first and the second data lines, the amplifier being activated in the second predetermined period.

29. The semiconductor memory device as defined in claim 24, wherein the first means includes: a first P channel field effect transistor (PFET) connected between the first and the second data lines; a second PFET connected between the first data line and a power supply terminal, the power supply terminal supplying the first potential to the second PFET; and a third PFET connected between the second data line and the power supply terminal, the power supply terminal supplying the first potential to the third PFET, wherein gate electrodes of the first, the second, and the third PFETs are connected together.

30. The semiconductor memory device as defined in claim 24, wherein the first and the second potentials are equal.

31. The semiconductor memory device as defined in claim 27, further comprising an amplifier for amplifying a potential difference between the first and the second data lines.

32. The semiconductor memory as defined in claim 25, further comprising: a second data line pair having a third data line and a fourth data line, the third data line being coupled to the first data line and the fourth data line being coupled to the second data line in response to a control signal; and a third means for precharging the third and the fourth data lines to the first potential, wherein the third means precharges the third and the fourth data lines before the third and fourth data lines are coupled to the first and second data lines, respectively.

33. The semiconductor memory device as defined in claim 32, wherein the third means includes: a first P-channel field effect transistor (PFET) connected between the third and the fourth data lines; a second PFET connected between the third data line and a power supply terminal, the power supply terminal supplying the first potential to the second PFET; and a third PFET connected between the fourth data line and the power supply terminal, the power supply terminal supplying the first potential to the third PFET, wherein gate electrodes of the first, the second, and the third PFETs are connected together.

34. The semiconductor memory device as defined in claim 24, further comprising an amplifier for amplifying a potential difference between the first and the second data lines.

35. The semiconductor memory device as defined in claim 28, wherein the amplifier includes: a first pair of transistors having one NFET and one P channel field effect transistor (PFET); and a second pair of transistors having one NFET and one PFET, wherein the NFET and the PFET of each pair of transistors are connected in series between a power supply terminal and a ground terminal, gates of the NFET and the PFET of the first pair of transistors being connected to the second data line and to a series connection point of the second pair of transistors, and gates of the NFET and the PFET of the second pair of transistors being connected to the first data line and to a series connection point of the first pair of transistors.

36. A method for controlling a semiconductor memory, the semiconductor memory of the type having: a memory cell matrix including a plurality of memory cells arranged in matrix, word lines each connected to a row of memory cells in the memory cell matrix, and bit line pairs each connected to a column of memory cells in the memory cell matrix; a first data line pair having a first data line and a second data line, the bit line pairs being selectively coupled to the first data line pair; a precharging circuit; and a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth), the method comprising the steps of: precharging the first and the second data lines to a first potential (V); supplying a second potential (.phi.1.sub.max) to a gate electrode of the first NFET for making the first NFET conductive at least while the first data line pair is being sensed, the second potential being less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth); and discontinuing the precharging of the first and the second data lines, while continuing to supply the second potential to the gate electrode of the first NFET.

37. The method for controlling a semiconductor memory as defined in claim 36, wherein the first and the second potentials are equal so that the first NFET operates to limit a potential difference between the first and second data lines to the threshold voltage (Vth) of the first NFET or more while the gate electrode of the first NFET is receiving the second potential.

38. The method for controlling a semiconductor memory as defined in claim 37, further comprising the step of: amplifying a potential difference between the first and the second data lines, while continuing to supply the second potential to the gate electrode of the first NFET.

39. The method for controlling a semiconductor memory as defined in claim 36, further comprising the steps of: precharging a second data line pair, which has a third data line and a fourth data line, to the first potential; and coupling the second data line pair to the first data line pair in response to a control signal, the third data line being coupled to the first data line and the fourth data line being coupled to the second data line.

40. The method for controlling a semiconductor memory as defined in claim 36, further comprising the step of: amplifying a potential difference between the first and the second data lines, while continuing to supply the second potential to the gate electrode of the first NFET.

41. A semiconductor memory device comprising: a memory cell matrix including: a plurality of memory cells arranged in matrix; and a plurality of bit line pairs, each bit line pair being connected to memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the bit line pairs being selectively coupled to the first data line pair; a precharging means for precharging the first and the second data lines to a first potential (V); and a limiting circuit consisting of one limiting transistor directly connected between the first data line and the second data line, the limiting transistor having a threshold voltage (Vth) and a gate electrode, wherein a control signal is supplied to the gate electrode of the limiting transistor, one of the bit line pairs is coupled to the first data line pair during an output period of a memory read cycle, the control signal is held at a second potential (.phi.1.sub.max) during the entire output period to keep the limiting circuit activated during the entire output period, thereby limiting the potential difference between the first data line and the second data line to the threshold voltage of the limiting transistor or more during the output period, and the precharging means is turned off to prevent the precharging of the first and the second data lines during at least part of the output period.

42. The semiconductor memory device as defined in claim 41, further comprising an amplifier for amplifying a potential difference between the first and the second data lines, the amplifier being activated during at least part of the output period of a memory read cycle.

43. The semiconductor memory device as defined in claim 41, wherein the limiting transistor is a P channel field effect transistor (PFET), and the second potential is less than the sum of a gate ground potential (V.sub.GND) and the first potential, less the threshold voltage of the limiting transistor (.phi.1.sub.max <V.sub.GND +V-Vth).

44. The semiconductor memory device as defined in claim 41, wherein the limiting transistor is an N channel field effect transistor (NFET), and the second potential is less than the sum of the first potential and the threshold voltage of the limiting transistor (.phi.1.sub.max <V+Vth).

45. The semiconductor memory device as defined in claim 44, wherein the precharging means includes: a first P channel field effect transistor (PFET) connected between the first and the second data lines; a second PFET connected between the first data line and a power supply terminal, the power supply terminal supplying the first potential to the second PFET; and a third PFET connected between the second data line and the power supply terminal, the power supply terminal supplying the first potential to the third PFET, wherein gate electrodes of the first, the second, and the third PFETs are connected together.

46. The semiconductor memory device as defined in claim 44, wherein the first and the second potentials are equal.

47. The semiconductor memory device as defined in claim 44, further comprising an amplifier for amplifying a potential difference between the first and the second data lines, the amplifier being activated during at least part of the output period of a memory read cycle.

48. The semiconductor memory as defined in claim 41, further comprising: a second data line pair having a third data line and a fourth data line, the third data line being coupled to the first data line and the fourth data line being coupled to the second data line during the output period of a memory read cycle; and a second means for precharging the third and the fourth data lines to the first potential, wherein the second means for precharging precharges the third and the fourth data lines before the third and fourth data lines are coupled to the first and second data lines, respectively.

49. The semiconductor memory device as defined in claim 48, further comprising an amplifier for amplifying a potential difference between the first and the second data lines, the amplifier being activated during at least part of the output period of a memory read cycle.

50. The semiconductor integrated circuit as defined in claim 1, wherein the gate potential of the NMOS transistor is set such that the NMOS transistor is conductive at least during substantially the entire period that the data line differential amplifier circuit is activated.

51. The semiconductor integrated circuit as defined in claim 1, wherein the gate potential of the NMOS transistor is set to a power source potential to make the NMOS transistor conductive while the data line differential amplifier circuit is activated and during at least part of the time period when the first and second data lines are not being precharged to and equalized at a precharge potential.

52. The semiconductor integrated circuit as defined in claim 1, wherein the gate potential of the NMOS transistor is always at a power source potential.

53. The semiconductor integrated circuit as defined in claim 1, further comprising an equalizer connected between the first and second data lines to selectively equalize the data line pair at an equalization potential.

54. The semiconductor integrated circuit as defined in claim 8, wherein the gate potential of the NMOS transistor is always at a power source potential.

55. The semiconductor integrated circuit as defined in claim 8, further comprising an equalizer connected between the first and second data lines to selectively equalize the data line pair at an equalization potential.

56. The semiconductor integrated circuit as defined in claim 11, wherein the second control signal is set to a power source potential to make the second transistor of the first conductive type maintain the potential difference between the data lines during part of the time period when the second pair of transistors of the second conductive type is turned off, and the predetermined potential is equal to the power source potential.

57. The semiconductor integrated circuit as defined in claim 11, wherein in response to the second control signal, the amplitude limiting circuit maintains the potential difference between the data lines at the threshold level of the second transistor.

58. The semiconductor integrated circuit as defined in claim 11, further comprising a second transistor of the second conductive type having a source connected to the first data line, a drain connected to the second data line, and a gate to which the third control signal is applied, wherein the second transistor pair of the second conductive type and the second transistor of the second conductive type, in response to the third control signal, equalizes the data lines by charging and equalizing the data lines to the predetermined potential.

59. The semiconductor integrated circuit as defined in claim 17, wherein the limiting circuit operates to limit the potential difference between the data lines at least during substantially the entire period that the differential amplifier is activated, and the predetermined potential is equal to the power source potential.

60. The semiconductor integrated circuit as defined in claim 17, wherein the first control signal is always at the power source potential.

61. The semiconductor integrated circuit as defined in claim 18, wherein the control signal is set to the power source potential to make the limiting circuit operate to limit the second potential difference between the data line pair during at least part of the time period when the equalizer is turned off.

62. The semiconductor integrated circuit as defined in claim 18, wherein the control signal is always at the power source potential.

63. The dynamic random access memory as defined in claim 19, wherein the amplitude limiting circuit operates to limit the potential difference between the data lines at least during substantially the entire active operating cycle of the dynamic random access memory.

64. The dynamic random access memory as defined in claim 19, wherein the first control signal is set to the power source potential to make the amplitude limiting circuit operate to limit the potential difference between the data lines during at least part of the active operating cycle, and during at least part of the time period when the pair of PMOS transistors is turned off.

65. The dynamic random access memory as defined in claim 19, wherein the first control signal is set to the power source potential throughout an entire operating cycle of the dynamic random access memory.

66. The dynamic random access memory as defined in claim 19, wherein the NMOS transistor keeps the potential difference between the data lines at the threshold level of the NMOS transistor in response to the first control signal.

67. The dynamic random access memory as defined in claim 19, further comprising a third PMOS transistor, the source of the third PMOS transistor being connected to one of the data line pair and the drain of the third PMOS transistor being connected to the other of the data line pair, wherein the pair of PMOS transistors and the third PMOS transistor equalizes the data line pair at a potential supplied by the power source.

68. The semiconductor memory device according to claim 20, wherein the second control signal is set to a power source potential to make the amplitude limiting circuit operate to limit the potential difference between the first and second data lines during at least part of the time period when the equalizing means is turned off, and the predetermined potential is equal to the power source potential.

69. The semiconductor memory device as defined in claim 24, wherein second means supplies the second potential to the gate electrode of the first NFET during at least substantially the entire period that the first data line pair is being sensed.

70. The semiconductor memory device as defined in claim 24, wherein the first and second potentials are equal to a power source potential.

71. The semiconductor memory device as defined in claim 24, wherein the second means supplies a power source potential to the gate electrode of the first NFET throughout an entire operating cycle of the semiconductor memory device.

72. The method as defined in claim 36, wherein the second potential is supplied to the gate electrode of the first NFET during at least substantially the entire period that the first data line pair is being sensed.

73. The method as defined in claim 36, wherein the first and second potentials are equal to a power source potential.

74. The method as defined in claim 36, wherein a power source potential is supplied to the gate electrode of the first NFET throughout an entire operating cycle of the semiconductor memory.

75. The method as defined in claim 36, wherein the step of precharging includes both precharging and equalizing the first and the second data lines to the first potential, and the step of discontinuing the precharging includes discontinuing both precharging and equalizing of the first and the second data lines.

76. The semiconductor memory device as defined in claim 41, wherein the first and second potentials are equal to a power source potential.

77. The semiconductor memory device as defined in claim 41, wherein the control signal is held at a power source potential throughout an entire operating cycle of the semiconductor memory device.

78. A semiconductor integrated circuit for reading data in memory cells comprising: a memory cell matrix having dynamic random access memory (DRAM) cells arranged in a plurality of rows and a plurality of columns along two directions which are at right angles to each other; a plurality of word lines each arranged at one row of said plurality of rows of said cell matrix; a plurality of bit line pairs which have a pair of bit lines arranged at each column of said plurality of bit line pairs of said cell matrix, and each pair of which has a first and a second bit line for reading said data; A plurality of bit line differential amplifier circuits, each of which is provided for each pair of the plurality of said bit line pairs and amplifies a potential difference between said first and second bit lines; a pair of data lines having a first data line coupled to the plurality of said first bit lines and a second data line coupled to the plurality of said second bit lines; a first switch circuit, provided between the plurality of said bit line differential amplifier circuits of each pair of the plurality of pairs of said bit lines and said pair of data lines, for turning on and off a charge transmission from each of said bit line pairs to said data line pair; a data line differential amplifier circuit for amplifying the potential difference between said data line pair; and an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor which has a source electrode directly connected to one of said first and second data lines, a drain electrode directly connected to the other of said first and second data lines, and a gate electrode having a gate potential set such that the NMOS transistor is conductive when the potential difference between said first and second data lines becomes a predetermined regulated value while the data line differential amplifier circuit is activated, thereby limiting an amplitude between said first and second data lines to less than said predetermined regulated value by conduction of said transistor, wherein in a first predetermined period, the first and second data lines are precharged to a precharge potential, and in a second predetermined period that follows the first predetermined period, the precharging of the first and second data lines is discontinued, and the NMOS transistor is conductive.

79. The semiconductor integrated circuit as defined in claim 78, wherein in the first predetermined period, the NMOS transistor is conductive.

80. The semiconductor integrated circuit as defined in claim 78, wherein in the first predetermined period, the NMOS transistor is not conductive.

81. A semiconductor integrated circuit for reading data in memory cells comprising: a memory cell matrix having memory cells arranged in a plurality of rows and a plurality of columns along two directions which are at right angles to each other; a plurality of word lines each arranged at one row of said cell matrix; a plurality of bit line pairs which have a pair of bit lines arranged at each column of said cell matrix, and each pair of which has a first and second bit line for reading said data; a plurality of bit line differential amplifier circuits, each of which is provided for each pair of the plurality of said bit line pairs and amplifies a potential difference between said first and second bit lines; a pair of data lines having a first data line connected to the plurality of said first bit lines and a second data line connected to the plurality of said second bit lines; a first switch circuit, provided between the plurality of said bit line differential amplifier circuits of each pair of the plurality of pairs of said bit lines and said pair of data lines; a data line differential amplifier circuit for amplifying the potential difference between said data line pair and for generating complimentary signals having a first signal and a second signal; and an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor which has a source electrode directly connected to one of said first and second data lines, a drain electrode directly connected to the other of said first and second data lines, and a gate electrode having a gate potential set such that the NMOS transistor is conductive when the potential difference between said first and second data line becomes a predetermined regulated value while the data line differential amplifier circuit is activated, said amplitude limiting circuit limiting an amplitude between said first and second data lines to less than said predetermined regulated value, said predetermined regulated value being smaller than a voltage difference between said first and second signals, wherein in a first predetermined period, the first and second data lines are precharged to a precharge potential, and in a second predetermined period that follows the first predetermined period, the precharging of the first and second data lines is discontinued, and the NMOS transistor is conductive.

82. The semiconductor integrated circuit as defined in claim 81, wherein in the first predetermined period, the NMOS transistor is conductive.

83. The semiconductor integrated circuit as defined in claim 81, wherein in the first predetermined period, the NMOS transistor is not conductive.

84. A semiconductor integrated circuit comprising: at least one memory cell having a first transistor of a first conductive type having a gate, a source and a drain, the memory cell further having a capacitor connected between the source of the first transistor and a power source; a word line connected to the gate of the first transistor; at least one bit line pair, the pair having a first and a second bit line, the first bit line connected to the drain of the first transistor; a first and second data line; at least one first pair of transistors of the first conductive type connected in series to each other and connected to the bit lines; at least one first pair of transistors of a second conductive type connected in series to each other and connected to the bit lines and to the first transistor pair of the first conductive type to form a bit line differential amplifier that amplifies a potential difference between the bit lines; at least one second pair of transistors of the first conductive type, one of the transistors in the second transistor pair of the first conductive type having a source connected to the first bit line and a drain connected to the first data line, the other of the transistors in the second transistor pair of the first conductive type having a source connected to the second bit line and a drain connected to the second data line, the second transistor pair of the first conductive type having gates connected to each other to which a first control signal is applied, the second transistor pair of the first conductive type, in response to the first control signal, transferring the potential difference between the bit lines amplified by the differential amplifier to the data lines; a second transistor of the first conductive type having a drain connected to the first data line, a source connected to the second data line and a gate to which a second control signal is applied, wherein the second transistor of the first conductive type forms an amplitude limiting circuit, and in response to the second control signal, maintains the potential difference between the data lines at a threshold level of the second transistor or more; and a second pair of transistors of the second conductive type having sources connected to the power source, a drain of one of the second pair of transistors of the second conductive type being connected to the first data line and a drain of the other of the second transistor pair of the second conductive type being connected to the second data line, and gates of the second transistor pair of the second conductive type being supplied a third control signal, wherein the second transistor pair of the second conductive type, in response to the third control signal, equalizes the data lines by charging the data lines to a predetermined potential, wherein in a first predetermined period, the data lines are equalized at the predetermined potential, and in a second predetermined period that follows the first predetermined period, the equalizing of the data lines is discontinued, and the second transistor of the first conductive type operates to limit the potential difference between the data lines.

85. The semiconductor integrated circuit as defined in claim 84, wherein the first predetermined period the second transistor of the first conductive type operates to limit the potential difference between the data lines.

86. The semiconductor integrated circuit as defined in claim 84, wherein in the first predetermined period the second transistor of the first conductive type does not operate to limit the potential difference between the data lines.

87. A semiconductor integrated circuit comprising: a memory cell array having a plurality of memory cells operating at a power source potential; a plurality of bit line pairs, each having a first and a second bit line and connected to one of the memory cells; a first and a second data line connected to the first and second bit lines, respectively, via a differential amplifier; a limiting circuit consisting of one metal oxide semiconductor (MOS) transistor, responsive to a first control signal, for keeping a potential difference between the data lines induced by the differential amplifier at a threshold level of the MOS transistor or more but lower than the power source potential; and means, responsive to a second control signal, for equalizing the data lines by charging the data lines to a predetermined potential, wherein in a first predetermined period, the means for equalizing equalizes the data lines, and in a second predetermined period that follows the first predetermined period, the means for equalizing is turned off to discontinue the equalization of the data lines, and the MOS transistor operates to limit the potential difference between the data lines.

88. The semiconductor integrated circuit as defined in claim 87, wherein in the first predetermined period, the MOS transistor operates to limit the potential difference between the data lines.

89. The semiconductor integrated circuit as defined in claim 87, wherein in the first predetermined period, the MOS transistor does not operate to limit the potential difference between the data lines.

90. A semiconductor integrated circuit comprising: at least one memory cell operating at a power source potential; at least one bit line differential amplifier connected to the memory cell via a bit line pair, the bit line differential amplifier generating a first potential difference by amplifying a first potential difference on the bit line pair; a first switch connected to the differential amplifier via the bit line pair ,the first switch transferring the amplified first potential difference to a data line pair; a limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor having a source directly connected to one of the data line pair, a drain directly connected to the other of the data line pair, and a gate to which a control signal is applied, said limiting circuit limiting a second potential difference (V.sub.2) between the data line pair to a threshold level (V.sub.th) of the NMOS transistor or more but lower than the power source potential (V.sub.th .ltoreq.V.sub.2 <V.sub.cc); a second switch connected to the limiting circuit via the data line pair, the second potential difference being transferred via the second switch; and an equalizer connected to the second switch via the data line pair, the equalizer equalizing the data line pair by charging to the power source potential the data line pair, wherein in a first predetermined period, the equalizer equalizes the data line pair, and in a second predetermined period that follows the first predetermined period, the equalizer is turned off to discontinue the equalization of the data line pair, and the limiting circuit limits the second potential difference between the data line pair.

91. The semiconductor integrated circuit as defined in claim 90, wherein in the first predetermined period, the limiting circuit limits the second potential difference between the data line pair.

92. The semiconductor integrated circuit as defined in claim 90, wherein in the first predetermined period, the limiting circuit does not limit the second potential difference between the data line pair.

93. A dynamic random access memory having a plurality of memory cells, data stored in one of the memory cells being amplified and transferred from a bit line pair to a data line pair, the dynamic random access memory comprising: an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor having a source directly connected to one of the data line pair, a drain directly connected to the other of the data line pair and a gate to which a first control signal is applied, the NMOS transistor keeping a potential difference between the data lines at a threshold level of the NMOS transistor or more in response to the first control signal; and a pair of P channel metal oxide semiconductor (PMOS) transistors having sources connected to a power source, a drain of one of the PMOS transistors being connected to one of the data line pair, a drain of the other of the PMOS transistors being connected to one of the data line pair, a drain of the other of the PMOS transistors being connected to the other of the data line pair, the pair of PMOS transistors equalizing the data line pair by charging to a potential supplied by the power source the data line pair whose potential difference remains at the threshold level of the NMOS transistor or more, wherein in a first predetermined period, the data line pair is equalized by the pair of PMOS transistors, and in a second predetermined period that follows the first predetermined period, the equalization of the data line pair is discontinued, while the amplitude limiting circuit operates to limit the potential difference between the data lines.

94. The dynamic random access memory as defined in claim 93, wherein in the first predetermined period, the amplitude limiting circuit operates to limit the potential difference between the data lines.

95. The dynamic random access memory as defined in claim 93, wherein in the first predetermined period, the amplitude limiting circuit does not operate to limit the potential difference between the data lines.

96. In a semiconductor memory device of the type having: a plurality of memory cells, a plurality of bit line pairs, each having a first and a second bit line, either the first or the second bit line, or both the first and second bit lines being connected to one of the memory cells, a plurality of differential amplifiers connected between the first and second bit lines, a first and a second data line selectively coupled to the first and second bit lines via coupling means, and equalizing means, responsive to a first control signal, for equalizing the data lines by charging the data lines to a predetermined potential, the improvement which comprises: an amplitude limiting circuit consisting of one transistor having a current path and a control electrode, the current path of the transistor being directly connected between the first and second data lines, and the control electrode of the transistor receiving a second control signal, for limiting a potential difference between the first and second data lines to a threshold level of the transistor or more in response to the second control signal, wherein in a first predetermined period, the first control signal is active so that the equalizing means equalizes the data lines, and in a second predetermined period that follows the first predetermined period, the second control signal is inactive so that the equalizing means does not equalize the data lines, and the second control signal is at a level that causes the amplitude limiting circuit to limit the potential difference between the first and second data lines.

97. The semiconductor memory device as defined in claim 96, wherein in the first predetermined period, the second control signal is at a level that causes the amplitude limiting circuit to limit the potential difference between the first and second data lines.

98. The semiconductor memory device as defined in claim 96, wherein in the first predetermined period, the second control signal is at a level that prevents the amplitude limiting circuit from limiting the potential difference between the first and second data lines.

99. A semiconductor memory device comprising: a memory cell matrix having: a plurality of memory cells arranged in matrix; a plurality of word lines, each word line being connected to a row of memory cells in the memory cell matrix; and a plurality of bit line pairs each having a first bit line and a second bit line, each bit line pair being connected to a column of memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the first bit lines of the bit line pairs being selectively coupled to the first data line and the second bit lines of the bit line pairs being selectively coupled to the second data line; a first means for precharging the first and the second data lines to a first potential (V); a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth) and including a gate electrode; and a second means for supplying a second potential to the gate electrode of the first NFET for making the first NFET conductive at least while the first data line pair is being sensed, the second potential being a maximum voltage level (.phi..sub.1.sub.max) that is less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth), wherein in a first predetermined period, the first means precharges the first and the second data lines to the first potential and the second means does not supply the second potential to the gate electrode of the first NFET, and in a second predetermined period that follows the first predetermined period, the first means is turned off to discontinue the precharging of the first and the second data lines, and the second means supplies the second potential to the gate electrode of the first NFET.

100. A method for controlling a semiconductor memory, the semiconductor memory of the type having: a memory cell matrix including a plurality of memory cells arranged in matrix, word lines each connected to a row of memory cells in the memory cell matrix, and bit line pairs each connected to a column of memory cells in the memory cell matrix; a first data line pair having a first data line and a second data line, the bit line pairs being selectively coupled to the first data line pair; a precharging circuit; and a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth), the method comprising the steps of: precharging the first and the second data lines to a first potential (V); and supplying a second potential (.phi.1.sub.max) to a gate electrode of the first NFET for making the first NFET conductive at least while the first data line pair is being sensed, the second potential being less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth), wherein in a first predetermined period, the first and the second data lines are precharged, and in a second predetermined period that follows the first predetermined period, the first and second data lines are not precharged, and the second potential is supplied to the gate electrode of the first NFET.

101. The method as defined in claim 100, wherein in the first predetermined period, the second potential is supplied to the gate electrode of the first NFET.

102. The method as defined in claim 100, wherein in the first predetermined period, the second potential is not supplied to the gate electrode of the first NFET.

103. A semiconductor memory device comprising: a memory cell matrix including: a plurality of memory cells arranged in matrix; and a plurality of bit line pairs, each bit line pair being connected to memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the bit line pairs being selectively coupled to the first data line pair; a precharging means for precharging the first and the second data lines to a first potential (V); and a limiting circuit consisting of one limiting transistor directly connected between the first data line and the second data line, the limiting transistor having a threshold voltage (Vth) and a gate electrode, wherein a control signal is supplied to the gate electrode of the limiting transistor, before a predetermined period, the precharging means precharges the data lines, and during the predetermined period: the precharging means does not precharge the data lines; one of the bit line pairs is coupled to the first data line pair; and the control signal is held at a second potential (.phi.1.sub.max) to keep the limiting circuit activated, thereby limiting the potential difference between the first data line and the second data line to the threshold voltage of the limiting transistor or more during the predetermined period.

104. The semiconductor memory device as defined in claim 103, wherein before the predetermined period and while the precharging means precharges the data lines, the control signal is held at the second potential to keep the limiting circuit activated.

105. The semiconductor memory device as defined in claim 103, wherein before the predetermined period and while the precharging means precharges the data lines, the control signal is not held at the second potential.

106. A semiconductor integrated circuit for reading data in memory cells comprising: a memory cell matrix having dynamic random access memory (DRAM) cells arranged in a plurality of rows and a plurality of columns along two directions which are at right angles to each other; a plurality of word lines each arranged at one row of said plurality of rows of said cell matrix; a plurality of bit line pairs which have a pair of bit lines arranged at each column of said plurality of bit line pairs of said cell matrix, and each pair of which has a first and a second bit line for reading said data; a plurality of bit line differential amplifier circuits, each of which is provided for each pair of the plurality of said bit line pairs and amplifies a potential difference between said first and second bit lines; a pair of data lines having a first data line coupled to the plurality of said first bit lines and a second data line coupled to the plurality of said second bit lines; a first switch circuit, provided between the plurality of said bit line differential amplifier circuits of each pair of the plurality of pairs of said bit lines and said pair of data lines, for turning on and off a charge transmission from each of said bit line pairs to said data line pair; a data line differential amplifier circuit for amplifying the potential difference between said data line pair; an equalizer connected between the first and second data lines to selectively equalize the data line pair at an equalization potential; and an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor which has a source electrode directly connected to one of said first and second data lines, a drain electrode directly connected to the other of said first and second data lines, and a gate electrode having a gate potential set such that the NMOS transistor is conductive when the potential difference between said first and second data lines becomes a predetermined regulated value while the data line differential amplifier circuit is activated, thereby limiting an amplitude between said first and second data lines to less than said predetermined regulated value by conduction of said transistor, wherein the gate potential of the NMOS transistor is set such that the amplitude limiting operation of the amplitude limiting circuit is not synchronized with the equalization operation of the equalizer.

107. A semiconductor integrated circuit for reading data in memory cells comprising: a memory cell matrix having memory cells arranged in a plurality of rows and a plurality of columns along two directions which are at right angles to each other; a plurality of word lines each arranged at one row of said cell matrix; a plurality of bit line pairs which have a pair of bit lines arranged at each column of said cell matrix, and each pair of which has a first and a second bit line for reading said data; a plurality of bit line differential amplifier circuits, each of which is provided for each pair of the plurality of said bit line pairs and amplifies a potential difference between said first and second bit lines; a pair of data lines having a first data line connected to the plurality of said first bit lines and a second data line connected to the plurality of said second bit lines; a first switch circuit, provided between the plurality of said bit line differential amplifier circuits of each pair of the plurality of pairs of said bit lines and said pair of data lines; a data line differential amplifier circuit for amplifying the potential difference between said data line pair and for generating complimentary signals having a first signal and a second signal; an equalizer connected between the first and second data lines to selectively equalize the data line pair at an equalization potential; and an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor which has a source electrode directly connected to one of said first and second data lines, a drain electrode directly connected to the other of said first and second data lines, and a gate electrode having a gate potential set such that the NMOS transistor is conductive when the potential difference between said first and second data line becomes a predetermined regulated value while the data line differential amplifier circuit is activated, said amplitude limiting circuit limiting an amplitude between said first and second data lines to less than said predetermined regulated value, said predetermined regulated value being smaller than a voltage difference between said first and second signals, wherein the gate potential of the NMOS transistor is set such that the amplitude limiting operation of the amplitude limiting circuit is not synchronized with the equalization operation of the equalizer.

108. A semiconductor integrated circuit comprising: at least one memory cell having a first transistor of a first conductive type having a gate, a source and a drain, the memory cell further having a capacitor connected between the source of the first transistor of the first conductive type and a power source; a word line connected to the gate of the first transistor of the first conductive type; at least one bit line pair, the pair having a first and a second bit line, the first bit line connected to the drain of the first transistor of the first conductive type; a first and second data line; at least one first pair of transistors of the first conductive type connected in series to each other and connected to the bit lines; at least one first pair of transistors of a second conductive type connected in series to each other and connected to the bit lines and to the first transistor pair of the first conductive type to form a bit line differential amplifier that amplifies a potential difference between the bit lines; at least one second pair of transistors of the first conductive type, one of the transistors in the second transistor pair of the first conductive type having a source connected to the first bit line and a drain connected to the first data line, the other of the transistors in the second transistor pair of the first conductive type having a source connected to the second bit line and a drain connected to the second data line, the second transistor pair of the first conductive type having gates connected to each other to which a first control signal is applied, the second transistor pair of the first conductive type, in response to the first control signal, transferring the potential difference between the bit lines amplified by the differential amplifier to the data lines; a second transistor of the first conductive type having a drain connected to the first data line, a source connected to the second data line and a gate to which a second control signal is applied, wherein the second transistor of the first conductive type forms an amplitude limiting circuit, and in response to the second control signal, maintains the potential difference between the data lines at a threshold level of the second transistor or more; and a second pair of transistors of the second conductive type having sources connected to the power source, a drain of one of the second pair of transistors of the second conductive type being connected to the first data line and a drain of the other of the second transistor pair of the second conductive type being connected to the second data line, and gates of the second transistor pair of the second conductive type being supplied a third control signal, and a second transistor of the second conductive type having a source connected to the first data line, a drain connected to the second data line, and a gate to which the third control signal is applied, wherein the second transistor pair of the second conductive type and the second transistor of the second conductive type, in response to the third control signal, equalizes the data lines by charging and equalizing the data lines to a predetermined potential, wherein the second control signal is different from and is not synchronized with the third control signal.

109. A semiconductor integrated circuit comprising: a memory cell array having a plurality of memory cells operating at a power source potential; a plurality of bit line pairs, each having a first and a second bit line and connected to one of the memory cells; a first and a second data line connected to the first and second bit lines, respectively, via a differential amplifier; a limiting circuit consisting of one metal oxide semiconductor (MOS) transistor, responsive to a first control signal, for keeping a potential difference between the data lines induced by the differential amplifier at a threshold level of the MOS transistor or more but lower than the power source potential, the limiting circuit operating while the differential amplifier is activated; and means, responsive to a second control signal, for equalizing the data lines, wherein the first control signal is different from and is not synchronized with the second control signal.

110. A semiconductor integrated circuit comprising: at least one memory cell operating at a power source potential; at least one bit line differential amplifier connected to the memory cell via a bit line pair, the bit line differential amplifier generating a first potential difference by amplifying a first potential difference on the bit line pair; a first switch connected to the differential amplifier via the bit line pair, the first switch transferring the amplified first potential difference to a data line pair; a limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor having a source directly connected to one of the data line pair, a drain directly connected to the other of the data line pair, and a gate to which a control signal is applied, said limiting circuit limiting a second potential difference (V.sub.2) between the data line pair to a threshold level (V.sub.th) of the NMOS transistor or more but lower than the power source potential (V.sub.th .ltoreq.V.sub.2 <V.sub.cc); a second switch connected to the limiting circuit via the data line pair, the second potential difference being transferred via the second switch; and an equalizer connected to the second switch via the data line pair, the equalizer equalizing the data line pair by charging to the power source potential the data line pair, wherein the control signal is set such that he limiting operation of the limiting circuit is not synchronized with the equalization operation of the equalizer.

111. A dynamic random access memory having a plurality of memory cells, data stored in one of the memory cells being amplified and transferred from a bit line pair to a data line pair, the dynamic random access memory comprising: an amplitude limiting circuit consisting of an N channel metal oxide semiconductor (NMOS) transistor having a source directly connected to one of the data line pair, a drain directly connected to the other of the data line pair and a gate to which a first control signal is applied, the NMOS transistor keeping a potential difference between the data lines at a threshold level of the NMOS transistor or more in response to the first control signal; and first, second, and third P channel metal oxide semiconductor (PMOS) transistors, the first and second PMOS transistors having sources connected to a power source, a drain of the first PMOS transistor being connected to one of the data line pair and a drain of the second PMOS transistor being connected to the other of the data line pair, the source of the third PMOS transistor being connected to one of the data line pair and the drain of the third PMOS transistor being connected to the other of the data line pair, the first, second, and third PMOS transistors equalizing the data line pair at a potential supplied by the power source, wherein the first control signal is set such that the amplitude limiting circuit operates to limit the potential difference between the data lines during at least part of an active operating cycle of the dynamic random access memory, and the first control signal is set such that the amplitude limiting operation of the amplitude limiting circuit is not synchronized with the equalization operation of the first, second, and third PMOS transistors.

112. In a semiconductor memory device of the type having: a plurality of memory cells, a plurality of bit line pairs, each having a first and a second bit line, either the first or the second bit line, or both the first and second bit lines being connected to one of the memory cells, a plurality of differential amplifiers connected between the first and second bit lines, a first and a second data line selectively coupled to the first and second bit lines via coupling means, and equalizing means, responsive to a first control signal, for equalizing the data lines by charging the data lines to a predetermined potential, the improvement which comprises: an amplitude limiting circuit consisting of one transistor having a current path and a control electrode, the current path of the transistor being directly connected between the first and second data lines, and the control electrode of the transistor receiving a second control signal, for limiting a potential difference between the first and second data lines to a threshold level of the transistor or more in response to the second control signal, wherein the first control signal is different from and is not synchronized with the second control signal.

113. A semiconductor memory device comprising: a memory cell matrix having: a plurality of memory cells arranged in matrix; a plurality of word lines, each word line being connected to a row of memory cells in the memory cell matrix; and a plurality of bit line pairs each having a first bit line and a second bit line, each bit line pair being connected to a column of memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the first bit lines of the bit line pairs being selectively coupled to the first data line and the second bit lines of the bit line pairs being selectively coupled to the second data line; a first means for precharing the first and the second data lines to a first potential (V); a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth) and including a gate electrode; and a second means for supplying a second potential to the gate electrode of the first NFET for making the first NFET conductive, the second potential being a maximum voltage level (.phi.1.sub.max) that is less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth), wherein a period during which the second means supplies the second potential to the first NFET is not the same as a period during which the first means precharges the first and second data lines.

114. A method for controlling a semiconductor memory, the semiconductor memory of the type having: a memory cell matrix including a plurality of memory cells arranged in matrix, word lines each connected to a row of memory cells in the memory cell matrix, and bit line pairs each connected to a column of memory cells in the memory cell matrix; a first data line pair having a first data line and a second data line, the bit line pairs being selectively coupled to the first data line pair; a precharging circuit; and a first N channel field effect transistor (NFET) directly connected between the first and the second data lines, the first NFET having a threshold voltage (Vth), the method comprising the steps of: precharging the first and the second data lines to a first potential (V); and supplying a second potential (.phi.1.sub.max) to a gate electrode of the first NFET for making the first NFET conductive at least while the first data line pair is being sensed, the second potential being less than the sum of the first potential and the threshold voltage of the first NFET (.phi.1.sub.max <V+Vth), wherein a period during which the second potential is supplied to the gate electrode of the first NFET is not the same as a period during which the first and second data lines are precharged.

115. A semiconductor memory device comprising: a memory cell matrix including: a plurality of memory cells arranged in matrix; and a plurality of bit line pairs, each bit line pair being connected to memory cells from the memory cell matrix; a first data line pair having a first data line and a second data line, the bit line pairs being selectively coupled to the first data line pair; a precharging means for precharging and equalizing the first and the second data lines to a first potential (V); and a limiting circuit consisting of one limiting transistor directly connected between the first data line and the second data line, the limiting transistor having a threshold voltage (Vth) and a gate electrode, wherein a control signal is supplied to the gate electrode of the limiting transistor, one of the bit line pairs is coupled to the first data line pair during an output period of a memory read cycle, the control signal is held at a second potential (.phi.1.sub.max) during the entire output period to keep the limiting circuit activated during the entire output period, thereby limiting the potential difference between the first data line and the second data line to the threshold voltage of the limiting transistor or more during the output period, and a period during which the control signal is held at the second potential is not the same as a period during which the precharging means precharges and equalizes the first and second data lines.