Transmitting/Receiving Signal Processing Circuit in Digital Cordless Telephone

This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. .sctn.119 from an application for TRANSMITTING/RECEIVING SIGNAL PROCESSING CIRCUIT IN DIGITAL CORDLESS TELEPHONE filed in the Korean Industrial property Office 3 Aug. 1994 and assigned Ser. No. 19179/1994.

The present invention relates to a transmitting/receiving signal processing circuit in a digital cordless communication device, and more particularly to a transmitting/receiving signal processing circuit which incorporates a frequency-discrimination demodulator and a frequency synthesized local oscillator comprised of a heterodyne phase locked loop (PLL) for high speed switching.

In the late 1980's and early 1990's, a second generation of digital cordless telephones (CT2) using a frequency division multiple access-time division duplexing (FDMA-TDD) method was introduced. This method has proven to be effective in the field of telecommunications.

In designing transceivers for digital cordless telephones that perform this or other methods of communication, accurate generation of frequencies for signal transmission and reception is always a key concern. Many devices employ one or more phase locked loops (PLL) in order to generate desired frequencies. One such device is disclosed in U.S. application Ser. No. 08/402,506 entitled Transceiver Signal Processor For Digital Cordless Communication Apparatus, assigned to the same assignee as the present invention.

Another device is disclosed in U.S. Pat. No. 5,423,075 entitled Combined Radio Transmission And Reception Apparatus With A PLL Circuit issued to Boese et al. on 6 Jun. 1995. In Boese et al. '075, a transceiver having a transmitting section and a receiving section is provided with a single phase locked loop (PLL) to which the two sections have alternating access. While conventional art such as Boese et al. '075 has merit in its own right, I have learned that an improved device which performs effective high speed frequency switching can be contemplated.

It is therefore an object of the present invention to provide an improved transmitting/receiving signal processing circuit.

It is another object to provide a transmitting/receiving signal processing circuit that can be implemented using commercialized, off-the-shelf components.

It is still another object to provide a transmitting/receiving signal processing circuit that provides improved power efficiency.

It is yet another object to provide a transmitting/receiving signal processing circuit that eliminates frequency drifting.

To accomplish these and other objects, a transmitting/receiving signal processing unit constructed according to the principles of the present invention is provided in a digital cordless telephone device. The transmitting/receiving signal processing unit of the present invention contemplates a transmitting unit for convening a signal input through a speaker, and transmitting the converted signal to a telephone via an antenna in a time division communication system which uses a single frequency channel for transmission and reception according to constant time periods. A receiving unit is also provided for converting a signal received in an antenna, and then transmitting the converted signal to a user. The present invention further includes a frequency synthesizer with a first phase locked loop (PLL) synthesizing a reference transmission frequency for channel conversion; a switching stage providing a local oscillation signal derived from the receiving unit as a heterodyne source in a receiving mode, and providing a signal multiplied by the reference transmission frequency as the heterodyne source in a transmission mode; and a second phase locked loop (PLL) connected between the first phase locked loop (PLL) and the receiving unit, for receiving the heterodyne sources and generating transmission/receiving frequencies in the transmission/receiving modes, respectively.

A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:

FIG. 1 is a block diagram illustrating a conventional transmitting/receiving signal processing circuit using a transmission frequency mixture conversion system in a digital cordless telephone;

FIG. 2 is a block diagram illustrating another conventional transmitting/receiving signal processing circuit using a heterodyne double phase locked loop of a transmitting/receiving frequency conversion system in a digital cordless telephone; and

FIG. 3 is a block diagram illustrating a transmitting/receiving signal processing circuit using a frequency discriminating demodulator and a frequency synthesized local oscillator comprised of a heterodyne single phase locked loop in a digital cordless telephone constructed according to the principles of the present invention.

Turning now to the drawings and referring to FIG. 1, a block diagram of a conventional transmitting/receiving signal processing circuit using a transmission frequency mixture conversion system in a digital cordless telephone is illustrated. GPT Ltd., in England, has adopted the use of this transmitting/receiving signal processing circuit and Motorola, Inc., in the U.S.A., has adopted the use of a circuit that is similar to the circuit represented in FIG. 1.

In FIG. 1, reference numeral 1 designates an antenna, reference numeral 2 designates a bandpass filter (BPF), reference numeral 3 designates a transmitter/receiver switch, reference numeral 4 designates a low-noise receiver amplifier, reference numeral 5 designates a radio frequency bandpass filter, reference numeral 6 designates a first receiver mixer, reference numeral 7 designates a first intermediate frequency (IF) receiver bandpass filter, reference numeral 8 designates a second receiver mixer, reference numeral 9 designates a receiver local oscillator (LO), reference numeral 10 designates a second intermediate frequency (IF) receiver bandpass filter, reference numeral 11 designates an intermediate frequency (IF) amplifier, reference numeral 12 designates a demodulator, reference numeral 13 designates a low-pass filter (LPF), reference numeral 14 designates a data slicer, reference numeral 15 designates a reference frequency crystal oscillator, reference numeral 16 designates a transceiver frequency synthesizer, reference numeral 17 designates a voltage-controlled oscillator (VCO), reference numeral 18 designates a reception buffer amplifier for a reception path, reference numeral 19 designates a transmission buffer amplifier for a transmission path, reference numeral 20 designates a transmitter offset local oscillator, reference numeral 21 designates an amplifier/multiplier stage, reference numeral 22 designates a transmitter offset intermediate frequency (IF) bandpass filter, reference numeral 23 designates a transmitter mixer, reference numeral 24 designates a transmission frequency bandpass filter, and reference numeral 25 designates a transmitter power amplifier.

In the transceiver signal processing circuit shown in FIG. 1, a single phase locked loop (PLL) frequency synthesizer (A) having reference frequency crystal oscillator 15, transceiver frequency synthesizer 16 and voltage-controlled oscillator (VCO) 17 is used as a first local oscillator for both the transmitting and receiving portions of the circuit.

In the transceiver signal processing circuit shown in FIG. 1, however, the maximum phase comparing frequency of the single phase locked loop (PLL) frequency synthesizer (A) can not exceed the frequency difference between channels, with the loop bandwidth being much smaller than that (generally one tenth or below). Accordingly, the locking (stabilizing) time of the loop is rather long since it is inversely proportional to the loop bandwidth. That is to say, since a locking time much greater than the guard time (i.e., the delay time between an FDMA-TDD transmit frame and receive frame) is required, undesirable frequency transients occurring due to load fluctuations between transmission and receiving states cannot be restored (for their subsequent removal) within the guard time. Therefore, the burden placed on buffering amplifiers 18 and 19, which are utilized to improve the isolation performance between the load and oscillator, increases. Accordingly, this arrangement is not suitable for high-frequency circuits and results in lower efficiency.

Since frequency switching is impossible due to the foregoing problems, transmitter mixer 23 mixes the output frequency of second transmitter local oscillator 20 with the transmitter intermediate frequency during transmission to output the required frequency signal. During this process, due to the signal loss in transmitter mixer 23, the gain of transmitter power amplifier 25 should be large. Therefore, power consumption becomes large when a multi-stage transmitter power amplifier is used.

Also, since the output of transmitter mixer 23 includes many harmonics and intermodulation components, multi-stage bandpass filter 24 has high signal loss which causes design problems.

The burden of high-frequency circuitry due to the foregoing problems lowers the integration efficiency of semiconductor circuits and worsens productivity. Furthermore, it is difficult to reduce chip size and cost.

Referring now to FIG. 2, another conventional transceiver signal processing circuit which uses a double phase locked loop (PLL) method for synthesizing the heterodyned transmitter/receiver frequencies in a digital cordless telephone is shown. In FIG. 2, like elements are designated by the same reference numerals as in FIG. 1, and descriptions of these elements will therefore be omitted.

In FIG. 2, reference numeral 26 designates a voltage-varied crystal oscillator, reference numeral 27 designates a first frequency multiplier, reference numeral 28 designates a bandpass filter, reference numeral 29 designates a second frequency multiplier, reference numeral 30 designates a reference frequency crystal oscillator, reference numeral 100 designates a transmitter phase locked loop (PLL), reference numeral 110 designates a receiver phase locked loop (PLL), and reference numeral 200 designates a heterodyning phase locked loop (PLL) for high-speed switching between transmitter and receiver frequencies. Transmitter phase locked loop (PLL) 100 includes a transmitter frequency synthesizer 31, a transmitter voltage-controlled oscillator (VCO) 32, and a buffering amplifier 33. Receiver phase locked loop (PLL) 110 includes a receiver frequency synthesizer 34, a receiver voltage-controlled oscillator (VCO) 35, and a receiver frequency amplifier 36. Heterodyning phase locked loop (PLL) 200 includes: a phase comparator 38, a loop low-pass filter 39, a transceiver voltage-controlled oscillator (VCO) 40, a buffering amplifier 41, a frequency mixer 42, and a low-pass filter 43. Reference numeral 37 designates another transmitter/receiver switch, and reference numeral 44 designates a buffering amplifier.

Since the above heterodyning phase-locked loop (PLL) transceiver uses a frequency discrimination method, in which a frequency is demodulated in demodulator 12 by multiplying a second intermediate frequency (IF) (which can not be 0 Hz) with the second intermediate frequency (IF) phase-shifted by 90 degrees, the offset corresponding to the second intermediate frequency (IF) of the receiver is generated at the required transmitter frequency.

During this time, if the offset is set to 0 Hz, since the signal obtained by multiplying the output signal of voltage-varied crystal oscillator 26 in first frequency multiplier 27 coincides with a first intermediate frequency (IF) of the receiver, which is a weak frequency component, the reception sensitivity is destroyed. Accordingly, it is impossible to set the actual offset to 0 Hz.

Therefore, the transceiver signal processing circuit of FIG. 2 is provided with a separate transmitter phase locked loop (PLL) 100 and receiver phase locked loop (PLL) 110. Frequency signals are provided to heterodyning phase locked loop (PLL) 200 via transmitter/receiver switch 37. During this time, since the two frequency signals are alternately selected by transmitter/receiver switch 37, the same problems as those in the transceiver signal processing circuit of FIG. 1 exist.

Also, since two phase locked loops (PLL) are used, the circuit is complex, and the frequency division rate data of transmitting and receiving channels should be input separately. Moreover, since two frequencies are generated with a spacing equal to the second intermediate frequency (IF) frequency, the transmitter voltage-controlled oscillator (VCO) 32 and receiver voltage-controlled oscillator (VCO) 35 are likely to beat with each other.

Referring now to FIG. 3, a block diagram of a transmitting/receiving signal processing circuit using a frequency discrimination demodulator and a frequency synthesis local oscillator comprised of a heterodyne single phase locked loop (PLL) in a digital cordless telephone constructed according to the principles of the present invention is illustrated.

The elements shown in FIG. 3 may be adopted as a radio frequency (RF) unit, since a digital cordless communication device is divided into a radio frequency (RF) unit and a baseband unit. The transmitting/receiving signal processing circuit of FIG. 3 includes a frequency discriminating demodulator block 101, a first phase locked loop (PLL) 120, a second phase locked loop (PLL) 130, and a switching circuit 54. FIG. 3 further includes an antenna 1, a transmitter/receiver switch 3, a low noise amplifier 4, a band pass filter (BPF) 5, a first receiver mixer 6, a band pass filter (BPF) 7, a low pass filter (LPF) 13, a data slicer 14, a receiver buffer amplifier 18, a low pass filter (LPF) 50, a reference frequency quartz-crystal oscillator 51, a frequency multiplier 52, a band pass filter (BPF) 53, an amplifier 55, a frequency multiplier 56, a band pass filter (BPF) 57, and first and second power amplifiers 400 and 401, respectively.

Frequency discriminating demodulator block 101 includes a first intermediate frequency (IF) amplifier 102, a second intermediate frequency (IF) mixer 103, band pass filters (BPFs) 104 and 106, second intermediate frequency (IF) amplifiers 105 and 107, a multiplier 108, a phase shifter 109, a receiver local oscillator 111, and a frequency multiplier 112.

First phase locked loop (PLL) 120 for converting a channel includes frequency dividers 121 and 125, a phase comparator 122, a low pass filter (LPF) 123, and a voltage-controlled oscillator 124.

Second phase locked loop (PLL) 130 for switching a transmitting/receiving frequency at a high speed includes a phase comparator 136, a low pass filter (LPF) 137, a voltage-controlled ocsillator (VCO) 131, an isolation buffer 132, a mixer 133, a low pass filter (LPF) 134, and an amplifier 135.

Transmitting/receiving switch 3 and switching circuit 54 receive switching control signals C1 and C2 from the baseband unit (not shown), respectively.

In a transmission mode, SW1 of transmitting/receiving switch 3 is connected to second power amplifier 401 in response to a state of switching control signal C1, while SW22 and SW11 of switching circuit 54 are closed and opened, respectively, in response to a state of switching control signal C2.

In a receiving mode, SW1 of transmitting/receiving switch 3 is connected to low noise amplifier 4 to provide a radio frequency (RF) signal from antenna 1. Also during the receiving mode, SW22 and SW11 of switching circuit 54 are opened and closed, respectively.

Accordingly, the output frequency of frequency multiplier 112 received through amplifier 55 is utilized as a heterodyne source of second phase locked loop (PLL) 130 during the receiving mode, thereby simplifying the construction of the radio frequency (RF) unit.

An explanation of the operations of the transmitting/receiving signal processing circuit of FIG. 3 will now be given.

Generally, in a frequency division multiple access and time-division duplex (FDMA-TDD) system providing bilateral communication, the receiver uses a heterodyne system and the transmitter uses an alternating current signaling system in order to generate proper frequencies for transmission and reception modes. The reception and transmission modes are alternately repeated in accordance with a predetermined time period and a given guard time, thereby requiring that the frequency of signals transmitted from voltage-controlled oscillator (VCO) 131 be adjusted to necessary levels for both the reception and transmission modes. In other words, voltage-controlled oscillator (VCO) 131 generates a first frequency for the reception mode and a second frequency for the transmission mode. Accordingly, second phase locked loop (PLL) 130 comprised of voltage-controlled oscillator (VCO) 131 must be capable of being switched at a high speed in order to stabilize the frequency switching operation within a given short guard time.

In the present invention, second phase locked loop (PLL) 130 comprised of phase comparator 136, low pass filter (LPF) 137, voltage-controlled oscillator (VCO) 131, buffer 132, mixer 133, low pass filter (LPF) 134, and amplifier 135 is capable of quickly and effectively switching between transmission and reception mode frequencies. A necessary minimum frequency should be set since a locking time of second phase-locked loop (PLL) 130 is proportional to a reciprocal of the frequency of signals being compared in phase comparator 136.

The output frequency of voltage-controlled oscillator (VCO) 131 in the FDMA-TDD system of the present invention must have a minimum resolution and be carefully controlled, thereby placing limitations on the frequency of signals being compared in phase comparator 136.

In order to produce frequencies having a predetermined difference, the present invention uses first phase locked loop (PLL) 120 for frequency synthesis. First phase locked loop (PLL) 120, which generates a frequency that is not switched, is comprised of frequency dividers 121 and 125, phase comparator 122, low pass filter (LPF) 123, and voltage-controlled oscillator (VCO) 124.

In order to generate a frequency fh to be compared in phase comparator 136 of second phase locked loop (PLL) 130, an output of voltage-controlled oscillator 131 is transmitted through buffer 132 and is mixed with signals in mixer 133. The output of mixer 133 is then filtered in lowpass filter 134, amplified in amplifier 135, and provided to phase comparator 136 where its phase is compared with the phase of an output from first phase locked loop (PLL) 120. Accordingly, second phase locked loop (PLL) 130 is capable of being switched at a high speed.

When the frequency fh represents a desired channel difference, voltage-controlled oscillator 131 generates the transmission or receiving frequency with at least the same resolution as the single phase locked loop frequency synthesizer shown in FIG. 1. The frequency generated from voltage-controlled oscillator 131 is then provided to either first receiver mixer 6 or power amplifiers 400 and 401.

In order to generate the frequency fh, the frequency of the signal output from voltage-controlled oscillator 124 is synthesized with a desired resolution by first phase locked loop (PLL) 120.

For purposes of explanation, assume the following. A frequency generated by reference frequency quartz-crystal oscillator 51 is referred to as f1, frequency multiplier 52 multiplies frequencies by a factor of i, frequency multiplier 56 multiplies frequencies by a factor of m for transmission and by a factor of n for reception, and a radio carrier frequency generated by voltage-controlled oscillator (VCO) 131 for transmission is referred to as fc. A first local oscillation frequency generated for reception by voltage-controlled oscillator (VCO) 131 and provided to first receiver mixer 6 is referred to as f(LO1). A second local oscillation frequency provided to second intermediate frequency mixer 103 from frequency multiplier 112 is referred to as f(LO2). A frequency generated by receiver reference signal generator 111 is referred to as f2, while frequency multiplier 112 multiplies frequencies by a factor of W. The output frequency of voltage-controlled oscillator 124 and amplifier 135 is referred to as fh.

As stated above, voltage-controlled oscillator 131 in second phase locked loop (PLL) 130 is controlled to be oscillated to fc in the transmission mode and to f(LO1) in the receiving mode. The output frequency fh of voltage-controlled oscillator 124 and lowpass amplifier 135 is expressed as follows:

in the transmission mode

in the receiving mode

A first receiver intermediate frequency f(IF1)=fc-f(LO1) or f(IF1)=f(LO1)-fc, while a second receiver intermediate frequency f(IF2)=f(IF1)-f(LO2) or f(IF2)=f(LO2)-f(IF1) where f(LO2)=[(f2)(W)]. Exemplary values for these frequencies and factors are:

fc=864.150-868.050 MHz, (100 kHz steps)

f(LO1)=720.400-724.300 Mhz, (100 kHz steps)

f(LO2)=143.250 MHz

f(IF1)=143.750 MHz

f(IF2)=500 kHz

fh=4.150-8.050 MHz, (100 kHz steps)

f1=86.000 MHz

f2=71.625 MHz

i=2

W=2

m=5 (transmission mode)

n=5 (receiving mode)

Since frequency multiplier 56 includes and uses both multiplying factors n and m, there is no need for a switching operation. Switching circuit 54 is connected between band pass filter (BPF) and multiplier 56 in the transmission mode, and voltage-controlled oscillator 131 oscillates to a frequency band around fc. Switching circuit 54 is connected between amplifier 55 and multiplier 56 in the receiving mode, and voltage-controlled oscillator 131 is adjusted to oscillate to a frequency band around f(LOI).

According to the present invention, a heterodyne source in the transmission mode differs from the heterodyne source in the receiving mode, thereby fundamentally removing the problem of interference between the transmission and the reception modes. Frequency multiplier 56, buffer 132, and mixer 133 in which a high frequency of the heterodyne loop is inserted, serve to lower only the frequency fh, so that the present invention can reduce power consumption and be easily constructed.

The transmitting/receiving signal processing circuit constructed according to the principles of the present invention employs the heterodyne loop in order to improve power efficiency and solve the problem of frequency drifting. The heterodyne source from frequency discriminating demodulator 101 is applied in the receiving mode, and the heterodyne source from reference frequency quartz-crystal oscillator 51 is applied in the transmission mode, thereby enabling use of a single reference loop. Therefore, since there is no need to switch the reference loop itself, there is an advantage in that the problem of frequency drifting can be fundamentally removed. Also, the single reference loop does not generate intermodulation components, as compared to a plurality of reference loops.

In addition, the single reference loop is easily implemented by using a commercialized, off-the-shelf, component. Also, integration of the demodulator function and the single reference loop function into a single chip is not difficult since interference between the two loops is essentially removed, and all necessary frequencies can be produced with only reference frequency quartz-crystal oscillator 51 during the transmission mode. As a result, there is an advantage in that the frequency can be adjusted well. Generally, a frequency error of the transmitter can be limited by using corresponding standard regulations.

Finally, there is an advantage in that, since a single reference frequency synthesis loop for channel conversion is used, data inputs are simply and efficiently processed and channel conversion time can be reduced. Accordingly, power consumption during a standby for the receiving mode is reduced.

While there have been illustrated and described what are considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. In addition, many modifications may be made to adapt a particular situation to the teaching of the present invention without departing from the central scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the present invention, but that the present invention includes all embodiments falling within the scope of the appended claims.