Vertical Filter Circuit for PIP Function

1. Field of the Invention

This invention relates to a vertical filter circuit for a picture in picture (PIP) function and, more particularly, to a vertical filter circuit for constructing a sub-screen when the input signal of a main screen is a double-scanned signal or a HDTV signal.

2. Brief Discussion of Related Art

Generally, a PIP function is used for simultaneously displaying image signals of both the main screen and a sub-screen by horizontally and vertically compressing the sub-screen image signal. It will be appreciated that image signals of the same or different broadcasting channels may be displayed on the main and sub-screens. An image signal reproduced from an image recording/reproducing apparatus (VCR) be also displayed on the main screen, while the image signal of a broadcast channel can be displayed on the sub-screen with the size and position of the sub-screen being varied by a user.

The sub-screen for the PIP is processed as a digital signal. The data amount in the sub-screen of a predetermined size, i.e., a typical size ratio of sub-screen to main screen is 1 to 9, should be compressed into a predetermined amount corresponding to this ratio.

It will be noted that horizontal signal components of the sub-screen can be compressed into one third by setting the analog-to-digital (A/D) conversion clock frequency to one third of the digital-to-analog (D/A) conversion clock frequency. Moreover, vertical signal components of the sub-screen can be compressed into one third of the data amount of that of the main screen by reducing the number of scanning lines to one third. Accordingly, the data amount of the sub-screen can be compressed into one ninth of that of the main screen.

However, since a low sampling frequency is used for generating the abovedescribed sub screen, the video signal frequency must be restricted. Moreover, since the direction of the horizontal signal and the direction of the scanning line coincide with each other, the horizontal signal is continuous. To restrict the frequency band of the continuous signal, a low pass filtering must be performed before the A/D conversion. It will be noted that, when the vertical signal and the scanning line cross each other, the vertical signal becomes digitalized (discontinuous). The frequency band of this discontinuous signal cannot be restricted by present day analog technology. Therefore, to restrict the frequency band of the vertical signal, a digital filter called a vertical digital filter (hereinafter referred to as vertical filter) was designed. FIGS. 1 to 4F are useful in understanding the construction and operation of a typical vertical filter.

FIG. 1 illustrates a method for constructing the PIP sub-screen using a general interlace scanning signal. One line of PIP sub-screen data is generated for every third line of the image date per field.

A vertical filter is needed to remove or suppress a flicker phenomenon caused by a shortage in the number of vertical lines, i.e., so-called aliasing error. This is accomplished by restricting the frequency band of the discontinuous vertical signal. A high level diagram of the vertical filter is shown in FIG. 2, a more detailed example is shown in FIG. 3. This vertical filter technology used for providing PIP functions is described by Masashi Honzawa et al. in the article entitled "New Picture in Picture LSI Enhanced Functionality for High Picture Quality," in IEEE Transaction on Consumer Electronics, Vol. 36, No. 3, August, 1990.

Referring to FIG. 2, the vertical filter includes a three tap finite impulse response (FIR) filter adapted for vertical filtering and constructed using two 1H line memories 1 and 2, three multipliers 3, 4 and 5, and an adder 6. FIG. 3 illustrates a modified vertical filter. The modified filter uses only one 1H line memory 15 but performs the same function as the vertical filter circuit shown in FIG. 2. This is possible because only one significant line of the three lines of main screen data are necessary for compressing the sub-screen data.

The operation of the circuit shown in FIG. 3 will be described with respect to the waveforms shown in FIGS. 4A to 4F, wherein control signals CTL1 to CTL4 (shown in FIGS. 4B to 4E) are varied every third horizontal (H) period on the basis of the horizontal synchronous signal of FIG. 4A. These signals are supplied to AND gates 10, 11, 12 and 16 shown in FIG. 3. A final output signal of 1H line memory 15 can extract data (h.sub.2 Z.sup.-2 +h.sub.1 Z.sup.-1 +h.sub.0 Z.sup.0) every 3H period as shown in FIG. 4F.

The above-described vertical filter circuit can only be used for generating the PIP sub-screen when applied to a display device in which the main screen is generated by interlace scanning. When the input signal of main screen is a double-scanned signal or a HDTV signal, the number of scanning lines is increased by two, prohibiting use of the vertical filter.

U.S. Pat. No. 4,768,093 also discloses a vertical filter for PIP. This patent relates to a filter whose length is greater than a decimation factor in a television having a PIP function and which is applied to a general raster scan display device. However, both types of prior art filter cannot be applied to the double-scanned display device or HDTV.

The principal object of the present invention is to overcome the limitations of prior art vertical filters.

It is an object of the present invention to provide a vertical filter circuit for a PIP function, which can be used for constructing a sub-screen when the input signal of a main screen is a double-scanned signal or a HDTV signal.

Another object of the present invention is to provide a vertical filter circuit for a PIP function which has a simple circuit structure for removing the flicker phenomenon caused by a shortage in the number of the vertical lines in a sub-screen when the input signal of a main screen is a double-scanned signal or a HDTV signal.

These and other objects, features and advantages according to the present invention are provided by a vertical filter circuit for a PIP function, for generating a sub-screen when the input signal of a main screen is a double-scanned signal or a HDTV signal. Preferably, the vertical filter circuit incudes a line delaying device acting as means for delaying the input signal for 1H period, a first signal generator for generating a first horizontal line signal of the sub-screen by summing the signal of the first 2H period, passed through the line delaying device after multiplying the respective input signal which is selected by 1H every 3H period by predetermined coefficients, and a signal of a third horizontal line interval which is multiplied by a predetermined coefficient, a second signal generator for generating a second horizontal line signal of the sub-screen by summing the signal of the third horizontal line interval, passed through the line delaying device every 3H period, and the signal of next horizontal line interval, multiplied by a predetermined coefficient, and a control signal generator which is reset by a vertical synchronous signal and which generates a plurality of control signals by counting a horizontal synchronous signal as selection control signals of the first and second signal generators.

The above objects and advantages of the present invention will become more apparent by reference to the attached drawings in which:

FIG. 1 is a diagram illustrating a method for constructing a PIP sub-screen by using a general interlace scanning signal;

FIG. 2 is a diagram illustrating the concept of a vertical filter circuit for constructing a PIP sub-screen using the method shown in FIG. 1;

FIG. 3 is a block diagram showing a modified form of the vertical filter circuit shown in FIG. 2;

FIGS. 4A to 4F are waveforms of input and output signals of each portion of the vertical filter circuit shown in FIG. 3;

FIG. 5 is a diagram illustrating a general method for constructing a PIP sub-screen using a double-scanned signal or HDTV signal;

FIG. 6 is a diagram illustrating the concept of a vertical filter circuit for constructing a PIP sub-screen using the method shown in FIG. 5;

FIG. 7 is a circuit diagram of a vertical filter circuit for a PiP function according to a preferred embodiment of the present invention;

FIGS. 8A to 8I are waveforms of input and output signals of each portion of the vertical filter circuit shown in FIG. 7;

FIG. 9 is a circuit diagram of a vertical filter circuit for a PIP function according to another preferred embodiment of the present invention; and

FIGS. 10A to 10K are waveforms of input and output signals of each portion of the vertical filter circuit shown in FIG. 9.

When a main screen is compressed into a predetermined ratio (generally, in the ratio of one third vertically and horizontally, respectively) for constructing a PIP sub-screen, the compression method must be varied according to the compression direction, i.e., horizontal or vertical. That is, for horizontal compression, the compression is generally performed by lowering a sampling frequency after performing a low pass filtering at an analog signal band. For vertical compression, the compression is performed by selecting only a part of lines since the number of lines are fixed.

In the case where the input signal of the main and sub-screens are interlace scanning signals, e.g., NTSC signals, the number of vertical lines should be reduced to one third as described in the prior art, if the sub-screen whose area corresponds to one ninth of that of the main screen is desired. However, in the case where the input signal of the main screen is a double-scanned signal or HDTV signal, the number of vertical lines in the original screen should be reduced by two thirds since the number of lines should be halved in comparison with the interlaced scanning signal to reduce the area of sub-screen to one ninth of that of the main screen.

When the number of the vertical lines are reduced, an aliasing error is generated. Thus, a vertical low pass filtering process should be performed via the vertical filter circuit before reducing the number of vertical lines so as to remove the aliasing error.

FIG. 5 is a diagram for illustrating a method for constructing a PIP sub-screen, wherein the input signal of the main screen is a double-scanned signal or HDTV signal. The PIP sub-screen for the double-scanning device or HDTV can be constructed by selecting two among three lines within one field.

To reduce the number of vertical lines to two-thirds, a low pass filtering should be performed every 3H period by constructing two different filters so as to obtain the output such as 1 and 2 shown in FIG. 5.

FIG. 6 is a diagram for illust,rating the concept of the vertical filter circuit for constructing the PIP sub-screen when the input signal of the main screen is a double-scanned signal or a HDTV signal. The circuit is composed of three line memories 21, 23 and 25, five multipliers 27, 29, 31, 33 and 35, and two adders 37 and 39.

Advantageously, 1H line memory 21, multipliers 27 and 29 and adder 37 compose a two tap filter, while 1H line memories 21, 23 and 25, multipliers 31, 33 and 35 and adder 39 compose a three tap filter. That is, when a first output H.sub.1 (Z) and a second output H.sub.2 (7) are repeatedly taken once every three lines, the output whose number of vertical lines is reduced to two thirds of the original screen can be obtained. Output H.sub.1 (Z) has a transfer function characteristic shown in formula (1), i.e., output of the three tap filter, and output H.sub.2 (Z) has a transfer function characteristic shown in formula (2), i.e., output of the two tap filter.

However, since the vertical filter employs three 1H line memories 21, 23 and 25, it is difficult to create an integrated circuit (IC) without increasing the size of the hardware. Accordingly, the vertical filter circuit according to the present invention is designed to perform the same function as that of the circuit shown in FIG. 6 but using only one 1H line memory.

FIG. 7 is a circuit diagram of a vertical filter circuit for a PIP function according to a preferred embodiment of the present invention. The vertical filter circuit includes a timing controller 51, which is reset by a vertical synchronous signal/V.sub.sync and which generates the first to sixth clock signals CTL1 to CTL6. This is accomplished by counting a horizontal synchronous signal/H.sub.sync. First to fifth multipliers 41, 43, 45, 47, and 49 multiply the input image signal by each of coefficients h.sub.2, h.sub.1, h.sub.0, h.sub.4 and h.sub.3, respectively. First to third AND gates 53, 55 and 57 logically multiply the output signals of first to third multipliers 41, 43 and 45 by first to third control signals CTL1 to CTL3. Preferably, OR gate 59 logically sums the output signals of first to third AND gates 53, 55 and 57. 1H line memory 65 delays the input signal provided via a first adder 61 and/or a first switch 63 for 1H period. A fourth AND gate 67 logically multiplies CTL4 by the output signal of 1H line memory 65. First adder 61 sums the output signal of OR gate 59 and the output signal of fourth AND gate 67. First switch 63 selectively switches the output signal of first adder 61 or the output signal of fourth multiplier 47 according to CTL5 and outputs the result to 1H line memory 65. A second adder 69 sums the output signal of 1H line memory 65 and the output signal of fifth multiplier 49. A second switch 71 selectively switches the output signal of first adder 61 or the output signal of second adder 69 according to CTL6 and continuously outputs the three tap filter signal and two tap filter signal every 3H period.

FIGS. 8A to 8I are waveforms of input and output signals of the vertical filter circuit shown in FIG. 7. FIG. 8A represents/H.sub.sync signal, FIGS. 8B to 8G represent control signals CTL1 to CTL6 output from timing controller 51, FIG. 8H represents the input signal of 1H line memory 65, and FIG. 8I represents the output signal of second switch 71.

The operation of the vertical filter circuit for a PIP function shown in FIG. 7 will be described with reference to the waveforms of FIGS. 8A to 8I. In FIG. 7, timing controller 51 is cleared by vertical synchronous signal/V.sub.sync and generates control signals CTL1 to CTL6 shown in FIG. 8B to FIG. 8G by counting horizontal synchronous signal/H.sub.sync shown in FIG. 8A.

First to third signals CTL1 to CTL3, shown in FIGS. 8B to 8D, are applied to the input terminals of first to third AND gates 53, 55 and 57, respectively. Control signal CTL4, shown in FIG. 8E, is applied to the input terminal of fourth AND gate 67. Control signal CTL5, shown in FIG. 8F, becomes a selection control signal of first switch 63. Control signal CTL6, shown in FIG. 8G, becomes a selection control signal of second switch 71.

In the first horizontal synchronous interval t1, shown in FIG. 8A, control signal CTL1, shown in FIG. 8B, is logical level "1", and control signals CTL2 and CTL3 shown in FIGS. 8C and 8D, are a logical level "0". Thus, the output of OR gate 59 is h.sub.2 X(n), which is the output of first multiplier 41. Fourth and fifth control signals CTL4 and CTL5, shown in FIGS. 8E and 8F, are "0". Thus, first switch 63 selects the output of first adder 61 so that the input signal, shown in FIG. 8H, of 1H line memory 65 is h.sub.2 X(n), which is the output of OR gate 59.

In the second horizontal synchronous interval t2, shown in FIG. 8A, control signal CTL2 is "1" and control signals CTL1 and CTL3 are "0" so that the output of OR gate 59 is hi, which is the output of second multiplier 43. Control signal CTL4 is "1" and control signal CTL5 is "0". Thus, first switch 63 selects the output of first adder 61 so that the input signal, shown in FIG. 8H, of 1H line memory 65 is the summed signal of h.sub.2 X(n+1) 1H-delayed in 1H line memory 65 and h.sub.1 X(n).

In the third horizontal synchronous interval t.sub.3, shown in FIG. 8A, control signal CTL3 is "1" and control signals CTL1 and CTL2 are "0". As a result, the output of OR gate 59 is h.sub.0 X(n), which is the output of third multiplier 45. Control signal CTL4 is "1" so that the output of first adder 61 is the summed signal of h.sub.0 X(n) and the summed signal of h.sub.2 X(n+2) and h.sub.1 X(n+1), which are 1H-delayed in 1H line memory. Control signal CTL6 is "0" so that second switch 71 selects the output of first adder 61, which can be expressed as a transfer function shown in FIG. 8I, that is, h.sub.0 Z.sup.0 +h.sub.1 Z.sup.-1 +h.sub.2 Z.sup.-2. Control signal CTL5 is "1" so that first switch 63 selects the output signal of fourth multiplier 47. As a result, h.sub.4 X(n), shown in FIG. 8H, is input to 1H line memory 65.

In the fourth horizontal synchronous interval t4, shown in FIG. 8A, control signal CTL5 is "0" and control signal CTL2 and CTL3 are "0". Therefore, the operation to the input terminal of 1H line memory 65 is the same as that in the first horizontal synchronous interval t1. That is, the input signal shown in FIG. 8H of 1H line memory 65 is h.sub.2 X(n), the output of OR gate 59. On the other hand, control signal CTL6 is "1" so that second switch selects the output of second adder 69. Here, the output of second adder 69 is the summed signal of h.sub.4 X(n+1) 1H-delayed in 1H line memory 65 and h.sub.3 X(n). The output can be expressed as the transfer function shown in FIG. 8I, that is, h.sub.3 Z.sup.0 +h.sub.4 Z.sup.-1.

In the fifth horizontal synchronous interval t5, shown in FIG. 8A, the output is the same as that in the second horizontal synchronous interval t2. In the sixth horizontal synchronous interval t6, shown in FIG. 8A, the output is the same as that in the third horizontal synchronous interval t3. The output has the transfer characteristic of h.sub.0 Z.sup.0 +h.sub.1 Z.sup.-1 +h.sub.2 Z.sup.-2 every third horizontal line interval and of h.sub.3 Z.sup.0 +h.sub.4 Z.sup.-3 for the next horizontal line interval. This is shown in FIGS. 8H and 8I.

FIG. 9 is a circuit diagram of a vertical filter circuit for a PIP function according to another preferred embodiment of the present invention. More specifically, FIG. 9 illustrates a vertical filter circuit which is composed of first to fifth multipliers 73, 75, 77, 79 and 81 which multiply the input signal by respective predetermined coefficients. A timing controller 107, which is cleared by a vertical synchronous signal/V.sub.sync, generates control signals CTL1 to CTL8. This is accomplished by counting horizontal synchronous signal/H.sub.sync. First to fifth AND gates 83, 85, 87, 89 and 91 logically multiply the output signals of first to fifth multipliers 73, 75, 77, 79 and 81 by control signal CTL1 to CTL5. A first adder 93 logically sums the output signals of first to fifth and gates 83, 85, 87, 89 and 91. Preferably, 1H line memory 99 delays the input signal for 1H period. A sixth AND gates 101 logically multiplies the output of 1H line memory 99 by control signal CTL6. A second adder 95 sums the output signal of first adder 93 and the output signal of sixth AND gate 101. A first switch 97 selectively switches the output signal of a second adder 95 or the output signal of fifth multiplier 81 according to control signal CTL7 and outputs the result to 1H line memory 99. A third adder 103 sums the output signal of 1H line memory 99 and the output signal of fifth multiplier 81. A second switch 105 selectively switches the output signal of second adder 95 or the output signal of third adder 104 according to control signal CTL8.

FIGS. 10A to 10K are waveforms of input and output signals of the vertical filter circuit shown in FIG. 9. FIG. 10A represents/H.sub.sync signal, FIGS. 10B to 10I represent control signals CTL1 to CTL8 output from timing controller 107, FIG. 10J represents the input signal of 1H line memory 99, and FIG. 10K represents the output signal of second switch 105.

The operation of the vertical filter circuit for a PIP function shown in FIG. 9 according to a preferred embodiment of the present invention will be described with reference to FIGS. 10A to 10K. In FIG. 9, the coefficients of first to fifth multipliers 73, 75, 77, 79 and 81 are fixed as 1/32,-1/16, 1/8, 1/4 and 1/2, respectively. Timing controller 107 generates control signals CTL1 to CTL8 (shown in FIGS. 10B to 10I) by counting horizontal synchronous signal/H.sub.sync (shown in FIG. 10A) and applies the result to each portion. Control signals CTL1 to CTL5 are applied to first to fifth AND gates 83, 85, 87, 87 and 91, respectively, and the output of the multipliers are output only through AND gates to which a "high" control signal is applied.

Control signal CTL6 is applied to the input terminal of sixth AND gate 101. Control signal CTL7 becomes the selection control signal of first switch 97 and control signal CTL8 becomes the selection control signal of second switch 105.

In the first horizontal synchronous interval t1 (shown in FIG. 10A), control signals CTL3 and CTL8 (shown in FIGS. 10B, 10D and 10I) are "1", and control signals CTL2, CTL4, CTL5, CTL6 and CTL7 (shown in FIGS. 10C, 10E to 10H) are "0". Therefore, the input of 1H line memory 99 is the summed signal of the outputs of first and third AND gates 83 and 87, that is, 1/32X(n)+1/8X(n). The value is expressed as the transfer function of 5/32Z.sup.0.

In the second horizontal synchronous interval t2 control signals CTL4, CTL5 and CTL6 are "1" and control signals CTL1, CTL3, CTL7 and CTL8 are "0". Therefore, the input of 1H line memory 99 is the summed signal of the value of 5/32X(n+1), which is 1H-delayed and the outputs-1/16X(n), 1/4X(n) and 1/2X(n) of second, fourth and fifth AND gates 85, 89 and 91. The value is expressed as the transfer function of 22/32Z.sup.0 +5/32Z.sup.-1.

In the third horizontal synchronous interval t3, control signals CTL1, CTL3, CTL6 and CTL7 are "1", and control signals CTL2, CTL4, CTL5 and CTL8 are "0". Therefore, the input of 1H line memory 99 is the output signal of fifth multiplier 81, that is, 1/2X(n). The value is expressed as the transfer function of 1/2Z.sup.0. The output H.sub.1 (Z) of second switch 105 is a signal from second adder 95. That is, summed signal of the value of 22/32X(n+2)+5/32X(n+1), which is 1H-delayed, and the outputs 1/32X(n) and 1/8X(n) of first and third AND gates 83 and 87. The value can be expressed as the transfer function shown in formula (3).

In the fourth horizontal synchronous interval t4, the input of 1H line memory 99 is 5/32Z.sup.0, which is the same as that in the third horizontal synchronous interval, and the output H.sub.z (Z) of second switch 105 is a signal from third adder 103. This signal is the summed signal of the value of 1/2X(n+1), which is 1H-delayed, and the output 1/2X(n) of fifth AND gate 81. The value can be expressed as the transfer function shown in formula (4).

In the fifth horizontal synchronous interval t5, the input of 1H line memory 99 is the same as that in the second horizontal synchronous interval t2. In the sixth horizontal synchronous interval t6, the input of 1H line memory 99 and the output of second switch 105 are the same as those in the third horizontal synchronous interval t3.

After the output of three tap .filter is output every 3H period, the output of two tap filter is output for the next horizontal synchronous interval.

According to the preferred embodiment shown in FIG. 7, when coefficients h.sub.0 to h.sub.4 of the multipliers 41, 43, 45, 47, and 49 are fixed to be proper for a system, the coefficients of first and second outputs H.sub.1 (Z) and H.sub.2 (Z) are fixed as predetermined values, as shown in formulas (1) and (2). However, according to a preferred embodiment shown in FIG. 9, when CTL1 to CTL6 output from the timing controller, the coefficients of first and second outputs shown in formulas (3) and (4) can be varied to be proper for the system.

As described above, the vertical filter circuit for a PIP function, according to the present invention, can be applied for constructing a sub-screen when the input signal of main screen is a double-scanned signal or a HDTV signal. This can be obtained by using one line memory, so that a flicker phenomenon, caused by a shortage in the number of the vertical lines in the sub-screen, can be avoided while the hardware can be simplified to thereby reduce manufacturing costs.

Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure and teachings. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.